From patchwork Fri Nov 13 14:51:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11903715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CEA0C4742C for ; Fri, 13 Nov 2020 14:52:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30CEA21D79 for ; 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Fri, 13 Nov 2020 07:52:22 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 13 Nov 2020 07:52:20 -0700 From: Lars Povlsen To: Linus Walleij Subject: [PATCH v10 1/3] dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver Date: Fri, 13 Nov 2020 15:51:49 +0100 Message-ID: <20201113145151.68900-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201113145151.68900-1-lars.povlsen@microchip.com> References: <20201113145151.68900-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201113_095225_990005_BAF170D0 X-CRM114-Status: GOOD ( 16.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Belloni , Rob Herring , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , linux-gpio@vger.kernel.org, Andy Shevchenko , Lars Povlsen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds DT bindings for the Microsemi/Microchip SGPIO controller, bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and mscc,luton-sgpio. Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring --- .../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml new file mode 100644 index 000000000000..08325bf77a81 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi/Microchip Serial GPIO controller + +maintainers: + - Lars Povlsen + +description: | + By using a serial interface, the SIO controller significantly extend + the number of available GPIOs with a minimum number of additional + pins on the device. The primary purpose of the SIO controllers is to + connect control signals from SFP modules and to act as an LED + controller. + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - microchip,sparx5-sgpio + - mscc,ocelot-sgpio + - mscc,luton-sgpio + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + microchip,sgpio-port-ranges: + description: This is a sequence of tuples, defining intervals of + enabled ports in the serial input stream. The enabled ports must + match the hardware configuration in order for signals to be + properly written/read to/from the controller holding + registers. Being tuples, then number of arguments must be + even. The tuples mast be ordered (low, high) and are + inclusive. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "low" indicates start bit number of range + minimum: 0 + maximum: 31 + - description: | + "high" indicates end bit number of range + minimum: 0 + maximum: 31 + minItems: 1 + maxItems: 32 + + bus-frequency: + description: The sgpio controller frequency (Hz). This dictates + the serial bitstream speed, which again affects the latency in + getting control signals back and forth between external shift + registers. The speed must be no larger than half the system + clock, and larger than zero. + default: 12500000 + +patternProperties: + "^gpio@[0-1]$": + type: object + properties: + compatible: + const: microchip,sparx5-sgpio-bank + + reg: + description: | + The GPIO bank number. "0" is designates the input pin bank, + "1" the output bank. + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: | + Specifies the pin (port and bit) and flags. Note that the + SGIO pin is defined by *2* numbers, a port number between 0 + and 31, and a bit index, 0 to 3. The maximum bit number is + controlled indirectly by the "ngpios" property: (ngpios/32). + const: 3 + + ngpios: + description: The numbers of GPIO's exposed. This must be a + multiple of 32. + minimum: 32 + maximum: 128 + + required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - ngpios + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - microchip,sgpio-port-ranges + - "#address-cells" + - "#size-cells" + +examples: + - | + sgpio2: gpio@1101059c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x1101059c 0x100>; + microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; + bus-frequency = <25000000>; + sgpio_in2: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out2: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; From patchwork Fri Nov 13 14:51:50 2020 Content-Type: text/plain; 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Fri, 13 Nov 2020 07:52:28 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 13 Nov 2020 07:52:26 -0700 From: Lars Povlsen To: Linus Walleij Subject: [PATCH v10 2/3] pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO Date: Fri, 13 Nov 2020 15:51:50 +0100 Message-ID: <20201113145151.68900-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201113145151.68900-1-lars.povlsen@microchip.com> References: <20201113145151.68900-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201113_095232_063373_BE0935E1 X-CRM114-Status: GOOD ( 22.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Belloni , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , linux-gpio@vger.kernel.org, Andy Shevchenko , Lars Povlsen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO (SGPIO) device used in various SoC's. The driver is added as a pinctrl driver, albeit only having just GPIO support currently. The hardware supports other functions that will be added following. Signed-off-by: Lars Povlsen --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 16 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-microchip-sgpio.c | 709 ++++++++++++++++++++++ 4 files changed, 727 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-microchip-sgpio.c diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..75a00dfa824a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2117,6 +2117,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported T: git git://github.com/microchip-ung/linux-upstream.git F: arch/arm64/boot/dts/microchip/ +F: drivers/pinctrl/pinctrl-microchip-sgpio.c N: sparx5 ARM/MIOA701 MACHINE SUPPORT diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 815095326e2d..9b8ed7516355 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -374,6 +374,22 @@ config PINCTRL_OCELOT select OF_GPIO select REGMAP_MMIO +config PINCTRL_MICROCHIP_SGPIO + bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + depends on HAS_IOMEM + select GPIOLIB + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + help + Support for the serial GPIO interface used on Microsemi and + Microchip SoC's. By using a serial interface, the SIO + controller significantly extends the number of available + GPIOs with a minimum number of additional pins on the + device. The primary purpose of the SIO controller is to + connect control signals from SFP modules and to act as an + LED controller. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f53933b2ff02..c9fcfafc45c7 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o +obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-y += actions/ diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c new file mode 100644 index 000000000000..d6c31cc7678e --- /dev/null +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Microsemi/Microchip SoCs serial gpio driver + * + * Author: Lars Povlsen + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinconf.h" + +#define SGPIO_BITS_PER_WORD 32 +#define SGPIO_MAX_BITS 4 +#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ + +enum { + REG_INPUT_DATA, + REG_PORT_CONFIG, + REG_PORT_ENABLE, + REG_SIO_CONFIG, + REG_SIO_CLOCK, + MAXREG +}; + +enum { + SGPIO_ARCH_LUTON, + SGPIO_ARCH_OCELOT, + SGPIO_ARCH_SPARX5, +}; + +struct sgpio_properties { + int arch; + u8 regoff[MAXREG]; +}; + +#define SGPIO_LUTON_AUTO_REPEAT BIT(5) +#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) +#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) +#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) + +#define SGPIO_OCELOT_AUTO_REPEAT BIT(10) +#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) +#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) +#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) + +#define SGPIO_SPARX5_AUTO_REPEAT BIT(6) +#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) +#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) +#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) + +const struct sgpio_properties properties_luton = { + .arch = SGPIO_ARCH_LUTON, + .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, +}; + +const struct sgpio_properties properties_ocelot = { + .arch = SGPIO_ARCH_OCELOT, + .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, +}; + +const struct sgpio_properties properties_sparx5 = { + .arch = SGPIO_ARCH_SPARX5, + .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, +}; + +static const char * const functions[] = { "gpio" }; + +struct sgpio_bank { + struct sgpio_priv *priv; + bool is_input; + struct gpio_chip gpio; + struct pinctrl_desc pctl_desc; +}; + +struct sgpio_priv { + struct device *dev; + struct sgpio_bank in; + struct sgpio_bank out; + u32 bitcount; + u32 ports; + u32 clock; + u32 __iomem *regs; + const struct sgpio_properties *properties; +}; + +struct sgpio_port_addr { + u8 port; + u8 bit; +}; + +static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, + struct sgpio_port_addr *addr) +{ + addr->port = pin / priv->bitcount; + addr->bit = pin % priv->bitcount; +} + +static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) +{ + u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + + return readl(reg); +} + +static inline void sgpio_writel(struct sgpio_priv *priv, + u32 val, u32 rno, u32 off) +{ + u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + + writel(val, reg); +} + +static inline void sgpio_clrsetbits(struct sgpio_priv *priv, + u32 rno, u32 off, u32 clear, u32 set) +{ + u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + u32 val = readl(reg); + + val &= ~clear; + val |= set; + + writel(val, reg); +} + +static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) +{ + int width = priv->bitcount - 1; + u32 clr, set; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + clr = SGPIO_LUTON_PORT_WIDTH; + set = SGPIO_LUTON_AUTO_REPEAT | + FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); + break; + case SGPIO_ARCH_OCELOT: + clr = SGPIO_OCELOT_PORT_WIDTH; + set = SGPIO_OCELOT_AUTO_REPEAT | + FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); + break; + case SGPIO_ARCH_SPARX5: + clr = SGPIO_SPARX5_PORT_WIDTH; + set = SGPIO_SPARX5_AUTO_REPEAT | + FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); + break; + default: + return; + } + sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); +} + +static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) +{ + u32 clr, set; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + clr = SGPIO_LUTON_CLK_FREQ; + set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); + break; + case SGPIO_ARCH_OCELOT: + clr = SGPIO_OCELOT_CLK_FREQ; + set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); + break; + case SGPIO_ARCH_SPARX5: + clr = SGPIO_SPARX5_CLK_FREQ; + set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); + break; + default: + return; + } + sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); +} + +static void sgpio_output_set(struct sgpio_priv *priv, + struct sgpio_port_addr *addr, + int value) +{ + unsigned int bit = SGPIO_SRC_BITS * addr->bit; + u32 clr, set; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); + set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); + break; + case SGPIO_ARCH_OCELOT: + clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); + set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); + break; + case SGPIO_ARCH_SPARX5: + clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); + set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); + break; + default: + return; + } + sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); +} + +static int sgpio_output_get(struct sgpio_priv *priv, + struct sgpio_port_addr *addr) +{ + u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); + unsigned int bit = SGPIO_SRC_BITS * addr->bit; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); + break; + case SGPIO_ARCH_OCELOT: + val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); + break; + case SGPIO_ARCH_SPARX5: + val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); + break; + default: + val = 0; + break; + } + return !!(val & BIT(bit)); +} + +static int sgpio_input_get(struct sgpio_priv *priv, + struct sgpio_port_addr *addr) +{ + return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); +} + +static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + u32 param = pinconf_to_config_param(*config); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + int val; + + sgpio_pin_to_addr(priv, pin, &addr); + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + val = bank->is_input; + break; + + case PIN_CONFIG_OUTPUT_ENABLE: + val = !bank->is_input; + break; + + case PIN_CONFIG_OUTPUT: + if (bank->is_input) + return -EINVAL; + val = sgpio_output_get(priv, &addr); + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, val); + + return 0; +} + +static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + int cfg, err = 0; + u32 param, arg; + + sgpio_pin_to_addr(priv, pin, &addr); + + for (cfg = 0; cfg < num_configs; cfg++) { + param = pinconf_to_config_param(configs[cfg]); + arg = pinconf_to_config_argument(configs[cfg]); + + switch (param) { + case PIN_CONFIG_OUTPUT: + if (bank->is_input) + return -EINVAL; + sgpio_output_set(priv, &addr, arg); + break; + + default: + err = -ENOTSUPP; + } + } + + return err; +} + +static const struct pinconf_ops sgpio_confops = { + .is_generic = true, + .pin_config_get = sgpio_pinconf_get, + .pin_config_set = sgpio_pinconf_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) +{ + return 1; +} + +static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return functions[0]; +} + +static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned *const num_groups) +{ + *groups = functions; + *num_groups = ARRAY_SIZE(functions); + + return 0; +} + +static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + return 0; +} + +static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + return (input == bank->is_input) ? 0 : -EINVAL; +} + +static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(priv, offset, &addr); + + if ((priv->ports & BIT(addr.port)) == 0) { + dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", + addr.port, addr.bit); + return -EINVAL; + } + + return 0; +} + +static const struct pinmux_ops sgpio_pmx_ops = { + .get_functions_count = sgpio_get_functions_count, + .get_function_name = sgpio_get_function_name, + .get_function_groups = sgpio_get_function_groups, + .set_mux = sgpio_pinmux_set_mux, + .gpio_set_direction = sgpio_gpio_set_direction, + .gpio_request_enable = sgpio_gpio_request_enable, +}; + +static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + return bank->pctl_desc.npins; +} + +static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + return bank->pctl_desc.pins[group].name; +} + +static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); + + *pins = &bank->pctl_desc.pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops sgpio_pctl_ops = { + .get_groups_count = sgpio_pctl_get_groups_count, + .get_group_name = sgpio_pctl_get_group_name, + .get_group_pins = sgpio_pctl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + + /* Fixed-position function */ + return bank->is_input ? 0 : -EINVAL; +} + +static int microchip_sgpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + + /* Fixed-position function */ + if (bank->is_input) + return -EINVAL; + + sgpio_pin_to_addr(priv, gpio, &addr); + + sgpio_output_set(priv, &addr, value); + + return 0; +} + +static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + + return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static void microchip_sgpio_set_value(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + microchip_sgpio_direction_output(gc, gpio, value); +} + +static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + struct sgpio_priv *priv = bank->priv; + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(priv, gpio, &addr); + + return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); +} + +static int microchip_sgpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + struct sgpio_bank *bank = gpiochip_get_data(gc); + struct sgpio_priv *priv = bank->priv; + int pin; + + /* + * Note that the SGIO pin is defined by *2* numbers, a port + * number between 0 and 31, and a bit index, 0 to 3. + */ + if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || + gpiospec->args[1] > priv->bitcount) + return -EINVAL; + + pin = gpiospec->args[1] + gpiospec->args[0] * priv->bitcount; + + if (pin > gc->ngpio) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[2]; + + return pin; +} + +static int microchip_sgpio_get_ports(struct sgpio_priv *priv) +{ + const char *range_property_name = "microchip,sgpio-port-ranges"; + struct device *dev = priv->dev; + u32 range_params[64]; + int i, nranges, ret; + + /* Calculate port mask */ + nranges = device_property_count_u32(dev, range_property_name); + if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { + dev_err(dev, "%s port range: '%s' property\n", + nranges == -EINVAL ? "Missing" : "Invalid", + range_property_name); + return -EINVAL; + } + + ret = device_property_read_u32_array(dev, range_property_name, + range_params, nranges); + if (ret) { + dev_err(dev, "failed to parse '%s' property: %d\n", + range_property_name, ret); + return ret; + } + for (i = 0; i < nranges; i += 2) { + int start, end; + + start = range_params[i]; + end = range_params[i + 1]; + if (start > end || end >= SGPIO_BITS_PER_WORD) { + dev_err(dev, "Ill-formed port-range [%d:%d]\n", + start, end); + } + priv->ports |= GENMASK(end, start); + } + + return 0; +} + +static int microchip_sgpio_register_bank(struct device *dev, + struct sgpio_priv *priv, + struct fwnode_handle *fwnode, + int bankno) +{ + struct pinctrl_pin_desc *pins; + struct pinctrl_desc *pctl_desc; + struct pinctrl_dev *pctldev; + struct sgpio_bank *bank; + struct gpio_chip *gc; + u32 ngpios; + int i, ret; + + /* Get overall bank struct */ + bank = (bankno == 0) ? &priv->in : &priv->out; + bank->priv = priv; + + if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { + dev_info(dev, "failed to get number of gpios for bank%d\n", + bankno); + ngpios = 64; + } + + priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; + if (priv->bitcount > SGPIO_MAX_BITS) { + dev_err(dev, "Bit width exceeds maximum (%d)\n", + SGPIO_MAX_BITS); + return -EINVAL; + } + + pctl_desc = &bank->pctl_desc; + pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", + dev_name(dev), + bank->is_input ? "in" : "out"); + pctl_desc->pctlops = &sgpio_pctl_ops; + pctl_desc->pmxops = &sgpio_pmx_ops; + pctl_desc->confops = &sgpio_confops; + pctl_desc->owner = THIS_MODULE; + + pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pctl_desc->npins = ngpios; + pctl_desc->pins = pins; + + for (i = 0; i < ngpios; i++) { + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(priv, i, &addr); + + pins[i].number = i; + pins[i].name = devm_kasprintf(dev, GFP_KERNEL, + "SGPIO_%c_p%db%d", + bank->is_input ? 'I' : 'O', + addr.port, addr.bit); + if (!pins[i].name) + return -ENOMEM; + } + + pctldev = devm_pinctrl_register(dev, pctl_desc, bank); + if (IS_ERR(pctldev)) + return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); + + gc = &bank->gpio; + gc->label = pctl_desc->name; + gc->parent = dev; + gc->of_node = to_of_node(fwnode); + gc->owner = THIS_MODULE; + gc->get_direction = microchip_sgpio_get_direction; + gc->direction_input = microchip_sgpio_direction_input; + gc->direction_output = microchip_sgpio_direction_output; + gc->get = microchip_sgpio_get_value; + gc->set = microchip_sgpio_set_value; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->of_xlate = microchip_sgpio_of_xlate; + gc->of_gpio_n_cells = 3; + gc->base = -1; + gc->ngpio = ngpios; + + ret = devm_gpiochip_add_data(dev, gc, bank); + if (ret) + dev_err(dev, "Failed to register: ret %d\n", ret); + + return ret; +} + +static int microchip_sgpio_probe(struct platform_device *pdev) +{ + int div_clock = 0, ret, port, i, nbanks; + struct device *dev = &pdev->dev; + struct fwnode_handle *fwnode; + struct sgpio_priv *priv; + struct clk *clk; + u32 val; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); + + div_clock = clk_get_rate(clk); + if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) + priv->clock = 12500000; + if (priv->clock == 0 || priv->clock > (div_clock / 2)) { + dev_err(dev, "Invalid frequency %d\n", priv->clock); + return -EINVAL; + } + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + priv->properties = device_get_match_data(dev); + priv->in.is_input = true; + + /* Get rest of device properties */ + ret = microchip_sgpio_get_ports(priv); + if (ret) + return ret; + + nbanks = device_get_child_node_count(dev); + if (nbanks != 2) { + dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); + return -EINVAL; + } + + i = 0; + device_for_each_child_node(dev, fwnode) { + ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); + if (ret) + return ret; + } + + if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { + dev_err(dev, "Banks must have same GPIO count\n"); + return -ERANGE; + } + + sgpio_configure_bitstream(priv); + + val = max(2U, div_clock / priv->clock); + sgpio_configure_clock(priv, val); + + for (port = 0; port < SGPIO_BITS_PER_WORD; port++) + sgpio_writel(priv, 0, REG_PORT_CONFIG, port); + sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); + + return 0; +} + +static const struct of_device_id microchip_sgpio_gpio_of_match[] = { + { + .compatible = "microchip,sparx5-sgpio", + .data = &properties_sparx5, + }, { + .compatible = "mscc,luton-sgpio", + .data = &properties_luton, + }, { + .compatible = "mscc,ocelot-sgpio", + .data = &properties_ocelot, + }, { + /* sentinel */ + } +}; + +static struct platform_driver microchip_sgpio_pinctrl_driver = { + .driver = { + .name = "pinctrl-microchip-sgpio", + .of_match_table = microchip_sgpio_gpio_of_match, + .suppress_bind_attrs = true, + }, + .probe = microchip_sgpio_probe, +}; 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Fri, 13 Nov 2020 07:52:35 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 13 Nov 2020 07:52:33 -0700 From: Lars Povlsen To: Linus Walleij Subject: [PATCH v10 3/3] arm64: dts: sparx5: Add SGPIO devices Date: Fri, 13 Nov 2020 15:51:51 +0100 Message-ID: <20201113145151.68900-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201113145151.68900-1-lars.povlsen@microchip.com> References: <20201113145151.68900-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201113_095236_298034_43A755A0 X-CRM114-Status: GOOD ( 11.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Belloni , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , linux-gpio@vger.kernel.org, Andy Shevchenko , Lars Povlsen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 + .../dts/microchip/sparx5_pcb134_board.dtsi | 258 ++++++++++++++++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 55 ++++ 4 files changed, 409 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 3cb01c39c3c8..f09707297a9f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -226,6 +226,22 @@ si2_pins: si2-pins { function = "si2"; }; + sgpio0_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", + "GPIO_33"; + function = "sg2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; @@ -256,6 +272,81 @@ emmc_pins: emmc-pins { }; }; + sgpio0: gpio@61101036c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101036c 0x100>; + sgpio_in0: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out0: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + + sgpio1: gpio@611010484 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x6 0x11010484 0x100>; + sgpio_in1: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out1: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + + sgpio2: gpio@61101059c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101059c 0x100>; + sgpio_in2: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out2: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 6b2da7c7520c..9baa085d7861 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -69,6 +69,11 @@ spi-flash@9 { }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <0 23>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f37b478d6534..6820579448d0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -36,6 +36,242 @@ gpio-restart { gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "twr0:green"; + gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; + }; + led@1 { + label = "twr0:yellow"; + gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; + }; + led@2 { + label = "twr1:green"; + gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; + }; + led@3 { + label = "twr1:yellow"; + gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; + }; + led@4 { + label = "twr2:green"; + gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; + }; + led@5 { + label = "twr2:yellow"; + gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; + }; + led@6 { + label = "twr3:green"; + gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; + }; + led@7 { + label = "twr3:yellow"; + gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; + }; + led@8 { + label = "eth12:green"; + gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@9 { + label = "eth12:yellow"; + gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@10 { + label = "eth13:green"; + gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@11 { + label = "eth13:yellow"; + gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@12 { + label = "eth14:green"; + gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@13 { + label = "eth14:yellow"; + gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@14 { + label = "eth15:green"; + gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@15 { + label = "eth15:yellow"; + gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@16 { + label = "eth48:green"; + gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@17 { + label = "eth48:yellow"; + gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@18 { + label = "eth49:green"; + gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@19 { + label = "eth49:yellow"; + gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@20 { + label = "eth50:green"; + gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@21 { + label = "eth50:yellow"; + gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@22 { + label = "eth51:green"; + gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@23 { + label = "eth51:yellow"; + gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@24 { + label = "eth52:green"; + gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@25 { + label = "eth52:yellow"; + gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@26 { + label = "eth53:green"; + gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@27 { + label = "eth53:yellow"; + gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@28 { + label = "eth54:green"; + gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@29 { + label = "eth54:yellow"; + gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@30 { + label = "eth55:green"; + gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@31 { + label = "eth55:yellow"; + gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@32 { + label = "eth56:green"; + gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@33 { + label = "eth56:yellow"; + gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@34 { + label = "eth57:green"; + gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@35 { + label = "eth57:yellow"; + gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@36 { + label = "eth58:green"; + gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@37 { + label = "eth58:yellow"; + gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@38 { + label = "eth59:green"; + gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@39 { + label = "eth59:yellow"; + gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@40 { + label = "eth60:green"; + gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@41 { + label = "eth60:yellow"; + gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@42 { + label = "eth61:green"; + gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@43 { + label = "eth61:yellow"; + gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@44 { + label = "eth62:green"; + gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@45 { + label = "eth62:yellow"; + gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@46 { + label = "eth63:green"; + gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@47 { + label = "eth63:yellow"; + gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; }; &spi0 { @@ -70,6 +306,28 @@ spi-flash@9 { }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <8 15>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index b02b8c8ce44d..e28c6dd16377 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -20,6 +20,50 @@ gpio-restart { gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "eth60:yellow"; + gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@1 { + label = "eth60:green"; + gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@2 { + label = "eth61:yellow"; + gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@3 { + label = "eth61:green"; + gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@4 { + label = "eth62:yellow"; + gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@5 { + label = "eth62:green"; + gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@6 { + label = "eth63:yellow"; + gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@7 { + label = "eth63:green"; + gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; &gpio { @@ -83,6 +127,17 @@ spi-flash@9 { }; }; +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl";