From patchwork Mon Nov 16 17:11:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 11909789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CC86C6379F for ; Mon, 16 Nov 2020 17:12:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 747B920888 for ; Mon, 16 Nov 2020 17:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732624AbgKPRMT (ORCPT ); Mon, 16 Nov 2020 12:12:19 -0500 Received: from relay11.mail.gandi.net ([217.70.178.231]:52821 "EHLO relay11.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731130AbgKPRMT (ORCPT ); Mon, 16 Nov 2020 12:12:19 -0500 X-Greylist: delayed 2863 seconds by postgrey-1.27 at vger.kernel.org; Mon, 16 Nov 2020 12:12:18 EST Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id 96CFF100041; Mon, 16 Nov 2020 17:12:15 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , Subject: [PATCH 1/5] dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property Date: Mon, 16 Nov 2020 18:11:55 +0100 Message-Id: <20201116171159.1735315-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116171159.1735315-1-gregory.clement@bootlin.com> References: <20201116171159.1735315-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Lars Povlsen This documents the 'microchip,reset-switch-core' property in the ocelot-reset driver. Signed-off-by: Lars Povlsen --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 4d530d815484..20fff03753ad 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -9,9 +9,15 @@ microchip Sparx5 armv8 SoC's. Required Properties: - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" +Optional properties: +- microchip,reset-switch-core : Perform a switch core reset at the + time of driver load. This is may be used to initialize the switch + core to a known state (before other drivers are loaded). + Example: reset@1070008 { compatible = "mscc,ocelot-chip-reset"; reg = <0x1070008 0x4>; + microchip,reset-switch-core; }; From patchwork Mon Nov 16 17:11:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 11909803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4421FC2D0A3 for ; Mon, 16 Nov 2020 17:22:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19EF220855 for ; Mon, 16 Nov 2020 17:22:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732778AbgKPRWv (ORCPT ); Mon, 16 Nov 2020 12:22:51 -0500 Received: from mslow2.mail.gandi.net ([217.70.178.242]:58526 "EHLO mslow2.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732777AbgKPRWv (ORCPT ); Mon, 16 Nov 2020 12:22:51 -0500 Received: from relay4-d.mail.gandi.net (unknown [217.70.183.196]) by mslow2.mail.gandi.net (Postfix) with ESMTP id 35CC33B5638 for ; Mon, 16 Nov 2020 17:12:40 +0000 (UTC) X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 0A516E0002; Mon, 16 Nov 2020 17:12:16 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , Subject: [PATCH 2/5] power: reset: ocelot: Add support for reset switch on load time Date: Mon, 16 Nov 2020 18:11:56 +0100 Message-Id: <20201116171159.1735315-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116171159.1735315-1-gregory.clement@bootlin.com> References: <20201116171159.1735315-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Lars Povlsen This patch add support for resetting the networking switch core at reset driver load time. It is useful in order to bring the switch core in a known state after a reboot or after a bootloader may have been using the switch for network access. Signed-off-by: Lars Povlsen --- drivers/power/reset/ocelot-reset.c | 40 ++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c index f74e1dbb4ba3..a203c42e99d4 100644 --- a/drivers/power/reset/ocelot-reset.c +++ b/drivers/power/reset/ocelot-reset.c @@ -29,6 +29,7 @@ struct ocelot_reset_context { struct notifier_block restart_handler; }; +#define SOFT_SWC_RST BIT(1) #define SOFT_CHIP_RST BIT(0) #define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 @@ -37,6 +38,32 @@ struct ocelot_reset_context { #define IF_SI_OWNER_SIBM 1 #define IF_SI_OWNER_SIMC 2 +static int ocelot_switch_core_reset(const struct ocelot_reset_context *ctx) +{ + + const char *driver = "ocelot-reset"; + int timeout; + + pr_notice("%s: Resetting Switch Core\n", driver); + + /* Make sure the core is PROTECTED from reset */ + regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, + ctx->props->vcore_protect, + ctx->props->vcore_protect); + + writel(SOFT_SWC_RST, ctx->base); + for (timeout = 0; timeout < 100; timeout++) { + if ((readl(ctx->base) & SOFT_SWC_RST) == 0) { + pr_debug("%s: Switch Core Reset complete.\n", driver); + return 0; + } + udelay(1); + } + + pr_warn("%s: Switch Core Reset timeout!\n", driver); + return -ENXIO; +} + static int ocelot_restart_handle(struct notifier_block *this, unsigned long mode, void *cmd) { @@ -66,7 +93,6 @@ static int ocelot_reset_probe(struct platform_device *pdev) { struct ocelot_reset_context *ctx; struct resource *res; - struct device *dev = &pdev->dev; int err; @@ -87,6 +113,11 @@ static int ocelot_reset_probe(struct platform_device *pdev) return PTR_ERR(ctx->cpu_ctrl); } + /* Optionally, call switch reset function */ + if (of_property_read_bool(pdev->dev.of_node, + "microchip,reset-switch-core")) + ocelot_switch_core_reset(ctx); + ctx->restart_handler.notifier_call = ocelot_restart_handle; ctx->restart_handler.priority = 192; err = register_restart_handler(&ctx->restart_handler); @@ -128,4 +159,9 @@ static struct platform_driver ocelot_reset_driver = { .of_match_table = ocelot_reset_of_match, }, }; -builtin_platform_driver(ocelot_reset_driver); + +static int __init reset_init(void) +{ + return platform_driver_register(&ocelot_reset_driver); +} +postcore_initcall(reset_init); From patchwork Mon Nov 16 17:11:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 11909799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10660C61DD8 for ; Mon, 16 Nov 2020 17:22:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D842B20855 for ; Mon, 16 Nov 2020 17:22:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731001AbgKPRWv (ORCPT ); Mon, 16 Nov 2020 12:22:51 -0500 Received: from mslow2.mail.gandi.net ([217.70.178.242]:58528 "EHLO mslow2.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732778AbgKPRWv (ORCPT ); Mon, 16 Nov 2020 12:22:51 -0500 Received: from relay4-d.mail.gandi.net (unknown [217.70.183.196]) by mslow2.mail.gandi.net (Postfix) with ESMTP id F01153B5C58 for ; Mon, 16 Nov 2020 17:12:40 +0000 (UTC) X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 35F8CE000E; Mon, 16 Nov 2020 17:12:18 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH 3/5] MIPS: dts: mscc: add reset switch property Date: Mon, 16 Nov 2020 18:11:57 +0100 Message-Id: <20201116171159.1735315-4-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116171159.1735315-1-gregory.clement@bootlin.com> References: <20201116171159.1735315-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This property allows resetting the networking switch core at reset driver load time. Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mscc/ocelot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index 535a98284dcb..070c4a6b790d 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -187,6 +187,7 @@ port10: port@10 { reset@1070008 { compatible = "mscc,ocelot-chip-reset"; reg = <0x1070008 0x4>; + microchip,reset-switch-core; }; gpio: pinctrl@1070034 { From patchwork Mon Nov 16 17:11:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 11909805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A67F9C63697 for ; Mon, 16 Nov 2020 17:22:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A1AB20855 for ; Mon, 16 Nov 2020 17:22:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732781AbgKPRWv (ORCPT ); Mon, 16 Nov 2020 12:22:51 -0500 Received: from mslow2.mail.gandi.net ([217.70.178.242]:58536 "EHLO mslow2.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732779AbgKPRWv (ORCPT ); Mon, 16 Nov 2020 12:22:51 -0500 Received: from relay5-d.mail.gandi.net (unknown [217.70.183.197]) by mslow2.mail.gandi.net (Postfix) with ESMTP id A22613B5CB1 for ; Mon, 16 Nov 2020 17:12:42 +0000 (UTC) X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay5-d.mail.gandi.net (Postfix) with ESMTPSA id 938971C0003; Mon, 16 Nov 2020 17:12:19 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH 4/5] power: reset: ocelot: Add support 2 othe MIPS based SoCs Date: Mon, 16 Nov 2020 18:11:58 +0100 Message-Id: <20201116171159.1735315-5-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116171159.1735315-1-gregory.clement@bootlin.com> References: <20201116171159.1735315-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This adds reset support for Luton and Jaguar2 in the ocelot-reset driver. They are both MIPS based belonging to the VvoreIII family. Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni --- drivers/power/reset/ocelot-reset.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c index a203c42e99d4..0f92416f2907 100644 --- a/drivers/power/reset/ocelot-reset.c +++ b/drivers/power/reset/ocelot-reset.c @@ -29,6 +29,8 @@ struct ocelot_reset_context { struct notifier_block restart_handler; }; +#define BIT_OFF_INVALID 32 + #define SOFT_SWC_RST BIT(1) #define SOFT_CHIP_RST BIT(0) @@ -77,9 +79,11 @@ static int ocelot_restart_handle(struct notifier_block *this, ctx->props->vcore_protect, 0); /* Make the SI back to boot mode */ - regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL, - IF_SI_OWNER_MASK << if_si_owner_bit, - IF_SI_OWNER_SIBM << if_si_owner_bit); + if (if_si_owner_bit != BIT_OFF_INVALID) + regmap_update_bits(ctx->cpu_ctrl, + ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL, + IF_SI_OWNER_MASK << if_si_owner_bit, + IF_SI_OWNER_SIBM << if_si_owner_bit); pr_emerg("Resetting SoC\n"); @@ -127,6 +131,20 @@ static int ocelot_reset_probe(struct platform_device *pdev) return err; } +static const struct reset_props reset_props_jaguar2 = { + .syscon = "mscc,ocelot-cpu-syscon", + .protect_reg = 0x20, + .vcore_protect = BIT(2), + .if_si_owner_bit = 6, +}; + +static const struct reset_props reset_props_luton = { + .syscon = "mscc,ocelot-cpu-syscon", + .protect_reg = 0x20, + .vcore_protect = BIT(2), + .if_si_owner_bit = BIT_OFF_INVALID, /* n/a */ +}; + static const struct reset_props reset_props_ocelot = { .syscon = "mscc,ocelot-cpu-syscon", .protect_reg = 0x20, @@ -143,6 +161,12 @@ static const struct reset_props reset_props_sparx5 = { static const struct of_device_id ocelot_reset_of_match[] = { { + .compatible = "mscc,jaguar2-chip-reset", + .data = &reset_props_jaguar2 + }, { + .compatible = "mscc,luton-chip-reset", + .data = &reset_props_luton + }, { .compatible = "mscc,ocelot-chip-reset", .data = &reset_props_ocelot }, { From patchwork Mon Nov 16 17:11:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 11909791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A92F6C6369E for ; Mon, 16 Nov 2020 17:12:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7077A20888 for ; Mon, 16 Nov 2020 17:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732656AbgKPRMX (ORCPT ); Mon, 16 Nov 2020 12:12:23 -0500 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:37859 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732620AbgKPRMX (ORCPT ); Mon, 16 Nov 2020 12:12:23 -0500 X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id AD68960011; Mon, 16 Nov 2020 17:12:20 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH 5/5] MIPS: dts: mscc: add reset support for Luton and Jaguar2 Date: Mon, 16 Nov 2020 18:11:59 +0100 Message-Id: <20201116171159.1735315-6-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116171159.1735315-1-gregory.clement@bootlin.com> References: <20201116171159.1735315-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Allow Luton and Jaguar2 SoC to use reset feature by adding the reset node. Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mscc/jaguar2.dtsi | 6 ++++++ arch/mips/boot/dts/mscc/luton.dtsi | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi index 42b2b0a51ddc..f5f7b81c4044 100644 --- a/arch/mips/boot/dts/mscc/jaguar2.dtsi +++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi @@ -60,6 +60,12 @@ cpu_ctrl: syscon@70000000 { reg = <0x70000000 0x2c>; }; + reset@71010008 { + compatible = "mscc,luton-chip-reset"; + reg = <0x71010008 0x4>; + microchip,reset-switch-core; + }; + intc: interrupt-controller@70000070 { compatible = "mscc,jaguar2-icpu-intr"; reg = <0x70000070 0x94>; diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi index 2a170b84c5a9..4a26c2874386 100644 --- a/arch/mips/boot/dts/mscc/luton.dtsi +++ b/arch/mips/boot/dts/mscc/luton.dtsi @@ -56,6 +56,11 @@ cpu_ctrl: syscon@10000000 { reg = <0x10000000 0x2c>; }; + reset@00070090 { + compatible = "mscc,luton-chip-reset"; + reg = <0x70090 0x4>; + }; + intc: interrupt-controller@10000084 { compatible = "mscc,luton-icpu-intr"; reg = <0x10000084 0x70>;