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Mon, 16 Nov 2020 18:49:10 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 01/11] memattrs: add debug attribute Date: Mon, 16 Nov 2020 18:48:59 +0000 Message-Id: <2ba88b512ec667eff66b2ece2177330a28e657c0.1605316268.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM6PR06CA0075.namprd06.prod.outlook.com (2603:10b6:5:336::8) To SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ashkalra_ubuntu_server.amd.com (165.204.77.1) by DM6PR06CA0075.namprd06.prod.outlook.com (2603:10b6:5:336::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 6h5BPgt4Y51bSqz+F2p4Sarq96fJHGaPDK2TJLTGJD+FE72QqoDNr/r+Pb89RyaREBFlEcekFNl6MzQnBLwf2mQVGnM6hCHNXNFvabVCGGAkCRkBIxP2+m2WBbFFCi8K4/75QE44Tk1foPoXOgZrcFI2PzZyS1wYK9BtZqu2XB8KSVZhVDmfoMhx0Y/6Aw7pnCtJMK0DYrA3F4mTcSMfglp3HE1z6g6uJCju6O3Wxr66cMHeUVwLItSBv/hGJDQRNGRMTvCkZLrtSBpj33G6vztlDYQ8M96XcyKUSy2O8RJeIF4ttf+02UajTy+VH7NhIhUo+DkPUh78HO4d/MXtP2BpXfdK57BSrAwhuHrDxvJrEKaVbdvzB8rh1U3TUErbnH0wQmM4zk8UElqq8C6jQ8z8Tot0BmPHzd64Lryh7jRGQW+HVibu19U1+XrYnOEZ/8f4PKnTMsKVsckpN9B/ii6wkNnLmuNLUdnxBNUzn5gwbLiEy6rSvm2q3S/NWYyabuG7O441rQyBowBCgSA9W4VLfZc5QyTo+OtdqFdZHBzGJYsqQvV3lqX7ngcY7A43HETC1gilS3fEpwwSUvWGmYSuE3tcsWGSbeEsPFzYVW2CIQspfmgyQ2D4V/cCWk3fcsBni3TL8aNCawBxi2EeCd2n52ht1gZ1/DPjDLxr/fy7Yop35OlCTWT+yy+YrBIDNUy6ZoJ+y/UWnNZCBGpHdL2Hz83qLt0MTgY/r03cCesblObMIz7Es3oALp/SgYUky8Bw10KrSn2wVigqnO4RC9bFpICuYgypLJ/JkhYrArJYe4jeXHAoqCqz49aLUXMJXlGDCWkLG4jYdn6JO8DQ1nF650BIYMQfr4BAkGL/mYxsiXo/T2GSZM2Oh8cojbSfD6RePlZxEkh1Xm3/pkj4yg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ca3a6828-35e9-4d48-9a69-08d88a604e11 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2767.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2020 18:49:10.7083 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9EApdeOuPwkIInSgH1wAyMY6oN4UKHBH/X6q4MQ6az9jPaxzBFtnCImbUc6uisQKrb9z1JoT3guUwf/DB+/bnw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2782 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Brijesh Singh From: Brijesh Singh Extend the MemTxAttrs to include a 'debug' flag. The flag can be used as general indicator that operation was triggered by the debugger. A subsequent patch will set the debug=1 when issuing a memory access from the gdbstub or HMP commands. This is a prerequisite to support debugging an encrypted guest. When a request with debug=1 is seen, the encryption APIs will be used to access the guest memory. Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- include/exec/memattrs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 95f2d20d55..c8b56389d6 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -49,6 +49,8 @@ typedef struct MemTxAttrs { unsigned int target_tlb_bit0 : 1; unsigned int target_tlb_bit1 : 1; unsigned int target_tlb_bit2 : 1; + /* Memory access request from the debugger */ + unsigned int debug:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, From patchwork Mon Nov 16 18:49:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EC09C6379F for ; Mon, 16 Nov 2020 18:49:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C3EC42224B for ; Mon, 16 Nov 2020 18:49:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="CLivh4kP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727635AbgKPSta (ORCPT ); Mon, 16 Nov 2020 13:49:30 -0500 Received: from mail-dm6nam08on2059.outbound.protection.outlook.com ([40.107.102.59]:46305 "EHLO NAM04-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726886AbgKPSta (ORCPT ); Mon, 16 Nov 2020 13:49:30 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iqZur4guZm/rpMBbWrLQOqm/z7BcxviAeq4xBVRakqRz+vK6XxYwMiZvE1KVj6ssgbXUz5rZrSeqiSYTzG+FeeINoknE09z2EFAAmibhhY3FJBgiGsBtC5SRlmRVd8U9dg3AuasdOpGYhO8DKX62UNVs7qjGTWXy7ei6LlXDa0KTSYxBdLdFuVZX/yilpuY3QoZhHDaP7bvRDZpCwvwFRtEjn5kXEt5pF1Y1WnCd8pvZGyaK6sy9UdzfeaxVmJp66wjbQd0pLGe5IJ4i2PzYWK1tE4u/CRU8aw2xL50oRg5Oo4kc1c1XLM1swqqB1LkOhLtwIbUD+r012wrWNDn6Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ambiGrX8FcaNuelrmpZ/RrHxc1WSpleBvG7jGdWWWZs=; b=CmW/3x5thaZ2MkxQS9ddEpRnnrttSMQK03OcoQZtVfM2sNg0K/QgyTcgjITRSfZ8lmivdaf4Ppw/mIOtu8/EQ3cwIk9pDVdiEUAd/v+mWLUwMZgg3x6Y9PEUlpZgv8g8n/AucEZfN4xm0g0i4MhINAPffSu3R7Bg2Y1YeescTi7AWL6yKxHEAWduk090s5i5dBxXBRlaMaxkgGPW9fqZrE4xh4JF6t2eNoPAtHKdiYSTo9lXs83ZTUW7P0xg6k4ZLAPhsLzHJbgb0ERh9g+jYiKnWwn7qQ1dsDjUrKYPjmqgYGzjD/76aeVLWlYPhryuvyuxAIzoTFRTDBQkJiOh2A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ambiGrX8FcaNuelrmpZ/RrHxc1WSpleBvG7jGdWWWZs=; b=CLivh4kPRhlUBe0Im9UUqOj7i6SdhZkVpUJvYikgJTjy0vddxisaChaqWF92707vhqd7PWjpnQ5728rqiLYc3PN6tMgGcVdcfXTrkWJmT0c6kbpFgpVu/4HU+XxgV5HwI5KauF7RzAhEnBp9swLHr2Fx45jnpE7JILOtUd8Q1iY= Authentication-Results: redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) by SN6PR12MB2782.namprd12.prod.outlook.com (2603:10b6:805:73::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.19; Mon, 16 Nov 2020 18:49:26 +0000 Received: from SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec]) by SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec%3]) with mapi id 15.20.3541.025; Mon, 16 Nov 2020 18:49:26 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 02/11] exec: Add new MemoryDebugOps. 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This is required for example in case of AMD SEV platform where the guest memory is encrypted and a SEV specific debug assist/hook will be required to access the guest memory. The MemoryDebugOps are used by cpu_memory_rw_debug() and default to address_space_read and address_space_write_rom. Signed-off-by: Ashish Kalra Reviewed-by: Dr. David Alan Gilbert --- include/exec/memory.h | 11 +++++++++++ softmmu/physmem.c | 24 ++++++++++++++++++++---- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index aff6ef7605..73deb4b456 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2394,6 +2394,17 @@ MemTxResult address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, const void *buf, hwaddr len); +typedef struct MemoryDebugOps { + MemTxResult (*read)(AddressSpace *as, hwaddr phys_addr, + MemTxAttrs attrs, void *buf, + hwaddr len); + MemTxResult (*write)(AddressSpace *as, hwaddr phys_addr, + MemTxAttrs attrs, const void *buf, + hwaddr len); +} MemoryDebugOps; + +void address_space_set_debug_ops(const MemoryDebugOps *ops); + static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) { if (is_write) { diff --git a/softmmu/physmem.c b/softmmu/physmem.c index a9adedb9f8..057d6d4ce1 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -166,6 +166,18 @@ struct DirtyBitmapSnapshot { unsigned long dirty[]; }; +static const MemoryDebugOps default_debug_ops = { + .read = address_space_read, + .write = address_space_write_rom +}; + +static const MemoryDebugOps *debug_ops = &default_debug_ops; + +void address_space_set_debug_ops(const MemoryDebugOps *ops) +{ + debug_ops = ops; +} + static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) { static unsigned alloc_hint = 16; @@ -3407,6 +3419,10 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, page = addr & TARGET_PAGE_MASK; phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); asidx = cpu_asidx_from_attrs(cpu, attrs); + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + /* if no physical page mapped, return an error */ if (phys_addr == -1) return -1; @@ -3415,11 +3431,11 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, l = len; phys_addr += (addr & ~TARGET_PAGE_MASK); if (is_write) { - res = address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, - attrs, buf, l); + res = debug_ops->write(cpu->cpu_ases[asidx].as, phys_addr, + attrs, buf, l); } else { - res = address_space_read(cpu->cpu_ases[asidx].as, phys_addr, - attrs, buf, l); + res = debug_ops->read(cpu->cpu_ases[asidx].as, phys_addr, + attrs, buf, l); } if (res != MEMTX_OK) { return -1; From patchwork Mon Nov 16 18:49:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51A17C55ABD for ; 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dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) by SA0PR12MB4557.namprd12.prod.outlook.com (2603:10b6:806:9d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Mon, 16 Nov 2020 18:50:11 +0000 Received: from SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec]) by SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec%3]) with mapi id 15.20.3541.025; Mon, 16 Nov 2020 18:50:11 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 03/11] exec: add ram_debug_ops support Date: Mon, 16 Nov 2020 18:49:55 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM3PR12CA0106.namprd12.prod.outlook.com (2603:10b6:0:55::26) To SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ashkalra_ubuntu_server.amd.com (165.204.77.1) by DM3PR12CA0106.namprd12.prod.outlook.com (2603:10b6:0:55::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25 via Frontend Transport; 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Extend the 'struct MemoryRegion' to include new callbacks that can be used to override the use of memcpy() with something else. The new callbacks can be used to display the guest memory of an SEV guest by registering callbacks to the SEV memory encryption/decryption APIs. Typical usage: mem_read(uint8_t *dst, uint8_t *src, uint32_t len, MemTxAttrs *attrs); mem_write(uint8_t *dst, uint8_t *src, uint32_t len, MemTxAttrs *attrs); MemoryRegionRAMReadWriteOps ops; ops.read = mem_read; ops.write = mem_write; memory_region_init_ram(mem, NULL, "memory", size, NULL); memory_region_set_ram_debug_ops(mem, ops); Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- include/exec/memory.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 73deb4b456..2fb4193358 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -402,6 +402,18 @@ struct IOMMUMemoryRegionClass { typedef struct CoalescedMemoryRange CoalescedMemoryRange; typedef struct MemoryRegionIoeventfd MemoryRegionIoeventfd; +/* Memory Region RAM debug callback */ +typedef struct MemoryRegionRAMReadWriteOps MemoryRegionRAMReadWriteOps; + +struct MemoryRegionRAMReadWriteOps { + /* Write data into guest memory */ + int (*write) (uint8_t *dest, const uint8_t *src, + uint32_t len, MemTxAttrs attrs); + /* Read data from guest memory */ + int (*read) (uint8_t *dest, const uint8_t *src, + uint32_t len, MemTxAttrs attrs); +}; + /** MemoryRegion: * * A struct representing a memory region. @@ -445,6 +457,7 @@ struct MemoryRegion { const char *name; unsigned ioeventfd_nb; MemoryRegionIoeventfd *ioeventfds; + const MemoryRegionRAMReadWriteOps *ram_debug_ops; }; struct IOMMUMemoryRegion { @@ -1060,6 +1073,20 @@ void memory_region_init_rom_nomigrate(MemoryRegion *mr, uint64_t size, Error **errp); +/** + * memory_region_set_ram_debug_ops: Set access ops for a give memory region. + * + * @mr: the #MemoryRegion to be initialized + * @ops: a function that will be used when accessing @target region during + * debug + */ +static inline void +memory_region_set_ram_debug_ops(MemoryRegion *mr, + const MemoryRegionRAMReadWriteOps *ops) +{ + mr->ram_debug_ops = ops; +} + /** * memory_region_init_rom_device_nomigrate: Initialize a ROM memory region. * Writes are handled via callbacks. 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Signed-off-by: Ashish Kalra --- include/exec/memory.h | 10 +++++ softmmu/physmem.c | 88 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 2fb4193358..74f2dcec00 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2432,6 +2432,16 @@ typedef struct MemoryDebugOps { void address_space_set_debug_ops(const MemoryDebugOps *ops); +MemTxResult address_space_write_rom_debug(AddressSpace *as, + hwaddr addr, + MemTxAttrs attrs, + const void *ptr, + hwaddr len); + +MemTxResult address_space_read_debug(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, void *buf, + hwaddr len); + static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) { if (is_write) { diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 057d6d4ce1..2c08624ca8 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -3266,6 +3266,94 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len, #define RCU_READ_UNLOCK(...) rcu_read_unlock() #include "memory_ldst.c.inc" +MemTxResult address_space_read_debug(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, void *ptr, + hwaddr len) +{ + uint64_t val; + MemoryRegion *mr; + hwaddr l = len; + hwaddr addr1; + MemTxResult result = MEMTX_OK; + bool release_lock = false; + uint8_t *buf = ptr; + uint8_t *ram_ptr; + + for (;;) { + RCU_READ_LOCK_GUARD(); + mr = address_space_translate(as, addr, &addr1, &l, false, attrs); + if (!memory_access_is_direct(mr, false)) { + /* I/O case */ + release_lock |= prepare_mmio_access(mr); + l = memory_access_size(mr, l, addr1); + result |= memory_region_dispatch_read(mr, addr1, &val, + size_memop(l), attrs); + stn_he_p(buf, l, val); + } else { + /* RAM case */ + fuzz_dma_read_cb(addr, l, mr, false); + ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); + if (attrs.debug && mr->ram_debug_ops) { + mr->ram_debug_ops->read(buf, ram_ptr, l, attrs); + } else { + memcpy(buf, ram_ptr, l); + } + result = MEMTX_OK; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + release_lock = false; + } + + len -= l; + buf += l; + addr += l; + + if (!len) { + break; + } + l = len; + } + return result; +} + +inline MemTxResult address_space_write_rom_debug(AddressSpace *as, + hwaddr addr, + MemTxAttrs attrs, + const void *ptr, + hwaddr len) +{ + hwaddr l; + uint8_t *ram_ptr; + hwaddr addr1; + MemoryRegion *mr; + const uint8_t *buf = ptr; + + RCU_READ_LOCK_GUARD(); + while (len > 0) { + l = len; + mr = address_space_translate(as, addr, &addr1, &l, true, attrs); + + if (!(memory_region_is_ram(mr) || + memory_region_is_romd(mr))) { + l = memory_access_size(mr, l, addr1); + } else { + /* ROM/RAM case */ + ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + if (attrs.debug && mr->ram_debug_ops) { + mr->ram_debug_ops->write(ram_ptr, buf, l, attrs); + } else { + memcpy(ram_ptr, buf, l); + } + invalidate_and_set_dirty(mr, addr1, l); + } + len -= l; + buf += l; + addr += l; + } + return MEMTX_OK; +} + int64_t address_space_cache_init(MemoryRegionCache *cache, AddressSpace *as, hwaddr addr, From patchwork Mon Nov 16 18:51:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76B8EC2D0A3 for ; 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Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- include/exec/cpu-common.h | 15 +++++++++++++ softmmu/physmem.c | 47 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 19805ed6db..d2089e6873 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -71,11 +71,26 @@ size_t qemu_ram_pagesize_largest(void); void cpu_physical_memory_rw(hwaddr addr, void *buf, hwaddr len, bool is_write); +void cpu_physical_memory_rw_debug(hwaddr addr, uint8_t *buf, + int len, int is_write); static inline void cpu_physical_memory_read(hwaddr addr, void *buf, hwaddr len) { cpu_physical_memory_rw(addr, buf, len, false); } +static inline void cpu_physical_memory_read_debug(hwaddr addr, + void *buf, int len) +{ + cpu_physical_memory_rw_debug(addr, buf, len, false); +} +static inline void cpu_physical_memory_write_debug(hwaddr addr, + const void *buf, int len) +{ + cpu_physical_memory_rw_debug(addr, (void *)buf, len, true); +} +uint32_t ldl_phys_debug(CPUState *cpu, hwaddr addr); +uint64_t ldq_phys_debug(CPUState *cpu, hwaddr addr); + static inline void cpu_physical_memory_write(hwaddr addr, const void *buf, hwaddr len) { diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 2c08624ca8..6945bd5efe 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -3354,6 +3354,53 @@ inline MemTxResult address_space_write_rom_debug(AddressSpace *as, return MEMTX_OK; } +uint32_t ldl_phys_debug(CPUState *cpu, hwaddr addr) +{ + MemTxAttrs attrs; + int asidx = cpu_asidx_from_attrs(cpu, attrs); + uint32_t val; + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + debug_ops->read(cpu->cpu_ases[asidx].as, addr, attrs, + (void *) &val, 4); + + return tswap32(val); +} + +uint64_t ldq_phys_debug(CPUState *cpu, hwaddr addr) +{ + MemTxAttrs attrs; + int asidx = cpu_asidx_from_attrs(cpu, attrs); + uint64_t val; + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + debug_ops->read(cpu->cpu_ases[asidx].as, addr, attrs, + (void *) &val, 8); + return val; +} + +void cpu_physical_memory_rw_debug(hwaddr addr, uint8_t *buf, + int len, int is_write) +{ + MemTxAttrs attrs; + + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + if (is_write) { + debug_ops->write(&address_space_memory, addr, + attrs, buf, len); + } else { + debug_ops->read(&address_space_memory, addr, + attrs, buf, len); + } + +} + int64_t address_space_cache_init(MemoryRegionCache *cache, AddressSpace *as, hwaddr addr, From patchwork Mon Nov 16 18:51:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5268EC2D0A3 for ; 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dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) by SA0PR12MB4557.namprd12.prod.outlook.com (2603:10b6:806:9d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Mon, 16 Nov 2020 18:51:48 +0000 Received: from SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec]) by SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec%3]) with mapi id 15.20.3541.025; Mon, 16 Nov 2020 18:51:48 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 06/11] monitor/i386: use debug APIs when accessing guest memory Date: Mon, 16 Nov 2020 18:51:33 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR12CA0053.namprd12.prod.outlook.com (2603:10b6:3:103::15) To SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ashkalra_ubuntu_server.amd.com (165.204.77.1) by DM5PR12CA0053.namprd12.prod.outlook.com (2603:10b6:3:103::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25 via Frontend Transport; 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Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- monitor/misc.c | 4 ++-- softmmu/cpus.c | 2 +- target/i386/monitor.c | 54 ++++++++++++++++++++++++------------------- 3 files changed, 33 insertions(+), 27 deletions(-) diff --git a/monitor/misc.c b/monitor/misc.c index 32e6a8c13d..7eba3a6fce 100644 --- a/monitor/misc.c +++ b/monitor/misc.c @@ -824,8 +824,8 @@ static void hmp_sum(Monitor *mon, const QDict *qdict) sum = 0; for(addr = start; addr < (start + size); addr++) { - uint8_t val = address_space_ldub(&address_space_memory, addr, - MEMTXATTRS_UNSPECIFIED, NULL); + uint8_t val; + cpu_physical_memory_read_debug(addr, &val, 1); /* BSD sum algorithm ('sum' Unix command) */ sum = (sum >> 1) | (sum << 15); sum += val; diff --git a/softmmu/cpus.c b/softmmu/cpus.c index e46ac68ad0..79817330b7 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -779,7 +779,7 @@ void qmp_pmemsave(int64_t addr, int64_t size, const char *filename, l = sizeof(buf); if (l > size) l = size; - cpu_physical_memory_read(addr, buf, l); + cpu_physical_memory_read_debug(addr, buf, l); if (fwrite(buf, 1, l, f) != l) { error_setg(errp, QERR_IO_ERROR); goto exit; diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 7abae3c8df..9ca9c677a5 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -79,7 +79,7 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env) pgd = env->cr[3] & ~0xfff; for(l1 = 0; l1 < 1024; l1++) { - cpu_physical_memory_read(pgd + l1 * 4, &pde, 4); + cpu_physical_memory_read_debug(pgd + l1 * 4, &pde, 4); pde = le32_to_cpu(pde); if (pde & PG_PRESENT_MASK) { if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { @@ -87,7 +87,8 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env) print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); } else { for(l2 = 0; l2 < 1024; l2++) { - cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4); + cpu_physical_memory_read_debug((pde & ~0xfff) + l2 * 4, + &pte, 4); pte = le32_to_cpu(pte); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l1 << 22) + (l2 << 12), @@ -108,12 +109,12 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env) pdp_addr = env->cr[3] & ~0x1f; for (l1 = 0; l1 < 4; l1++) { - cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8); + cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); pdpe = le64_to_cpu(pdpe); if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8); + cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); pde = le64_to_cpu(pde); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -123,7 +124,8 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env) } else { pt_addr = pde & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8); + cpu_physical_memory_read_debug(pt_addr + l3 * 8, + &pte, 8); pte = le64_to_cpu(pte); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l1 << 30) + (l2 << 21) @@ -148,7 +150,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, uint64_t pdp_addr, pd_addr, pt_addr; for (l1 = 0; l1 < 512; l1++) { - cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8); + cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); pml4e = le64_to_cpu(pml4e); if (!(pml4e & PG_PRESENT_MASK)) { continue; @@ -156,7 +158,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8); + cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); pdpe = le64_to_cpu(pdpe); if (!(pdpe & PG_PRESENT_MASK)) { continue; @@ -171,7 +173,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8); + cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); pde = le64_to_cpu(pde); if (!(pde & PG_PRESENT_MASK)) { continue; @@ -186,7 +188,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pt_addr = pde & 0x3fffffffff000ULL; for (l4 = 0; l4 < 512; l4++) { - cpu_physical_memory_read(pt_addr + cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); pte = le64_to_cpu(pte); @@ -209,7 +211,7 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env) pml5_addr = env->cr[3] & 0x3fffffffff000ULL; for (l0 = 0; l0 < 512; l0++) { - cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8); + cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); pml5e = le64_to_cpu(pml5e); if (pml5e & PG_PRESENT_MASK) { tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); @@ -286,7 +288,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env) last_prot = 0; start = -1; for(l1 = 0; l1 < 1024; l1++) { - cpu_physical_memory_read(pgd + l1 * 4, &pde, 4); + cpu_physical_memory_read_debug(pgd + l1 * 4, &pde, 4); pde = le32_to_cpu(pde); end = l1 << 22; if (pde & PG_PRESENT_MASK) { @@ -295,7 +297,8 @@ static void mem_info_32(Monitor *mon, CPUArchState *env) mem_print(mon, env, &start, &last_prot, end, prot); } else { for(l2 = 0; l2 < 1024; l2++) { - cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4); + cpu_physical_memory_read_debug((pde & ~0xfff) + l2 * 4, + &pte, 4); pte = le32_to_cpu(pte); end = (l1 << 22) + (l2 << 12); if (pte & PG_PRESENT_MASK) { @@ -328,13 +331,13 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env) last_prot = 0; start = -1; for (l1 = 0; l1 < 4; l1++) { - cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8); + cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); pdpe = le64_to_cpu(pdpe); end = l1 << 30; if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8); + cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); pde = le64_to_cpu(pde); end = (l1 << 30) + (l2 << 21); if (pde & PG_PRESENT_MASK) { @@ -345,7 +348,8 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env) } else { pt_addr = pde & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8); + cpu_physical_memory_read_debug(pt_addr + l3 * 8, + &pte, 8); pte = le64_to_cpu(pte); end = (l1 << 30) + (l2 << 21) + (l3 << 12); if (pte & PG_PRESENT_MASK) { @@ -384,13 +388,13 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) last_prot = 0; start = -1; for (l1 = 0; l1 < 512; l1++) { - cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8); + cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); pml4e = le64_to_cpu(pml4e); end = l1 << 39; if (pml4e & PG_PRESENT_MASK) { pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8); + cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); pdpe = le64_to_cpu(pdpe); end = (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { @@ -402,7 +406,8 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) } else { pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8); + cpu_physical_memory_read_debug(pd_addr + l3 * 8, + &pde, 8); pde = le64_to_cpu(pde); end = (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { @@ -415,7 +420,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) } else { pt_addr = pde & 0x3fffffffff000ULL; for (l4 = 0; l4 < 512; l4++) { - cpu_physical_memory_read(pt_addr + cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); pte = le64_to_cpu(pte); @@ -464,7 +469,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) last_prot = 0; start = -1; for (l0 = 0; l0 < 512; l0++) { - cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8); + cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); pml5e = le64_to_cpu(pml5e); end = l0 << 48; if (!(pml5e & PG_PRESENT_MASK)) { @@ -475,7 +480,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pml4_addr = pml5e & 0x3fffffffff000ULL; for (l1 = 0; l1 < 512; l1++) { - cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8); + cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); pml4e = le64_to_cpu(pml4e); end = (l0 << 48) + (l1 << 39); if (!(pml4e & PG_PRESENT_MASK)) { @@ -486,7 +491,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8); + cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); pdpe = le64_to_cpu(pdpe); end = (l0 << 48) + (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { @@ -505,7 +510,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8); + cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); pde = le64_to_cpu(pde); end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { @@ -524,7 +529,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pt_addr = pde & 0x3fffffffff000ULL; for (l4 = 0; l4 < 512; l4++) { - cpu_physical_memory_read(pt_addr + l4 * 8, &pte, 8); + cpu_physical_memory_read_debug(pt_addr + l4 * 8, + &pte, 8); pte = le64_to_cpu(pte); end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12); From patchwork Mon Nov 16 18:51:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FCD2C2D0A3 for ; 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X-MS-Exchange-AntiSpam-MessageData: k+WnJDUK8cb5aRKLe5cmZt62xH4mSybijPK/cKOvN5ePsfOcf/qwvT/SSLR72iSI2R6uwp4CxQnTSMoKv0fcYy6gRT9HaDNZQImUCP4T2uxMJk6Jd/2EiOu0+BXV/jJ3Z5t0pJojmfq0r9m2uRb6HzT2WH78kHh8X5Hk3sQWR521C0121mZHmV4MNvFFxPKie2q3RWnrCDyVn6B04vwF+WBUTBOG3QjkWhinLb0gcgHvHXp2o8VKl8wmah0QzBb+SMJ2rgjw3xPhAQWxq8oEtrFNAbnpbHkZ5z0QCf+nxRsPprw+FtzHQ4CMNOLAc7RrLzvkdIl5gcSfkhN45++7JABgr5aWdhh2wPkQv42++HHxnNW3y58X4AqjW4hqrjPYqlnF+1knDU5Qb4f273Q4khQiO3Z7hl2q6j8zb88Pgo26+L8+fDxX9VN0Sr5oqftpwlivP7lvWfC9FzXP/253DVO05ZIDekgQx4u9/CfYpb92Qw6VOk5617GxyKUXUtq3N1UefoQS6ULCE5ZPUEc9i2G2QztfhaeGHzIPrpcd4CPsf7whqT344zACd2ef09B0Lhbza1+HjSgRG8fhq5hNRKy1DXVTEOnuX0VGzqNMVUwaYBtfDuYeC5PYorvKTNZKCKc7TlkgLn3yr2owjPc1GXQb4JC8NJsqy+At97P7NOAreV9tkeW8GNE3R37nlk/bxX4EOLQSEdWUlq6x/C34+EW/r56wHiy8v0rfg0iB5Q8iV2obxln5rQXbxGYydgH36I1iBLVnIYZ7a7cRlNovdzP0SPyJicc21JIk0DUvg9LZBI+/8NdGOm9iZ04Lg3B1WmIexgBpGeLu/Onstl9OAzLo1Yha04tuJ1aSGHTE++4IV1gCIxbDf30JqMfZQ5960Z1djVtLxDBS6Iiro/tm8w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 799bfd96-0ce7-4c34-41b6-08d88a60b661 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2767.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2020 18:52:05.6454 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Z4xeT5NDT6q0cQ3YhIbva6dcNwV/L4GxNT33UBzq3rb/DK0it0DWjEnMd5cKpdJ3uYU2hQfWh3/PammGOUu+zg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4557 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Brijesh Singh In order to support debugging with Secure Encrypted Virtualization (SEV), add a high-level memory encryption API. Also add a new API interface to override any CPU class specific callbacks for supporting debugging with SEV, for example, overriding the guest MMU/ page-table walker callback. Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- accel/kvm/kvm-all.c | 19 +++++++++++++++++++ accel/stubs/kvm-stub.c | 8 ++++++++ include/sysemu/kvm.h | 15 +++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 9ef5daf4c5..ae85f53e7d 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -123,6 +123,8 @@ struct KVMState /* memory encryption */ void *memcrypt_handle; int (*memcrypt_encrypt_data)(void *handle, uint8_t *ptr, uint64_t len); + void (*memcrypt_debug_ops_memory_region)(void *handle, MemoryRegion *mr); + void (*memcrypt_debug_ops_cpu_state)(void *handle, CPUState *cpu); /* For "info mtree -f" to tell if an MR is registered in KVM */ int nr_as; @@ -222,6 +224,23 @@ int kvm_get_max_memslots(void) return s->nr_slots; } +void kvm_memcrypt_set_debug_ops_memory_region(MemoryRegion *mr) +{ + if (kvm_state->memcrypt_handle && + kvm_state->memcrypt_debug_ops_memory_region) { + kvm_state->memcrypt_debug_ops_memory_region(kvm_state->memcrypt_handle, + mr); + } +} + +void kvm_memcrypt_set_debug_ops_cpu_state(CPUState *cs) +{ + if (kvm_state->memcrypt_handle && + kvm_state->memcrypt_debug_ops_cpu_state) { + kvm_state->memcrypt_debug_ops_cpu_state(kvm_state->memcrypt_handle, cs); + } +} + bool kvm_memcrypt_enabled(void) { if (kvm_state && kvm_state->memcrypt_handle) { diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 680e099463..bf93431e46 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -91,6 +91,14 @@ int kvm_memcrypt_encrypt_data(uint8_t *ptr, uint64_t len) return 1; } +void kvm_memcrypt_set_debug_ops_memory_region(MemoryRegion *mr) +{ +} + +void kvm_memcrypt_set_debug_ops_cpu_state(CPUState *cs) +{ +} + #ifndef CONFIG_USER_ONLY int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) { diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index bb5d5cf497..1bde2e3d71 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -470,6 +470,21 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function, uint32_t index, int reg); uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index); +/** + * kvm_memcrypt_set_debug_ram_ops: set debug_ram_ops callback + * + * When debug_ram_ops is set, debug access to this memory region will use + * memory encryption APIs. + */ +void kvm_memcrypt_set_debug_ops_memory_region(MemoryRegion *mr); + +/** + * kvm_memcrypt_set_debug_ops_cpu_state: override cpu_class callbacks + * + * This interface allows vendor specific debug ops to override any + * cpu_class callbacks. + */ +void kvm_memcrypt_set_debug_ops_cpu_state(CPUState *cs); void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len); From patchwork Mon Nov 16 18:52:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23096C2D0A3 for ; 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The command works only if the guest policy allows the debugging. Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- accel/kvm/kvm-all.c | 2 ++ accel/kvm/sev-stub.c | 4 +++ include/sysemu/sev.h | 1 + target/i386/sev.c | 58 ++++++++++++++++++++++++++++++++++++++++ target/i386/trace-events | 1 + 5 files changed, 66 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index ae85f53e7d..042205e3e1 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2232,6 +2232,8 @@ static int kvm_init(MachineState *ms) } kvm_state->memcrypt_encrypt_data = sev_encrypt_data; + kvm_state->memcrypt_debug_ops_memory_region = + sev_set_debug_ops_memory_region; } ret = kvm_arch_init(ms, s); diff --git a/accel/kvm/sev-stub.c b/accel/kvm/sev-stub.c index 4f97452585..3f1f0ef217 100644 --- a/accel/kvm/sev-stub.c +++ b/accel/kvm/sev-stub.c @@ -15,6 +15,10 @@ #include "qemu-common.h" #include "sysemu/sev.h" +void sev_set_debug_ops_memory_region(void *handle, MemoryRegion *mr) +{ +} + int sev_encrypt_data(void *handle, uint8_t *ptr, uint64_t len) { abort(); diff --git a/include/sysemu/sev.h b/include/sysemu/sev.h index 98c1ec8d38..6c37247915 100644 --- a/include/sysemu/sev.h +++ b/include/sysemu/sev.h @@ -18,4 +18,5 @@ void *sev_guest_init(const char *id); int sev_encrypt_data(void *handle, uint8_t *ptr, uint64_t len); +void sev_set_debug_ops_memory_region(void *handle, MemoryRegion *mr); #endif diff --git a/target/i386/sev.c b/target/i386/sev.c index 93c4d60b82..3036fb3e43 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -72,6 +72,8 @@ struct SevGuestState { static SevGuestState *sev_guest; static Error *sev_mig_blocker; +static MemoryRegionRAMReadWriteOps sev_ops; + static const char *const sev_fw_errlist[] = { "", "Platform state is invalid", @@ -679,6 +681,46 @@ sev_vm_state_change(void *opaque, int running, RunState state) } } +static int +sev_dbg_enc_dec(uint8_t *dst, const uint8_t *src, uint32_t len, bool write) +{ + int ret, error; + struct kvm_sev_dbg dbg; + + dbg.src_uaddr = (unsigned long)src; + dbg.dst_uaddr = (unsigned long)dst; + dbg.len = len; + + trace_kvm_sev_debug(write ? "encrypt" : "decrypt", src, dst, len); + ret = sev_ioctl(sev_guest->sev_fd, + write ? KVM_SEV_DBG_ENCRYPT : KVM_SEV_DBG_DECRYPT, + &dbg, &error); + if (ret) { + error_report("%s (%s) 0x%llx->0x%llx+0x%x ret=%d fw_error=%d '%s'", + __func__, write ? "write" : "read", dbg.src_uaddr, + dbg.dst_uaddr, dbg.len, ret, error, + fw_error_to_str(error)); + } + + return ret; +} + +static int +sev_mem_read(uint8_t *dst, const uint8_t *src, uint32_t len, MemTxAttrs attrs) +{ + assert(attrs.debug); + + return sev_dbg_enc_dec(dst, src, len, false); +} + +static int +sev_mem_write(uint8_t *dst, const uint8_t *src, uint32_t len, MemTxAttrs attrs) +{ + assert(attrs.debug); + + return sev_dbg_enc_dec(dst, src, len, true); +} + void * sev_guest_init(const char *id) { @@ -785,6 +827,22 @@ sev_encrypt_data(void *handle, uint8_t *ptr, uint64_t len) return 0; } +void +sev_set_debug_ops_memory_region(void *handle, MemoryRegion *mr) +{ + SevGuestState *s = handle; + + /* If policy does not allow debug then no need to register ops */ + if (s->policy & SEV_POLICY_NODBG) { + return; + } + + sev_ops.read = sev_mem_read; + sev_ops.write = sev_mem_write; + + memory_region_set_ram_debug_ops(mr, &sev_ops); +} + static void sev_register_types(void) { diff --git a/target/i386/trace-events b/target/i386/trace-events index 789c700d4a..f91213c5e9 100644 --- a/target/i386/trace-events +++ b/target/i386/trace-events @@ -15,3 +15,4 @@ kvm_sev_launch_start(int policy, void *session, void *pdh) "policy 0x%x session kvm_sev_launch_update_data(void *addr, uint64_t len) "addr %p len 0x%" PRIu64 kvm_sev_launch_measurement(const char *value) "data %s" kvm_sev_launch_finish(void) "" +kvm_sev_debug(const char *op, const uint8_t *src, uint8_t *dst, int len) "(%s) src %p dst %p len %d" From patchwork Mon Nov 16 18:52:29 2020 Content-Type: text/plain; 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Mon, 16 Nov 2020 18:52:40 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 09/11] hw/i386: set ram_debug_ops when memory encryption is enabled Date: Mon, 16 Nov 2020 18:52:29 +0000 Message-Id: <0afaef32bcf868297eff2837e2462a3c5efd21ba.1605316268.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM6PR05CA0038.namprd05.prod.outlook.com (2603:10b6:5:335::7) To SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ashkalra_ubuntu_server.amd.com (165.204.77.1) by DM6PR05CA0038.namprd05.prod.outlook.com (2603:10b6:5:335::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.15 via Frontend Transport; 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By setting the debug ops allow us to invoke encryption APIs when accessing the memory for the debug purposes. Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- hw/i386/pc.c | 9 +++++++++ hw/i386/pc_sysfw.c | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5e6c0023e0..dfb63cd686 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -913,6 +913,15 @@ void pc_memory_init(PCMachineState *pcms, e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); } + /* + * When memory encryption is enabled, the guest RAM will be encrypted with + * a guest unique key. Set the debug ops so that any debug access to the + * guest RAM will go through the memory encryption APIs. + */ + if (kvm_memcrypt_enabled()) { + kvm_memcrypt_set_debug_ops_memory_region(*ram_memory); + } + if (!pcmc->has_reserved_memory && (machine->ram_slots || (machine->maxram_size > machine->ram_size))) { diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index b6c0822fe3..9f90c9d761 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -209,6 +209,12 @@ static void pc_system_flash_map(PCMachineState *pcms, error_report("failed to encrypt pflash rom"); exit(1); } + + /* + * The pflash ROM is encrypted, set the debug ops so that any + * debug accesses will use memory encryption APIs. + */ + kvm_memcrypt_set_debug_ops_memory_region(flash_mem); } } } From patchwork Mon Nov 16 18:52:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0215C64E8A for ; Mon, 16 Nov 2020 18:53:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59D9C2225E for ; Mon, 16 Nov 2020 18:53:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="UjoSyWbS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728751AbgKPSxB (ORCPT ); Mon, 16 Nov 2020 13:53:01 -0500 Received: from mail-mw2nam12on2040.outbound.protection.outlook.com ([40.107.244.40]:28416 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726625AbgKPSxA (ORCPT ); Mon, 16 Nov 2020 13:53:00 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SaCN9QcRfnUSMpS/nD8vQavZowWUy8e52CduWWFxosH5Xb6qfyrkxvqTZCZo2FkNRJjIy7ZGCp5MaHhpVILMQoMH8ht2DLtPeJfUuk1Ydub7jcZGeoZHhYYWy5ERSAV7+YTuq9/7UIZ6fs3xQbr09ezQJbV2PDD/IY6zFccS3x10ld+68yGV905SyBBp8grcqQKhGgXs5MvlsllEAnRZ73YWInBmlCqQTshWH4d9r8Fin3rr240o/uZ5uTFjxUyXlq1dTJu0M7s0Uzu5zvVPq2SowFEbkzgPhhxESBDO0xptnvE3TifdCs9eMXyT8B/er3Sq9wiHCqnSrAm293LixA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vK36Zg/1QYy9Yne1JbuCJ0smnKXs7y6N61xip+7YPN0=; b=WUrqLms3TG9sCYNk0l6Mr/GW3LsJV6DeZz5N73t7SLEeZdnQaCHR5sijhp7616HYvpjeVG32bFlNizQvI7ZZY0XlzGH1Wy7rhab8TyqGOMLzJKHovDqUOwak2uFfNgylRj4860fJ4JARTshOPl3nFz4KOLFU4FjYsNYUK16Nctb7MVKvA7S54NJc1UAaposlGd6roVTwkIV1ARogMtLzqOR9Ppv77w4qLhbJ1kTBeeRPesvyeuJ6l5SeGnmJ6/vU6xaCCZ/R5u5voapLQ322+uvwBZEYtB9Xl65za0TdbHYokrJuvHk4Rvxr/iPNlBrGNrfAXg1SbpbXOFJ1gPtzIQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vK36Zg/1QYy9Yne1JbuCJ0smnKXs7y6N61xip+7YPN0=; b=UjoSyWbSHKlEg8Qh/F/WXjLCPGLqlyOxxZqRZypljqvFUHgJsG2ENboUD134JJjpiNFVx8SD6dyBtv/EAXla0MapI7aJelpk0ScKdCPqgTrBSidoG9l25iU+etmPPsH/xsBzn8Pi7H55K+Uii3Tql0xbZvQLZG7exQ9bhoS1zOc= Authentication-Results: redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) by SA0PR12MB4557.namprd12.prod.outlook.com (2603:10b6:806:9d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Mon, 16 Nov 2020 18:52:57 +0000 Received: from SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec]) by SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec%3]) with mapi id 15.20.3541.025; Mon, 16 Nov 2020 18:52:57 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 10/11] sev/i386: add SEV specific MemoryDebugOps. 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The SEV specific MemoryDebugOps invoke the generic address_space_rw_debug helpers which will then invoke the memory region specific callbacks to handle and access encrypted memory when guest RAM is accessed. Also invoke the memory encryption API to override any CPU class specific callbacks to handle memory encryption. Specifically for SEV we override CPU class specific guest MMU/page-table walker to invoke a SEV specific handler which can handle guest encrypted memory and also clear C-bit when walking SEV guest page table. Signed-off-by: Ashish Kalra --- accel/kvm/kvm-all.c | 1 + accel/kvm/sev-stub.c | 4 + include/sysemu/sev.h | 11 +++ target/i386/kvm.c | 4 + target/i386/sev.c | 185 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 205 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 042205e3e1..6d812d5b09 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2234,6 +2234,7 @@ static int kvm_init(MachineState *ms) kvm_state->memcrypt_encrypt_data = sev_encrypt_data; kvm_state->memcrypt_debug_ops_memory_region = sev_set_debug_ops_memory_region; + kvm_state->memcrypt_debug_ops_cpu_state = sev_set_debug_ops_cpu_state; } ret = kvm_arch_init(ms, s); diff --git a/accel/kvm/sev-stub.c b/accel/kvm/sev-stub.c index 3f1f0ef217..ad27226058 100644 --- a/accel/kvm/sev-stub.c +++ b/accel/kvm/sev-stub.c @@ -19,6 +19,10 @@ void sev_set_debug_ops_memory_region(void *handle, MemoryRegion *mr) { } +void sev_set_debug_ops_cpu_state(void *handle, CPUState *cpu) +{ +} + int sev_encrypt_data(void *handle, uint8_t *ptr, uint64_t len) { abort(); diff --git a/include/sysemu/sev.h b/include/sysemu/sev.h index 6c37247915..e6f176b85b 100644 --- a/include/sysemu/sev.h +++ b/include/sysemu/sev.h @@ -19,4 +19,15 @@ void *sev_guest_init(const char *id); int sev_encrypt_data(void *handle, uint8_t *ptr, uint64_t len); void sev_set_debug_ops_memory_region(void *handle, MemoryRegion *mr); +void sev_set_debug_ops_cpu_state(void *handle, CPUState *cpu); +hwaddr sev_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs); +MemTxResult sev_address_space_read_debug(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, void *ptr, + hwaddr len); +MemTxResult sev_address_space_write_rom_debug(AddressSpace *as, + hwaddr addr, + MemTxAttrs attrs, + const void *ptr, + hwaddr len); #endif diff --git a/target/i386/kvm.c b/target/i386/kvm.c index cf46259534..7a2d10b745 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1838,6 +1838,10 @@ int kvm_arch_init_vcpu(CPUState *cs) kvm_init_msrs(cpu); + if (kvm_memcrypt_enabled()) { + kvm_memcrypt_set_debug_ops_cpu_state(cs); + } + r = hyperv_init_vcpu(cpu); if (r) { goto fail; diff --git a/target/i386/sev.c b/target/i386/sev.c index 3036fb3e43..b942593bc8 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -843,6 +843,191 @@ sev_set_debug_ops_memory_region(void *handle, MemoryRegion *mr) memory_region_set_ram_debug_ops(mr, &sev_ops); } +hwaddr sev_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + target_ulong pde_addr, pte_addr; + uint64_t pte; + int32_t a20_mask; + uint32_t page_offset; + int page_size; + uint64_t me_mask; + + me_mask = sev_get_me_mask(); + + *attrs = cpu_get_mem_attrs(env); + + a20_mask = x86_get_a20_mask(env); + if (!(env->cr[0] & CR0_PG_MASK)) { + pte = addr & a20_mask; + page_size = 4096; + } else if (env->cr[4] & CR4_PAE_MASK) { + target_ulong pdpe_addr; + uint64_t pde, pdpe; + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + bool la57 = env->cr[4] & CR4_LA57_MASK; + uint64_t pml5e_addr, pml5e; + uint64_t pml4e_addr, pml4e; + int32_t sext; + + /* test virtual address sign extension */ + sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47; + if (sext != 0 && sext != -1) { + return -1; + } + + if (la57) { + pml5e_addr = ((env->cr[3] & ~0xfff & me_mask) + + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; + pml5e = ldq_phys_debug(cs, pml5e_addr) & me_mask; + if (!(pml5e & PG_PRESENT_MASK)) { + return -1; + } + } else { + pml5e = env->cr[3] & me_mask; + } + + pml4e_addr = ((pml5e & PG_ADDRESS_MASK) + + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; + pml4e = ldq_phys_debug(cs, pml4e_addr) & me_mask; + if (!(pml4e & PG_PRESENT_MASK)) { + return -1; + } + pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; + pdpe = ldq_phys_debug(cs, pdpe_addr) & me_mask; + if (!(pdpe & PG_PRESENT_MASK)) { + return -1; + } + if (pdpe & PG_PSE_MASK) { + page_size = 1024 * 1024 * 1024; + pte = pdpe; + goto out; + } + + } else +#endif + { + pdpe_addr = ((env->cr[3] & ~0x1f & me_mask) + + ((addr >> 27) & 0x18)) & a20_mask; + pdpe = ldq_phys_debug(cs, pdpe_addr) & me_mask; + if (!(pdpe & PG_PRESENT_MASK)) { + return -1; + } + } + + pde_addr = ((pdpe & PG_ADDRESS_MASK) + + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; + pde = ldq_phys_debug(cs, pde_addr) & me_mask; + if (!(pde & PG_PRESENT_MASK)) { + return -1; + } + if (pde & PG_PSE_MASK) { + /* 2 MB page */ + page_size = 2048 * 1024; + pte = pde; + } else { + /* 4 KB page */ + pte_addr = ((pde & PG_ADDRESS_MASK) + + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; + page_size = 4096; + pte = ldq_phys_debug(cs, pte_addr) & me_mask; + } + if (!(pte & PG_PRESENT_MASK)) { + return -1; + } + } else { + uint32_t pde; + + /* page directory entry */ + pde_addr = ((env->cr[3] & ~0xfff & me_mask) + + ((addr >> 20) & 0xffc)) & a20_mask; + pde = x86_ldl_phys(cs, pde_addr) & me_mask; + if (!(pde & PG_PRESENT_MASK)) { + return -1; + } + if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { + pte = pde | ((pde & 0x1fe000LL) << (32 - 13)); + page_size = 4096 * 1024; + } else { + /* page directory entry */ + pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask; + pte = ldl_phys_debug(cs, pte_addr) & me_mask; + if (!(pte & PG_PRESENT_MASK)) { + return -1; + } + page_size = 4096; + } + pte = pte & a20_mask; + } + +#ifdef TARGET_X86_64 +out: +#endif + pte &= PG_ADDRESS_MASK & ~(page_size - 1); + page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1); + return pte | page_offset; +} + +MemTxResult sev_address_space_write_rom_debug(AddressSpace *as, + hwaddr addr, + MemTxAttrs attrs, + const void *ptr, + hwaddr len) +{ + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + /* + * Invoke address_space_rw debug helper + */ + return address_space_write_rom_debug(as, addr, attrs, ptr, len); +} + +MemTxResult sev_address_space_read_debug(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, void *ptr, + hwaddr len) +{ + /* set debug attrs to indicate memory access is from the debugger */ + attrs.debug = 1; + + /* + * Invoke address_space_rw debug helper + */ + return address_space_read_debug(as, addr, attrs, ptr, len); +} + +static const MemoryDebugOps sev_debug_ops = { + .read = sev_address_space_read_debug, + .write = sev_address_space_write_rom_debug +}; + +void +sev_set_debug_ops_cpu_state(void *handle, CPUState *cs) +{ + SevGuestState *s = handle; + CPUClass *cc; + + /* If policy does not allow debug then no need to register ops */ + if (s->policy & SEV_POLICY_NODBG) { + return; + } + + cc = CPU_GET_CLASS(cs); + + /* + * Override guest MMU lookup/page-table-walker with SEV specific + * callback to handle encrypted memory. + */ + cc->get_phys_page_attrs_debug = sev_cpu_get_phys_page_attrs_debug; + + address_space_set_debug_ops(&sev_debug_ops); +} + static void sev_register_types(void) { From patchwork Mon Nov 16 18:53:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalra, Ashish" X-Patchwork-Id: 11910547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A18CC2D0A3 for ; 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dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) by SA0PR12MB4557.namprd12.prod.outlook.com (2603:10b6:806:9d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Mon, 16 Nov 2020 18:53:13 +0000 Received: from SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec]) by SN6PR12MB2767.namprd12.prod.outlook.com ([fe80::d8f2:fde4:5e1d:afec%3]) with mapi id 15.20.3541.025; Mon, 16 Nov 2020 18:53:13 +0000 From: Ashish Kalra To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, rth@twiddle.net, armbru@redhat.com, dgilbert@redhat.com, ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, marcel.apfelbaum@gmail.com, mtosatti@redhat.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, ssg.sos.patches@amd.com Subject: [PATCH 11/11] target/i386: clear C-bit when walking SEV guest page table Date: Mon, 16 Nov 2020 18:53:02 +0000 Message-Id: <82ab6378638ce00118bff1c006bd346be598caec.1605316268.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM6PR06CA0030.namprd06.prod.outlook.com (2603:10b6:5:120::43) To SN6PR12MB2767.namprd12.prod.outlook.com (2603:10b6:805:75::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ashkalra_ubuntu_server.amd.com (165.204.77.1) by DM6PR06CA0030.namprd06.prod.outlook.com (2603:10b6:5:120::43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: xgPHY3cN2q9jgNw48iRwD+ziTp4cyuu4L4caLGyv5emzICAzTndBRF3pUpYGtyfB9c+XWZN/k9D3SsINDPaEmWqb0pnQNZqPWNNYI7M4zKgtuhGB9+8+/4HrOnQLPyMPane4vlf2F0uPyieQD8N66C4p6/7SPOSlUN9ps3laEk4ZO6DdCb4WFfa6qvkfauqGXIfhNDrGTax9GWo0PuoHDQ2fTGYgWhvdpY+iY/dOjiAkhTTaprvrTe927Nn2RYccXQXxKb3CaJE8w5xYVXtURTKISClwXN0JmYfkH8IGAaHDvPCNj046iBDgarv92UL2wKZhzTqJLjJQYcmC154yUjGGNRAdP37L0QZy8auZaMkcObm1+bSCDzWN4kJEzrkWcfnCXBsGXhcoz7UPOW/obTy3i8IngNOp0ZV+vbbsD2wngAGgZlkrflPVWKZtS5eykA/OXljaThZ/o+oszy4CTzkCWcg218U717miewa7oP/8mdWkyPdj8jkKeVUx7KBAe3iMt/vHWeIqXy70CyHiTejrsmVnrjWtnAYcxLJfxDKwWjhwB1Qr1IJSKF15GWcX8I/0g7mRueqIIbSJ42HnDHFmvkbwxkgvSbB0i964aZaO1X/hdBhFeWfg2iAClbhytdhCnH/pUAfYmV+XZPcDnu+ssPvcNHGw437HawEfE8PVvzP6W9nr0oUeb/59yUnssX4jNmKDTqQQqTD2cfjpHrOxNQvnE9dpkJo7pkQbRYDF32gg8OpO6eCV83rIdQ5u/sUKLsikh1yfa99UFNPl1AFmOAT+DIuHp/ihX3hdjsqT2BzMIq1bNf19ZivoWR6j6ohmObFtDK6EvACcnPiplnk5j56L0XX9/mHcPz+4QSiih6IGg82cWwzFj7J7sLOOEPaOL1pbGfTeElmC1x1t/w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a79cfd89-ac0f-460f-d47e-08d88a60deac X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2767.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2020 18:53:13.2725 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +MzcMe2PuLSFC2czRN0/LkmtIORiahutx/07mUwpRKhiN7dfaTDd4D7f23Ys9iLQKSdHFStuQaA3cXs06w2DvQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4557 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Brijesh Singh In SEV-enabled guest the pte entry will have C-bit set, we need to clear the C-bit when walking the page table. This ensures that the proper page address translation occurs and, with the C-bit reset, the true physical address is got. The pte_mask to be used during guest page table walk is added as a vendor specific assist/hook as part of the new MemoryDebugOps and available via the new debug API interface cpu_physical_memory_pte_mask_debug(). Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- include/exec/cpu-common.h | 3 ++ include/exec/memory.h | 1 + softmmu/physmem.c | 13 +++++++- target/i386/monitor.c | 70 +++++++++++++++++++++++++-------------- target/i386/sev.c | 3 +- 5 files changed, 63 insertions(+), 27 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index d2089e6873..3374573d39 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -96,6 +96,9 @@ static inline void cpu_physical_memory_write(hwaddr addr, { cpu_physical_memory_rw(addr, (void *)buf, len, true); } + +uint64_t cpu_physical_memory_pte_mask_debug(void); + void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, bool is_write); diff --git a/include/exec/memory.h b/include/exec/memory.h index 74f2dcec00..ebe8ffc1eb 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2428,6 +2428,7 @@ typedef struct MemoryDebugOps { MemTxResult (*write)(AddressSpace *as, hwaddr phys_addr, MemTxAttrs attrs, const void *buf, hwaddr len); + uint64_t (*pte_mask)(void); } MemoryDebugOps; void address_space_set_debug_ops(const MemoryDebugOps *ops); diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 6945bd5efe..fc6b5588fc 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -166,9 +166,15 @@ struct DirtyBitmapSnapshot { unsigned long dirty[]; }; +static uint64_t address_space_pte_mask(void) +{ + return ~0; +} + static const MemoryDebugOps default_debug_ops = { .read = address_space_read, - .write = address_space_write_rom + .write = address_space_write_rom, + .pte_mask = address_space_pte_mask }; static const MemoryDebugOps *debug_ops = &default_debug_ops; @@ -3401,6 +3407,11 @@ void cpu_physical_memory_rw_debug(hwaddr addr, uint8_t *buf, } +uint64_t cpu_physical_memory_pte_mask_debug(void) +{ + return debug_ops->pte_mask(); +} + int64_t address_space_cache_init(MemoryRegionCache *cache, AddressSpace *as, hwaddr addr, diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 9ca9c677a5..c73cac04cb 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -106,16 +106,20 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env) unsigned int l1, l2, l3; uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask = cpu_physical_memory_pte_mask_debug(); pdp_addr = env->cr[3] & ~0x1f; + pdp_addr &= me_mask; for (l1 = 0; l1 < 4; l1++) { cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { /* 2M pages with PAE, CR4.PSE is ignored */ @@ -126,7 +130,7 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pt_addr + l3 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l1 << 30) + (l2 << 21) + (l3 << 12), @@ -148,10 +152,13 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask = cpu_physical_memory_pte_mask_debug(); for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); + pml4e = le64_to_cpu(pml4e & me_mask); if (!(pml4e & PG_PRESENT_MASK)) { continue; } @@ -159,7 +166,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); if (!(pdpe & PG_PRESENT_MASK)) { continue; } @@ -174,7 +181,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); if (!(pde & PG_PRESENT_MASK)) { continue; } @@ -191,7 +198,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12), @@ -208,13 +215,17 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env) uint64_t l0; uint64_t pml5e; uint64_t pml5_addr; + uint64_t me_mask; - pml5_addr = env->cr[3] & 0x3fffffffff000ULL; + me_mask = cpu_physical_memory_pte_mask_debug(); + + pml5_addr = env->cr[3] & 0x3fffffffff000ULL & me_mask; for (l0 = 0; l0 < 512; l0++) { cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); - pml5e = le64_to_cpu(pml5e); + pml5e = le64_to_cpu(pml5e & me_mask); if (pml5e & PG_PRESENT_MASK) { - tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); + tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL & + cpu_physical_memory_pte_mask_debug()); } } } @@ -326,19 +337,22 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env) uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; hwaddr start, end; + uint64_t me_mask; - pdp_addr = env->cr[3] & ~0x1f; + me_mask = cpu_physical_memory_pte_mask_debug(); + + pdp_addr = env->cr[3] & ~0x1f & me_mask; last_prot = 0; start = -1; for (l1 = 0; l1 < 4; l1++) { cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); end = l1 << 30; if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); end = (l1 << 30) + (l2 << 21); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -350,7 +364,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pt_addr + l3 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); end = (l1 << 30) + (l2 << 21) + (l3 << 12); if (pte & PG_PRESENT_MASK) { prot = pte & pde & (PG_USER_MASK | PG_RW_MASK | @@ -383,19 +397,22 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask = cpu_physical_memory_pte_mask_debug(); - pml4_addr = env->cr[3] & 0x3fffffffff000ULL; + pml4_addr = env->cr[3] & 0x3fffffffff000ULL & me_mask; last_prot = 0; start = -1; for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); + pml4e = le64_to_cpu(pml4e & me_mask); end = l1 << 39; if (pml4e & PG_PRESENT_MASK) { pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); end = (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { if (pdpe & PG_PSE_MASK) { @@ -408,7 +425,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); end = (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -423,7 +440,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); end = (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12); if (pte & PG_PRESENT_MASK) { @@ -464,13 +481,16 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) uint64_t l0, l1, l2, l3, l4; uint64_t pml5e, pml4e, pdpe, pde, pte; uint64_t pml5_addr, pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask = cpu_physical_memory_pte_mask_debug(); - pml5_addr = env->cr[3] & 0x3fffffffff000ULL; + pml5_addr = env->cr[3] & 0x3fffffffff000ULL & me_mask; last_prot = 0; start = -1; for (l0 = 0; l0 < 512; l0++) { cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); - pml5e = le64_to_cpu(pml5e); + pml5e = le64_to_cpu(pml5e & me_mask); end = l0 << 48; if (!(pml5e & PG_PRESENT_MASK)) { prot = 0; @@ -481,7 +501,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pml4_addr = pml5e & 0x3fffffffff000ULL; for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); + pml4e = le64_to_cpu(pml4e & me_mask); end = (l0 << 48) + (l1 << 39); if (!(pml4e & PG_PRESENT_MASK)) { prot = 0; @@ -492,7 +512,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); end = (l0 << 48) + (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { prot = 0; @@ -511,7 +531,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { prot = 0; @@ -531,7 +551,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) for (l4 = 0; l4 < 512; l4++) { cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12); if (pte & PG_PRESENT_MASK) { diff --git a/target/i386/sev.c b/target/i386/sev.c index b942593bc8..97726a639f 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -1003,7 +1003,8 @@ MemTxResult sev_address_space_read_debug(AddressSpace *as, hwaddr addr, static const MemoryDebugOps sev_debug_ops = { .read = sev_address_space_read_debug, - .write = sev_address_space_write_rom_debug + .write = sev_address_space_write_rom_debug, + .pte_mask = sev_get_me_mask, }; void