From patchwork Tue Nov 17 01:25:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 11911129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A39AFC63777 for ; Tue, 17 Nov 2020 01:24:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E48424690 for ; Tue, 17 Nov 2020 01:24:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730158AbgKQBYl (ORCPT ); Mon, 16 Nov 2020 20:24:41 -0500 Received: from mga07.intel.com ([134.134.136.100]:34910 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726908AbgKQBYl (ORCPT ); Mon, 16 Nov 2020 20:24:41 -0500 IronPort-SDR: 8fwgFIoGeC2nzzHEMWV/WzBKO4YY98qhCsiTLVt+DOO2ZWMLI34Ss4YrcbhVBKERUzvbJoKSY8 5KGrZxJApV6w== X-IronPort-AV: E=McAfee;i="6000,8403,9807"; a="234994419" X-IronPort-AV: E=Sophos;i="5.77,484,1596524400"; d="scan'208";a="234994419" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 17:24:36 -0800 IronPort-SDR: OhgRdexRzr1QR6Gy1/KxA7T18sCA7sIpzDpCZj+xBPJ3PJQj959MM1kxDfjkdceVPcMvOqq4yz D5z7FK9FHX8w== X-IronPort-AV: E=Sophos;i="5.77,484,1596524400"; d="scan'208";a="310060650" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.140]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 17:24:36 -0800 From: matthew.gerlach@linux.intel.com To: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, mdf@kernel.org, hao.wu@intel.com, trix@redhat.com, linux-doc@vger.kernel.org, corbet@lwn.net Cc: Matthew Gerlach Subject: [PATCH 1/2] fpga: dfl: refactor cci_enumerate_feature_devs() Date: Mon, 16 Nov 2020 17:25:51 -0800 Message-Id: <20201117012552.262149-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201117012552.262149-1-matthew.gerlach@linux.intel.com> References: <20201117012552.262149-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Matthew Gerlach In preparation of looking for dfls based on a vendor specific pcie capability, move code that assumes Bar0/offset0 as start of DFL to its own function. Signed-off-by: Matthew Gerlach Reviewed-by: Tom Rix --- drivers/fpga/dfl-pci.c | 86 ++++++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 37 deletions(-) diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index a2203d03c9e2..b1b157b41942 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -119,49 +119,20 @@ static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) return table; } -/* enumerate feature devices under pci device */ -static int cci_enumerate_feature_devs(struct pci_dev *pcidev) +static int find_dfl_in_bar0(struct pci_dev *pcidev, + struct dfl_fpga_enum_info *info) { - struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); - int port_num, bar, i, nvec, ret = 0; - struct dfl_fpga_enum_info *info; - struct dfl_fpga_cdev *cdev; resource_size_t start, len; + int port_num, bar, i; void __iomem *base; - int *irq_table; + int ret = 0; u32 offset; u64 v; - /* allocate enumeration info via pci_dev */ - info = dfl_fpga_enum_info_alloc(&pcidev->dev); - if (!info) - return -ENOMEM; - - /* add irq info for enumeration if the device support irq */ - nvec = cci_pci_alloc_irq(pcidev); - if (nvec < 0) { - dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec); - ret = nvec; - goto enum_info_free_exit; - } else if (nvec) { - irq_table = cci_pci_create_irq_table(pcidev, nvec); - if (!irq_table) { - ret = -ENOMEM; - goto irq_free_exit; - } - - ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table); - kfree(irq_table); - if (ret) - goto irq_free_exit; - } - - /* start to find Device Feature List in Bar 0 */ + /* start to find Device Feature List from Bar 0 */ base = cci_pci_ioremap_bar0(pcidev); - if (!base) { - ret = -ENOMEM; - goto irq_free_exit; - } + if (!base) + return -ENOMEM; /* * PF device has FME and Ports/AFUs, and VF device only has one @@ -208,12 +179,53 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev) dfl_fpga_enum_info_add_dfl(info, start, len); } else { ret = -ENODEV; - goto irq_free_exit; } /* release I/O mappings for next step enumeration */ pcim_iounmap_regions(pcidev, BIT(0)); + + return ret; +} + +/* enumerate feature devices under pci device */ +static int cci_enumerate_feature_devs(struct pci_dev *pcidev) +{ + struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); + struct dfl_fpga_enum_info *info; + struct dfl_fpga_cdev *cdev; + int nvec, ret = 0; + int *irq_table; + + /* allocate enumeration info via pci_dev */ + info = dfl_fpga_enum_info_alloc(&pcidev->dev); + if (!info) + return -ENOMEM; + + /* add irq info for enumeration if the device support irq */ + nvec = cci_pci_alloc_irq(pcidev); + if (nvec < 0) { + dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec); + ret = nvec; + goto enum_info_free_exit; + } else if (nvec) { + irq_table = cci_pci_create_irq_table(pcidev, nvec); + if (!irq_table) { + ret = -ENOMEM; + goto irq_free_exit; + } + + ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table); + kfree(irq_table); + if (ret) + goto irq_free_exit; + } + + ret = find_dfl_in_bar0(pcidev, info); + + if (ret) + goto irq_free_exit; + /* start enumeration with prepared enumeration information */ cdev = dfl_fpga_feature_devs_enumerate(info); if (IS_ERR(cdev)) { From patchwork Tue Nov 17 01:25:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 11911125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57712C6379F for ; Tue, 17 Nov 2020 01:24:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 120C224687 for ; Tue, 17 Nov 2020 01:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731557AbgKQBYo (ORCPT ); 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16 Nov 2020 17:24:36 -0800 From: matthew.gerlach@linux.intel.com To: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, mdf@kernel.org, hao.wu@intel.com, trix@redhat.com, linux-doc@vger.kernel.org, corbet@lwn.net Cc: Matthew Gerlach Subject: [PATCH 2/2] fpga: dfl: look for vendor specific capability Date: Mon, 16 Nov 2020 17:25:52 -0800 Message-Id: <20201117012552.262149-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201117012552.262149-1-matthew.gerlach@linux.intel.com> References: <20201117012552.262149-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Matthew Gerlach A DFL may not begin at offset 0 of BAR 0. A PCIe vendor specific capability can be used to specify the start of a number of DFLs. Signed-off-by: Matthew Gerlach Reported-by: kernel test robot --- Documentation/fpga/dfl.rst | 10 +++++ drivers/fpga/dfl-pci.c | 88 +++++++++++++++++++++++++++++++++++++- 2 files changed, 97 insertions(+), 1 deletion(-) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 0404fe6ffc74..c81ceb1e79e2 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -501,6 +501,16 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Location of DFLs on PCI bus +=========================== +The start of the DFL is assumed to be offset 0 of bar 0. +Alternatively, a vendor specific capability structure can be used to +specify the location of one or more DFLs. Intel has reserved the +vendor specific id of 0x43 for this purpose. The vendor specific +data begins with a 4 byte count of the number of DFLs followed 4 byte +Offset/BIR fields for each DFL. Bits 2:0 of Offset/BIR field indicates +the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are +zero. Open discussion =============== diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index b1b157b41942..5418e8bf2496 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -27,6 +27,13 @@ #define DRV_VERSION "0.8" #define DRV_NAME "dfl-pci" +#define PCI_VNDR_ID_DFLS 0x43 + +#define PCI_VNDR_DFLS_CNT_OFFSET 8 +#define PCI_VNDR_DFLS_RES_OFFSET 0x0c + +#define PCI_VND_DFLS_RES_BAR_MASK 0x7 + struct cci_drvdata { struct dfl_fpga_cdev *cdev; /* container device */ }; @@ -119,6 +126,82 @@ static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) return table; } +static int find_dfl_in_cfg(struct pci_dev *pcidev, + struct dfl_fpga_enum_info *info) +{ + u32 bar, offset, vndr_hdr, dfl_cnt, dfl_res; + int dfl_res_off, i, voff = 0; + resource_size_t start, len; + + while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) { + + pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr); + + dev_dbg(&pcidev->dev, + "vendor-specific capability id 0x%x, rev 0x%x len 0x%x\n", + PCI_VNDR_HEADER_ID(vndr_hdr), + PCI_VNDR_HEADER_REV(vndr_hdr), + PCI_VNDR_HEADER_LEN(vndr_hdr)); + + if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VNDR_ID_DFLS) + break; + } + + if (!voff) { + dev_dbg(&pcidev->dev, "%s no VSEC found\n", __func__); + return -ENODEV; + } + + pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT_OFFSET, &dfl_cnt); + dev_info(&pcidev->dev, "dfl_cnt %d\n", dfl_cnt); + for (i = 0; i < dfl_cnt; i++) { + dfl_res_off = voff + PCI_VNDR_DFLS_RES_OFFSET + + (i * sizeof(dfl_res)); + pci_read_config_dword(pcidev, dfl_res_off, &dfl_res); + + dev_dbg(&pcidev->dev, "dfl_res 0x%x\n", dfl_res); + + bar = dfl_res & PCI_VND_DFLS_RES_BAR_MASK; + + if (bar >= PCI_STD_NUM_BARS) { + dev_err(&pcidev->dev, "%s bad bar number %d\n", + __func__, bar); + return -EINVAL; + } + + len = pci_resource_len(pcidev, bar); + + if (len == 0) { + dev_err(&pcidev->dev, "%s unmapped bar number %d\n", + __func__, bar); + return -EINVAL; + } + + offset = dfl_res & ~PCI_VND_DFLS_RES_BAR_MASK; + + if (offset >= len) { + dev_err(&pcidev->dev, "%s bad offset %u >= %llu\n", + __func__, offset, len); + return -EINVAL; + } + + dev_info(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bar, offset); + + start = pci_resource_start(pcidev, bar) + offset; + len -= offset; + + if (!PAGE_ALIGNED(start)) { + dev_err(&pcidev->dev, "%s unaliged start 0x%llx\n", + __func__, start); + return -EINVAL; + } + + dfl_fpga_enum_info_add_dfl(info, start, len); + } + + return 0; +} + static int find_dfl_in_bar0(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info) { @@ -221,7 +304,10 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev) goto irq_free_exit; } - ret = find_dfl_in_bar0(pcidev, info); + ret = find_dfl_in_cfg(pcidev, info); + + if (ret) + ret = find_dfl_in_bar0(pcidev, info); if (ret) goto irq_free_exit;