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[139.181.33.34]) by smtp.gmail.com with ESMTPSA id b14sm30188632wrq.47.2020.11.17.23.36.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Nov 2020 23:36:44 -0800 (PST) From: mdurnev@gmail.com X-Google-Original-From: mikhail_durnev@mentor.com To: linux-kernel@vger.kernel.org Subject: [PATCH 1/3] drm/mipi-dbi: Add support for Type B Date: Wed, 18 Nov 2020 17:35:43 +1000 Message-Id: <1605684945-29727-2-git-send-email-mikhail_durnev@mentor.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605684945-29727-1-git-send-email-mikhail_durnev@mentor.com> References: <1605684945-29727-1-git-send-email-mikhail_durnev@mentor.com> X-Mailman-Approved-At: Wed, 18 Nov 2020 08:01:05 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikhail_durnev@mentor.com, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mikhail Durnev Intel 8080 type (Type B) parallel bus over GPIO. The parallel bus is implemented partially. It supports only write operations from the host to the display. Read operations would require switching GPIO mode between input and output back and forth. But this implementation is very simple, and GPIO mode can be set for all used pins to output once at initialization. It is enough to support only write operations to initialize displays and output video data. The bus driver returns EOPNOTSUPP for all read operations requested through a display driver. Bit banging is used to transmit data over the parallel bus from host to display. There are two numbers that contol timings: wr_up_delay and wr_down_delay. They should be provided by the display driver. The first number is related to the write control pulse duration, and the second number is related to the write cycle duration that can be found in the specification of the display. Signed-off-by: Mikhail Durnev Reported-by: kernel test robot --- drivers/gpu/drm/drm_mipi_dbi.c | 116 ++++++++++++++++++++++++++++++++++++++++- include/drm/drm_mipi_dbi.h | 30 ++++++++++- 2 files changed, 144 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c index 230c4fd..4d2e108 100644 --- a/drivers/gpu/drm/drm_mipi_dbi.c +++ b/drivers/gpu/drm/drm_mipi_dbi.c @@ -61,7 +61,7 @@ * 3. 8-bit with the Data/Command signal as a separate D/CX pin * * Currently mipi_dbi only supports Type C options 1 and 3 with - * mipi_dbi_spi_init(). + * mipi_dbi_spi_init() and Type B with mipi_dbi_gpio_init(). */ #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \ @@ -1158,6 +1158,120 @@ EXPORT_SYMBOL(mipi_dbi_spi_transfer); #endif /* CONFIG_SPI */ +/* + * This function implements data transfer only from host to display. + */ +static void mipi_dbi_gpio_transfer(struct mipi_dbi *dbi, u16 data) +{ + unsigned long ldata = data; + + /* + * Set W/R to low to start transfer. + * Set DB bits with provided data when W/R is low. + */ + gpiod_set_value_cansleep(dbi->wr, 0); + gpiod_set_array_value_cansleep(dbi->db->ndescs, dbi->db->desc, + dbi->db->info, &ldata); + + /* + * The bus usually needs additional delay. + */ + ndelay(dbi->wr_up_delay); + + /* + * Set W/R to high to indicate that DB lines are set. + */ + gpiod_set_value_cansleep(dbi->wr, 1); + + /* + * The connected display needs some time to read the data. + */ + ndelay(dbi->wr_down_delay); +} + +static int mipi_dbi_gpio_command(struct mipi_dbi *dbi, u8 *cmd, + u8 *par, size_t num) +{ + int i; + + /* + * Read commands are not currently supported. + */ + if (mipi_dbi_command_is_read(dbi, *cmd)) + return -EOPNOTSUPP; + + MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); + + gpiod_set_value_cansleep(dbi->dc, 0); + mipi_dbi_gpio_transfer(dbi, (u16)*cmd); + gpiod_set_value_cansleep(dbi->dc, 1); + + if (dbi->db->ndescs == 16 && + (*cmd == MIPI_DCS_WRITE_MEMORY_START || + *cmd == MIPI_DCS_WRITE_MEMORY_CONTINUE)) { + /* + * Only a couple of commands supports 16-bit transfer. + */ + for (i = 0; i < num; i += 2) { + u16 data = *(u16 *)&par[i]; + + if (dbi->swap_bytes) + data = (data >> 8) | (data << 8); + + mipi_dbi_gpio_transfer(dbi, data); + } + } else { + for (i = 0; i < num; i++) { + /* + * Other commands ignore most significant bits. + */ + mipi_dbi_gpio_transfer(dbi, (u16)par[i]); + } + } + + return 0; +} + +/** + * mipi_dbi_gpio_init - Initialize MIPI DBI Type B interface implemented via GPIO + * @dbi: MIPI DBI structure to initialize + * @dc: D/C gpio + * @wr: W/R gpio + * @db: DB gpios + * @wr_up_delay: Delay after setting DB and before changing W/R from low to high + * @wr_down_delay: Delay after changing W/R from low to high + * + * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the + * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or + * a driver-specific init. + * + * Returns: + * Zero on success, negative error code on failure. + */ +int mipi_dbi_gpio_init(struct mipi_dbi *dbi, struct gpio_desc *dc, + struct gpio_desc *wr, struct gpio_descs *db, + unsigned long wr_up_delay, unsigned long wr_down_delay) +{ + dbi->spi = 0; /* Type B uses GPIO lines rather than SPI */ + + dbi->read_commands = mipi_dbi_dcs_read_commands; + dbi->command = mipi_dbi_gpio_command; + + dbi->dc = dc; + dbi->wr = wr; + dbi->db = db; + dbi->wr_up_delay = wr_up_delay; + dbi->wr_down_delay = wr_down_delay; + + if (mipi_dbi_machine_little_endian()) + dbi->swap_bytes = true; + + mutex_init(&dbi->cmdlock); + + return 0; +} +EXPORT_SYMBOL(mipi_dbi_gpio_init); + #ifdef CONFIG_DEBUG_FS static ssize_t mipi_dbi_debugfs_command_write(struct file *file, diff --git a/include/drm/drm_mipi_dbi.h b/include/drm/drm_mipi_dbi.h index c2827ce..c4be5ca 100644 --- a/include/drm/drm_mipi_dbi.h +++ b/include/drm/drm_mipi_dbi.h @@ -55,7 +55,7 @@ struct mipi_dbi { struct spi_device *spi; /** - * @dc: Optional D/C gpio. + * @dc: D/C gpio, optional for Type C and mandatory for Type B. */ struct gpio_desc *dc; @@ -68,6 +68,31 @@ struct mipi_dbi { * @tx_buf9_len: Size of tx_buf9. */ size_t tx_buf9_len; + + /* Type B specific */ + + /** + * @wr: W/R gpio. + */ + struct gpio_desc *wr; + + /** + * @db: Data Bus gpios (usually 8 or 16). + */ + struct gpio_descs *db; + + /** + * @wr_up_delay: Delay after setting all db lines and before changing + * wr from low to high. + */ + unsigned long wr_up_delay; + + /** + * @wr_down_delay: Delay after changing wr from low to high and + * before wr can be changed again from hight to low to start a new + * write operation. + */ + unsigned long wr_down_delay; }; /** @@ -139,6 +164,9 @@ static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm) int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, struct gpio_desc *dc); +int mipi_dbi_gpio_init(struct mipi_dbi *dbi, struct gpio_desc *dc, + struct gpio_desc *wr, struct gpio_descs *db, + unsigned long wr_up_delay, unsigned long wr_down_delay); int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev, const struct drm_simple_display_pipe_funcs *funcs, const uint32_t *formats, unsigned int format_count, From patchwork Wed Nov 18 07:35:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: mdurnev@gmail.com X-Patchwork-Id: 11914055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBD47C63697 for ; Wed, 18 Nov 2020 08:01:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BFA620B80 for ; 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[139.181.33.34]) by smtp.gmail.com with ESMTPSA id b14sm30188632wrq.47.2020.11.17.23.36.45 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Nov 2020 23:36:46 -0800 (PST) From: mdurnev@gmail.com X-Google-Original-From: mikhail_durnev@mentor.com To: linux-kernel@vger.kernel.org Subject: [PATCH 2/3] drm/tiny: Add driver for ili9341 with parallel bus Date: Wed, 18 Nov 2020 17:35:44 +1000 Message-Id: <1605684945-29727-3-git-send-email-mikhail_durnev@mentor.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605684945-29727-1-git-send-email-mikhail_durnev@mentor.com> References: <1605684945-29727-1-git-send-email-mikhail_durnev@mentor.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Nov 2020 08:01:05 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikhail_durnev@mentor.com, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mikhail Durnev MRB2801 display module [1] is an example of ILI9341 display that connects to Intel 8080 parallel bus. Its connector is compatible with the ALIENTEK STM32 development board. It can be used with the drm/mipi-dbi bus driver if the bus is emulated with GPIO. [1] http://www.lcdwiki.com/2.8inch_16BIT_Module_ILI9341_SKU:MRB2801 Signed-off-by: Mikhail Durnev --- drivers/gpu/drm/tiny/Kconfig | 13 ++ drivers/gpu/drm/tiny/Makefile | 1 + drivers/gpu/drm/tiny/ili9341_gpio.c | 290 ++++++++++++++++++++++++++++++++++++ 3 files changed, 304 insertions(+) create mode 100644 drivers/gpu/drm/tiny/ili9341_gpio.c diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig index 2b6414f..e48e268 100644 --- a/drivers/gpu/drm/tiny/Kconfig +++ b/drivers/gpu/drm/tiny/Kconfig @@ -66,6 +66,19 @@ config TINYDRM_ILI9341 If M is selected the module will be called ili9341. +config TINYDRM_ILI9341_GPIO + tristate "DRM support for ILI9341 display panels with parallel bus interface over GPIO" + depends on DRM + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_MIPI_DBI + select BACKLIGHT_CLASS_DEVICE + help + DRM driver for the following Ilitek ILI9341 panels: + * MRB2801 2.8" 240x320 TFT + + If M is selected the module will be called ili9341_gpio. + config TINYDRM_ILI9486 tristate "DRM support for ILI9486 display panels" depends on DRM && SPI diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile index 6ae4e9e5..1ad2c0d 100644 --- a/drivers/gpu/drm/tiny/Makefile +++ b/drivers/gpu/drm/tiny/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_GM12U320) += gm12u320.o obj-$(CONFIG_TINYDRM_HX8357D) += hx8357d.o obj-$(CONFIG_TINYDRM_ILI9225) += ili9225.o obj-$(CONFIG_TINYDRM_ILI9341) += ili9341.o +obj-$(CONFIG_TINYDRM_ILI9341_GPIO) += ili9341_gpio.o obj-$(CONFIG_TINYDRM_ILI9486) += ili9486.o obj-$(CONFIG_TINYDRM_MI0283QT) += mi0283qt.o obj-$(CONFIG_TINYDRM_REPAPER) += repaper.o diff --git a/drivers/gpu/drm/tiny/ili9341_gpio.c b/drivers/gpu/drm/tiny/ili9341_gpio.c new file mode 100644 index 0000000..de8a63b8 --- /dev/null +++ b/drivers/gpu/drm/tiny/ili9341_gpio.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DRM driver for Ilitek ILI9341 panels with parallel bus interface + * + * Copyright 2020 Mikhail Durnev + * + * Based on ili9341.c: + * Copyright 2018 David Lechner + * + * Based on mi0283qt.c: + * Copyright 2016 Noralf Trønnes + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include