From patchwork Thu Nov 19 08:02:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavana Sharma X-Patchwork-Id: 11916667 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A04DC6379D for ; Thu, 19 Nov 2020 08:03:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 313CE2064B for ; Thu, 19 Nov 2020 08:03:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=digi.com header.i=@digi.com header.b="IvDUlNcR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726528AbgKSIDG (ORCPT ); Thu, 19 Nov 2020 03:03:06 -0500 Received: from outbound-ip24a.ess.barracuda.com ([209.222.82.206]:54310 "EHLO outbound-ip24a.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725850AbgKSIDF (ORCPT ); Thu, 19 Nov 2020 03:03:05 -0500 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10lp2107.outbound.protection.outlook.com [104.47.58.107]) by mx2.us-east-2a.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 19 Nov 2020 08:02:54 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kYEPT+1A14hxnC/4GZWdz0vHOgFKUTHdJpzssBWZX6xqAuF4ZM+NMh8lOr2KPj0Ygd4mCAjJKdbQBwXy7lLXV4cCaGoRvSIFuw+CR3GY7PtnjXJfR5h0ygWGqO7AfnwMUPqogYeQxXeiMUXw670voMAYAfEKkQSenc2iEGf9DSShF9rcx8h3TY4f/jfGM7Zzk5zpX2y2GKrS0+zwcVZYSfT1Z0IHIqGmcjkBt+LItu5R2djLk3gbJu7liGhAwhIy8jsHU1eQ+QooeY/8AKcxfGEW9275nqliO5CaNXAaYsSqohgIoVrTVGR2bC4f2oVbFM7vCCX07AeMMPDYdVLgyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xZyIIcbULkqFuqRRVCOgfB002r4JFCtYt2FmxhjIbMk=; b=cd5kxUmUj5N+x5coFd3Z6M0WFpXQF33/DLDy6VNPGUWVfTYJR/G2RcYtbQtfwJQfhidwKo+dmO0LBtWs89K78JREFixHnYVDY2H3wNS5cuvheADo0mCAhyuv0i3SwLY2j0bnNXDIc3RiPRfY9Vh+jxG+c9+Vmp280Dw8VosZ4L2It8CUl0YkfAR6WXFI205iUeiGBbN81RyebWm7sp6TzIgNen1l9+mK1ECm/KvkoX7aKybbzcbMt6UHGN9lHk4Pv5QfBO2fsLNMDABx7dynkYOeQfhpZTNLripFROBKurkudlv5VotFk03auHyo/ktmif283480v7wkM9bCBJQYCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=digi.com; dmarc=pass action=none header.from=digi.com; dkim=pass header.d=digi.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digi.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xZyIIcbULkqFuqRRVCOgfB002r4JFCtYt2FmxhjIbMk=; b=IvDUlNcRozWKt0Tp1gGSmtnAm7znFL0yXKP5euXgcQXZtfxtOXFXcGVmlHJ8xLmaj2dsXbPT0SHQshCuZ+T/WEmyERggMr13OLwspH6WtC5/sH6oUmEsHkO6QYoLYwge84FW0X9HoH+oCy+IldVGvSdfc83EB6NuvWjCZmqlzNA= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=digi.com; Received: from MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) by MN2PR10MB4399.namprd10.prod.outlook.com (2603:10b6:208:1d9::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20; Thu, 19 Nov 2020 08:02:52 +0000 Received: from MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32]) by MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32%9]) with mapi id 15.20.3564.028; Thu, 19 Nov 2020 08:02:52 +0000 From: Pavana Sharma To: kuba@kernel.org Cc: andrew@lunn.ch, ashkan.boldaji@digi.com, davem@davemloft.net, f.fainelli@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, marek.behun@nic.cz, netdev@vger.kernel.org, pavana.sharma@digi.com, vivien.didelot@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 1/4] dt-bindings: net: Add 5GBASER phy interface mode Date: Thu, 19 Nov 2020 18:02:27 +1000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [14.200.39.236] X-ClientProxiedBy: SYAPR01CA0046.ausprd01.prod.outlook.com (2603:10c6:1:1::34) To MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (14.200.39.236) by SYAPR01CA0046.ausprd01.prod.outlook.com (2603:10c6:1:1::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20 via Frontend Transport; Thu, 19 Nov 2020 08:02:47 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4e0eb68a-2210-4781-4fbf-08d88c61836f X-MS-TrafficTypeDiagnostic: MN2PR10MB4399: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:296; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xepD4bEtHKEwsuhyakMgleAZY9uOIP7pDVn9CmKuYoqhlwfdpEONbEuJ5/vGlqFi5AtFKqSshrDRXRTe1YSJpJ6fH5NpP+7hBrmgiuL+5vXyhV+hXn5PJoJY+BKd7mW28FzX/+s7H3GoJ3OgOt45iUGi/9HF56hunxRUDnJgycGuvwew+lDpc/9OqvCyGaZy+E/eyU+XhYpY/Qy0S/NNORmjFyIMQdZ4Sjf4ZMmpe5m+B7dOp4KznBa/15T4s0aPXnEpI0B7yqg5Aa1pWzoLK2IXj5NWN33RlKrjx3h67FklJbgESyZRh4lLtUrsVWAamCn9mIU2BWbJjCmYt/3WY3wiCwdLSa15acMXS+0hbdKpxEqrKa0hCkaAb7UnPzr4 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR10MB4174.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(346002)(376002)(366004)(136003)(396003)(39850400004)(7416002)(6486002)(956004)(8676002)(44832011)(26005)(86362001)(6506007)(8936002)(6512007)(6916009)(36756003)(52116002)(478600001)(16526019)(66476007)(66556008)(2906002)(316002)(5660300002)(2616005)(4744005)(186003)(4326008)(6666004)(69590400008)(66946007);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: d7PbkK9esf3C+K9wRSwHs90hrFpw5aqNumwRiXajKIMBrOCXZ9iJSN/z+gQUHJy0+CC4AgnH28XLt+9zNzu+F4C6cYwLiJlNSA3rZWaJLBN9PWJ2bCNOrLiJggjCv/Qm9cPY+dupQQczlDrUxRYxmy1+uxLvpkFJTmrpwwCQzpVjadA/OtZj93v99vn6ynyp01eYQyFisFpQcspgmpRO6fIVwd9nHxJ8Ay4lCl7XKVxVJwmnDINnuMuZh7qowYOXFqRXFW40EsO0U9nITJi/AnisDaTsRfLJfw9X89NTeC74ZmIvJSpRS/QaGRZkx+TTX4FP8uvrE+/db89r2dD575BzOTzyoU3yy7iJ8Wc8GMmu6QbLuXJFTCMHxXntQE1YVSW3ctY3O3KwSp8xNiGwEVtK24aWB0qRkzrdMhYjgcsHqBNNr6mP3zn9GzJ7sb66Vo/q3GlgCzhAjXsM/B1xuMVZmJIQcQYIGaKUW6O4nq277MYjHBDx1uNm9P0+PpgHpLOy9+Ka20NkMVSxLdpyWVuggiFj/EqV+pPnby20Pi0Jcm1CvGsT9vom5ey2GBVcflySX5/ytqHywImC8qKeoGRljR26jIyGYzN9wuD2/7Q8TXT/T1849EFjAnKKPubWQUVbXT0mD3zZeIhcCpcIoKYTfh/JfzQvaDaaBdZVitT39eLrbRY+TvzC+5Ft9nQsWjO/oltpARqvYEFGhtHrrBVOvhYUG3xmIPYyllSf1dlE4zG0GOTHWrSWyYthbYiCjI8CnPGwVUcIytXbNDzXkMDCuNE+S0arzX49bkGFTYB2rXDO6bdHTAfCL4LS7dphqGIULqZbKri+GuQenVInjBAsEpLWeP7VAlTpMIcdW9owLyzEKQiDooGq9KCjrlEs6qpcKAjfgT7bXe2ASVeXyQ== X-OriginatorOrg: digi.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e0eb68a-2210-4781-4fbf-08d88c61836f X-MS-Exchange-CrossTenant-AuthSource: MN2PR10MB4174.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2020 08:02:52.3795 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: abb4cdb7-1b7e-483e-a143-7ebfd1184b9e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VbGYyVchib7TX8VJeVdleglD/o+dlJzzc6RghwLIgKHp2J+dT+++XUm37QhK/LzY5MVoAacY0AD7wgrRX/FZOQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR10MB4399 X-BESS-ID: 1605772974-893002-12923-54978-1 X-BESS-VER: 2019.1_20201118.2036 X-BESS-Apparent-Source-IP: 104.47.58.107 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.228292 [from cloudscan12-147.us-east-2a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 MSGID_FROM_MTA_HEADER META: Message-Id was added by a relay X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS112744 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND, MSGID_FROM_MTA_HEADER X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add 5gbase-r PHY interface mode. Signed-off-by: Pavana Sharma --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index fdf709817218..aa6ae7851de9 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -89,6 +89,8 @@ properties: - trgmii - 1000base-x - 2500base-x + # 5GBASE-R + - 5gbase-r - rxaui - xaui From patchwork Thu Nov 19 08:03:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavana Sharma X-Patchwork-Id: 11916669 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF5CEC56201 for ; Thu, 19 Nov 2020 08:03:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 574202065E for ; Thu, 19 Nov 2020 08:03:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=digi.com header.i=@digi.com header.b="avCl3tda" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726235AbgKSIDg (ORCPT ); Thu, 19 Nov 2020 03:03:36 -0500 Received: from outbound-ip24b.ess.barracuda.com ([209.222.82.221]:49134 "EHLO outbound-ip24b.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725816AbgKSIDf (ORCPT ); Thu, 19 Nov 2020 03:03:35 -0500 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10lp2107.outbound.protection.outlook.com [104.47.58.107]) by mx4.us-east-2b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 19 Nov 2020 08:03:23 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PQd1wbka2ZzlT+GS7cll8kRXTVIlc9EMTAx+0eyo/glm8cMvcLIkFZuTi7pILrUmvbfP0c18vRegHHHCnBQ2mYz9bFFYSpUiBCyxVs0xKkF/YDbBpBfR7BkyJcCYKXBFnRqHj6LCeq4MqhjLKq95sS7atz+proh96eYGJu4FgZalJiuaRMhMJpwqiQvpSIagwzSh/m12Aw82wZswh76qRaIOHWNOLeL3lO3UsE8FzDhUg2XuZ2kOge9fMRdQXuuVoNpyL/Nv7IZ6/Ur20NOUx1Pdq5Nbd4kDhm69aTz5Na5esN1f8M/tFgZ5x6o8dP3wmpTStAJC9EME396MxBACPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wzhu3HKrBF9WL7Cqr05yTjxR+KiotXQXs5GjHw4rN/g=; b=Wz5WPl4PqnIKKvUX+wZryQEguFQpqPbBN0lWy2UFwgNfF1RJMcL0VT7H+sZueGe+7IaCsMEBYoJt0lPns+afBUTrwuJyrUzpCV+gQ+XcYgVD/2pvzDchhsHgECY8LhdXQ/iy0fdEfZsQefMMbtyNKPf3X51mOeEJ1IUPzplz1yvDQPGA8dYXjbT5kKp2rYi5LxKCkSlGrc9pb/fl/0rtceiZUFiQ8ACYpxepMFZlLPNQJmCtl8nJ+oKqWtqh2hGI3IAJw+UbLW4FPUNfyS6ptqhJ79cj37gfAoCz6/PbHdSS7Oxo7mgK0pR9jV23pecLIGZiqFtGs9OzaFOHmbNFQQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=digi.com; dmarc=pass action=none header.from=digi.com; dkim=pass header.d=digi.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digi.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wzhu3HKrBF9WL7Cqr05yTjxR+KiotXQXs5GjHw4rN/g=; b=avCl3tdaoSs4qaQ0KRiGb9KJ1MYJqcQBrpVvPXAn82cwW+NAMX5jnd5DqnCQSLlNg9dzeG8H1Z0oDiTr36zJI9sY19Ee3iI27uLNxmze1OlEHWPqf2wDIMHiwmE0bVvJb4lcbiyQLXCfrpWpb1Ymwz/JKk9Ia+YoYZUhDKx7DV4= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=digi.com; Received: from MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) by MN2PR10MB4399.namprd10.prod.outlook.com (2603:10b6:208:1d9::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20; Thu, 19 Nov 2020 08:03:22 +0000 Received: from MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32]) by MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32%9]) with mapi id 15.20.3564.028; Thu, 19 Nov 2020 08:03:22 +0000 From: Pavana Sharma To: kuba@kernel.org Cc: andrew@lunn.ch, ashkan.boldaji@digi.com, davem@davemloft.net, f.fainelli@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, marek.behun@nic.cz, netdev@vger.kernel.org, pavana.sharma@digi.com, vivien.didelot@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 2/4] net: phy: Add 5GBASER interface mode Date: Thu, 19 Nov 2020 18:03:01 +1000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [14.200.39.236] X-ClientProxiedBy: SYBPR01CA0121.ausprd01.prod.outlook.com (2603:10c6:10:5::13) To MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (14.200.39.236) by SYBPR01CA0121.ausprd01.prod.outlook.com (2603:10c6:10:5::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20 via Frontend Transport; Thu, 19 Nov 2020 08:03:17 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d1140df2-8a64-4590-0780-08d88c61955f X-MS-TrafficTypeDiagnostic: MN2PR10MB4399: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:296; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hCX9/P2NcUEFaS26U5333IhzOuDHhpX3H2R0hrWFhon0no3DP85UNTQ/RAro2mPMr3Tcdi0PthsS3TcmiI7L+NyGBK94ArPp/88yMB44Q3fd9tMl/Tf1qcWAD51ZkIKaGtWSDbRWRy4kSQlWj0PsfWthHSANCZQUh9jQQ8r11jeE3E4UE2nXlRQ3Jz3l6Upil56x6J2Pz8zglKxO6XjD8OXH0I9Nbfqt8Xb01wzBYZEK97GJiffTowxZj/iO6Mt/0IIfb5kPvM6VBVixMPBO3kAraKRpLVghXsmLCt69KY0Vnnqgr3p+FbRnLEIckUFOyVgO/rdmsKk2qSTfxy9oXTJAKAMDXNu8ZfO428DJMx2vMCP2XocerbaklaYdJ4ak X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR10MB4174.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(346002)(376002)(366004)(136003)(396003)(39850400004)(7416002)(6486002)(956004)(8676002)(44832011)(26005)(86362001)(6506007)(8936002)(6512007)(6916009)(36756003)(52116002)(478600001)(16526019)(66476007)(66556008)(2906002)(316002)(5660300002)(2616005)(186003)(4326008)(6666004)(69590400008)(66946007);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: FGhJ3ij9rbRwNMmT2hghY9R3dIPbHnqYS9TZLkiUhCwIC9eUmL+vMgQl3YuBVHNELwgxWJD5mmuzaOY/DNyi/dSSYXUQsUoHA/edPm34v6XlHmcKRtgwCZRtnm6TbBtLa2jfb+r32slZqEWnkvK4qAHsxeD7kGI0I5LHN+LfrkC6A/+mEHuNXujVx2bI7RPVzzmUPn578frr9buJ3y17h6BcxTo+p9lJ33z0HvsoHz5ZyDOBMmZKttQE/b/vR7TAUQ2woVdpDbUFjNGAca8v5CSSFPZSXlGjTcbSxxHKG1ESCKr85KadBWaMyYwlXUb2p64O88SqQA2tnvA459ErTEBOkSxjLKIV0B56827vTHL8SbZxKOCUUqb1qwCxp+jG+djy0zrcnZskcf3HYb8hXrPzJVlyQHN0EtDDNiL75JB81Ny8anKFcRg59j9Kw7E5PrDpG6+8eygY4RJmY0vSAxh2ASIBngH0syyrPg2GOC6fqEe/YtsIc/isZTWgbt5R72pgAJRByLcoEIaHE9l0ygdEC4Wrv4UrPHpjzUKrwUe+zYDNR9ZW0E9fcY7qZ8pX/70p7HZyCJJXOnJlePNyxDqnBKg4zKbKcGElH3fnXGEWLUe1l3dHn7MX5Gmvqn+TCPF8OCHPBT+LnAbHgJY3OZqW7ZhbBOVGtDBTKv7BglRxWFzcXowqKanvK/sVGfWeGy2vEZgkzVQRiHgzs89A4qUQQ50Hc5Hcmcg516p8DyR9kYNZsQYF/X7TSVaXpaOFBQ4d+sPpoR1dKS9sH0P5KUpEOIrGIr+s/aoppCmKg5cw0mQ5/aQFeq1LvhtA9Efg7OhgxSfIGIWBhcdBTBGGjHSpsegYnJ0+l7VY7BwTJuW7/fUV3r2iGX7zlunD6CtLTj62i5/qo7v9phZUwJPC6Q== X-OriginatorOrg: digi.com X-MS-Exchange-CrossTenant-Network-Message-Id: d1140df2-8a64-4590-0780-08d88c61955f X-MS-Exchange-CrossTenant-AuthSource: MN2PR10MB4174.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2020 08:03:22.3622 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: abb4cdb7-1b7e-483e-a143-7ebfd1184b9e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: t+Y2n+V8W6+0M0prm8Wvz/jHHkxxN/jjUQTkevKnMhk/tAZ0o+LZMb2Ho4DBzbsEbYywmt13cvsJem84mBqv7Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR10MB4399 X-BESS-ID: 1605773003-893007-810-54468-1 X-BESS-VER: 2019.1_20201118.2036 X-BESS-Apparent-Source-IP: 104.47.58.107 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.228292 [from cloudscan10-124.us-east-2a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 MSGID_FROM_MTA_HEADER META: Message-Id was added by a relay 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS112744 scores of KILL_LEVEL=7.0 tests=MSGID_FROM_MTA_HEADER, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add 5GBASE-R phy interface mode Signed-off-by: Pavana Sharma --- include/linux/phy.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/phy.h b/include/linux/phy.h index eb3cb1a98b45..71e280059ec5 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -106,6 +106,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX + * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR @@ -137,6 +138,8 @@ typedef enum { PHY_INTERFACE_MODE_TRGMII, PHY_INTERFACE_MODE_1000BASEX, PHY_INTERFACE_MODE_2500BASEX, + /* 5GBASE-R mode */ + PHY_INTERFACE_MODE_5GBASER, PHY_INTERFACE_MODE_RXAUI, PHY_INTERFACE_MODE_XAUI, /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ @@ -215,6 +218,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "1000base-x"; case PHY_INTERFACE_MODE_2500BASEX: return "2500base-x"; + case PHY_INTERFACE_MODE_5GBASER: + return "5gbase-r"; case PHY_INTERFACE_MODE_RXAUI: return "rxaui"; case PHY_INTERFACE_MODE_XAUI: From patchwork Thu Nov 19 08:03:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavana Sharma X-Patchwork-Id: 11916671 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A210C6379D for ; Thu, 19 Nov 2020 08:04:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 373F82223F for ; Thu, 19 Nov 2020 08:04:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=digi.com header.i=@digi.com header.b="x1QaDp1N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726541AbgKSIEX (ORCPT ); Thu, 19 Nov 2020 03:04:23 -0500 Received: from outbound-ip23b.ess.barracuda.com ([209.222.82.220]:49074 "EHLO outbound-ip23b.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726358AbgKSIEW (ORCPT ); Thu, 19 Nov 2020 03:04:22 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11lp2172.outbound.protection.outlook.com [104.47.56.172]) by mx5.us-east-2b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 19 Nov 2020 08:04:10 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=U8fgjC6jvG+t0vI1iChkcDQxjeJGbQW4n3uqisWBv9lhGa4EqayNiIGEOgYm0pT5srlsIF7RM0D0P6K0nm/ZC7su7+IkFZvfqRLl3Mld/cwE1BfVHDUMHxxNbeJIjXJthtjWqSgrj3HyuAcpiieGTyye+w9Xfops5ovh3/OSwTJiqIRJghVSMZYrNFRXg4/L/ULQ16A5epaNSDeoEZdTPfFebhilZ32lBm2FBrDsbtt446XQ0ef1hB104g6euI5m67iHQD63Qa9OOAKUgH0ezuWFs4721cDj0VlDTc29jWdAJPn2eFHTpr0WlduuPq89WVbp/FOZ+0z22IsugYjMHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WI8ma3aeR6JhCXnuT9FkcLM1t1v5D6W2G+KNh9ZQn5M=; b=W2LiSwqYDRtvK4oHUh8Ja8s1URmrEiDWljq9mCAxCVBLY96eu0E++FpTiG9sGIhnFSRlUXtOBAFKHJRm2HDKBNNeZeUXJ0FWlznBITuwAwmPbJ7B560xMR/KzJ5PJjaXbXBmuj2mZ/IJXY9zGcKUnWm1p9NVILtmOfJGnMX8lPBAtTxVJ6RJcn1VOmrver7O9SAP8BVB6Z51+fWO/G+TQO1TEbAt3FEeA6dDUOiDGC/JZXjTuTgffv3v4EyW9EYZaTsbbXYnpcbH8WF8jb9vUdK3zxnY6ebmeBryBu2PRIwWeNN4ADHgr9ZwEy4/Uk8D5RkOCDxi58qrmry1SLoXmQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=digi.com; dmarc=pass action=none header.from=digi.com; dkim=pass header.d=digi.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digi.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WI8ma3aeR6JhCXnuT9FkcLM1t1v5D6W2G+KNh9ZQn5M=; b=x1QaDp1N+nxQl7qAM3HBLVPFbfyfG7qbcmI4ZtvjrbmRdK026E5dOV7VIjIquuiWkNLPHDtIbMyQnfF/DlSXSjgDqAymT17MMY6BR1zLr8qm55fAuk1L8m/9T9Rs2bEM3xjn89PhY9UyHOQzR1/NruwKi52Z1yzOFu86yETnXMM= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=digi.com; Received: from MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) by MN2PR10MB4399.namprd10.prod.outlook.com (2603:10b6:208:1d9::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20; Thu, 19 Nov 2020 08:04:09 +0000 Received: from MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32]) by MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32%9]) with mapi id 15.20.3564.028; Thu, 19 Nov 2020 08:04:09 +0000 From: Pavana Sharma To: kuba@kernel.org Cc: andrew@lunn.ch, ashkan.boldaji@digi.com, davem@davemloft.net, f.fainelli@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, marek.behun@nic.cz, netdev@vger.kernel.org, pavana.sharma@digi.com, vivien.didelot@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Date: Thu, 19 Nov 2020 18:03:46 +1000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [14.200.39.236] X-ClientProxiedBy: SYXPR01CA0141.ausprd01.prod.outlook.com (2603:10c6:0:30::26) To MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (14.200.39.236) by SYXPR01CA0141.ausprd01.prod.outlook.com (2603:10c6:0:30::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20 via Frontend Transport; Thu, 19 Nov 2020 08:04:04 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a90a3a2e-9dc4-4d23-598d-08d88c61b153 X-MS-TrafficTypeDiagnostic: MN2PR10MB4399: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OtIcTvd+Hc2oISZ5BCapc94wHgyj7BTlb04b3/5Gpfp7Akgt4NGYoYdXAFduyhJALyYO5WxqzG4s7C6XLrl2InMsOPvk8fi8r6Wvc6wgxOnQbHq1PUV16ZK7k+6BbwNkd3DlHGHNB2Zu8jAmzYrXl7wPMuCx1OfGjS23GSWYSjbv2lYaCUi/Z9qZgq+EZc1MCaXcacFehYXxbG1GoSlAg/xgVbzfvG8+7XETMpt6TvTbg05YFu4zrCltslEHVPeM7RczVq6UXloPav7+frwi8xYfCUozw1zoitPO3P5S7R2K3gGk8QBEyT2zIBY7ohFs/Sp3b+TD+cXXQurD21Cfs77XDNCMNVHRzoHpAKjJgd307Hab/NoOUcHZZ87Qj94u X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR10MB4174.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(346002)(376002)(366004)(136003)(396003)(39850400004)(7416002)(6486002)(956004)(8676002)(44832011)(26005)(86362001)(6506007)(8936002)(6512007)(6916009)(36756003)(52116002)(478600001)(83380400001)(16526019)(66476007)(66556008)(2906002)(316002)(5660300002)(2616005)(186003)(4326008)(6666004)(30864003)(69590400008)(66946007);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: WZS3SV0x+qedLpvWxq2X1QnmH1TToO03jl+o/yN/u1fHoNUiHsfH7nSoZllg9pPk9FyYxoKpU/shUribnduLwbO1mw+gjDxTC5iw34NU2wscFx2fPqkpz/SQ6iaWn1NSfE/o9H2H5plyvs43wF1n/3es6Pm+uixKP/DezadDdYaPAIG4BmCsraL3gFcPspQoeuwSGW4MKmOkV+tIzSbzEw0t9UyKnFteqvSCRr/EwVXf3A32mVGn6EH2PIFlXN+EMWusbH+NgseYCrM0AWPzb1b8oBdu72IX45sj3GyVM7AMwXUlypws50vTgCQPdOdipu5XTtaii4+6NuiCzIiVZLfaQJwc5vKg8aDQppw9T73XlFCeSzvHaf+t1xCkD+NijM3hnzqsmbiu/rFxEk24/lUR37CHpromM1+tpuli85PRhDQ6bb0OzGyqhJsnV21A5hamIGtcs16ENl7AtUBQmp6yyvLkAUD973kC02zg6OHsvM5uj2RC00wlutf0z/nD2MxNraHzCljh0guyyJnqUKsS9pUq4e35O1nv5GpkRBwhVsFJqI4TC+Zt53teyAEmIZ2HsDQcIVdbaF4j3o6dQh20NUC417292ziqVX7PiufReed75/T+4fFRvDdYon72TUPfizqQHfDz9XhoHFFMAc21+HaDphFqo0x1NDbmri+TeTMANjfaCN16cUGoEbxA1pa/7j7rjKdbRxJx8CChx1s3Rd3zxRqIwQhElYYuZ1Eoe0mZ9Qi3t7AqsYc/qUg8Luch/NippnmlJXCIU56fVBgbfEkpPQHH1UeRPA8WPK5R65WIOXAg4jLRm9z8g46YXiSaroVLxrHDbmHbFvZoakXo8mNIIkjq4iH015gdl+rzlg3V2KshPvUKxZQ/tWiB7GObTe0BZ3WMHDx+Z4ML9Q== X-OriginatorOrg: digi.com X-MS-Exchange-CrossTenant-Network-Message-Id: a90a3a2e-9dc4-4d23-598d-08d88c61b153 X-MS-Exchange-CrossTenant-AuthSource: MN2PR10MB4174.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2020 08:04:09.4551 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: abb4cdb7-1b7e-483e-a143-7ebfd1184b9e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: j0I2QVwfs1bmDAT+lm4gySiNElDfYjhzh4TC5p15iN8gvEhs8I6qZtr6orfy8wD1EroUquuBBaasItiU+/8TRg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR10MB4399 X-BESS-ID: 1605773050-893009-20157-54589-1 X-BESS-VER: 2019.1_20201118.2036 X-BESS-Apparent-Source-IP: 104.47.56.172 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.228292 [from cloudscan9-45.us-east-2a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 MSGID_FROM_MTA_HEADER META: Message-Id was added by a relay 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS112744 scores of KILL_LEVEL=7.0 tests=MSGID_FROM_MTA_HEADER, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Returning 0 is no more an error case with MV88E6393 family which has serdes lane numbers 0, 9 or 10. So with this change .serdes_get_lane will return lane number or -errno (-ENODEV or -EOPNOTSUPP). Signed-off-by: Pavana Sharma --- drivers/net/dsa/mv88e6xxx/chip.c | 28 ++++++------ drivers/net/dsa/mv88e6xxx/chip.h | 16 +++---- drivers/net/dsa/mv88e6xxx/port.c | 6 +-- drivers/net/dsa/mv88e6xxx/serdes.c | 72 +++++++++++++++--------------- drivers/net/dsa/mv88e6xxx/serdes.h | 54 +++++++++++----------- 5 files changed, 88 insertions(+), 88 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index bd297ae7cf9e..57b6ce785629 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -485,12 +485,12 @@ static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, struct phylink_link_state *state) { struct mv88e6xxx_chip *chip = ds->priv; - u8 lane; + int lane; int err; mv88e6xxx_reg_lock(chip); lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane && chip->info->ops->serdes_pcs_get_state) + if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, state); else @@ -506,11 +506,11 @@ static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, const unsigned long *advertise) { const struct mv88e6xxx_ops *ops = chip->info->ops; - u8 lane; + int lane; if (ops->serdes_pcs_config) { lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane) + if (lane >= 0) return ops->serdes_pcs_config(chip, port, lane, mode, interface, advertise); } @@ -523,14 +523,14 @@ static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) struct mv88e6xxx_chip *chip = ds->priv; const struct mv88e6xxx_ops *ops; int err = 0; - u8 lane; + int lane; ops = chip->info->ops; if (ops->serdes_pcs_an_restart) { mv88e6xxx_reg_lock(chip); lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane) + if (lane >= 0) err = ops->serdes_pcs_an_restart(chip, port, lane); mv88e6xxx_reg_unlock(chip); @@ -544,11 +544,11 @@ static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, int speed, int duplex) { const struct mv88e6xxx_ops *ops = chip->info->ops; - u8 lane; + int lane; if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane) + if (lane >= 0) return ops->serdes_pcs_link_up(chip, port, lane, speed, duplex); } @@ -2422,11 +2422,11 @@ static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) struct mv88e6xxx_chip *chip = mvp->chip; irqreturn_t ret = IRQ_NONE; int port = mvp->port; - u8 lane; + int lane; mv88e6xxx_reg_lock(chip); lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane) + if (lane >= 0) ret = mv88e6xxx_serdes_irq_status(chip, port, lane); mv88e6xxx_reg_unlock(chip); @@ -2434,7 +2434,7 @@ static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) } static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, - u8 lane) + int lane) { struct mv88e6xxx_port *dev_id = &chip->ports[port]; unsigned int irq; @@ -2463,7 +2463,7 @@ static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, } static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, - u8 lane) + int lane) { struct mv88e6xxx_port *dev_id = &chip->ports[port]; unsigned int irq = dev_id->serdes_irq; @@ -2488,11 +2488,11 @@ static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on) { - u8 lane; + int lane; int err; lane = mv88e6xxx_serdes_get_lane(chip, port); - if (!lane) + if (lane < 0) return 0; if (on) { diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 81c244fc0419..d81f586d67e8 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -506,30 +506,30 @@ struct mv88e6xxx_ops { int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); /* Power on/off a SERDES interface */ - int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, + int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, bool up); /* SERDES lane mapping */ - u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); + int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, - u8 lane, struct phylink_link_state *state); + int lane, struct phylink_link_state *state); int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, - u8 lane, unsigned int mode, + int lane, unsigned int mode, phy_interface_t interface, const unsigned long *advertise); int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, - u8 lane); + int lane); int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, - u8 lane, int speed, int duplex); + int lane, int speed, int duplex); /* SERDES interrupt handling */ unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, int port); - int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, + int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, bool enable); irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, - u8 lane); + int lane); /* Statistics from the SERDES interface */ int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 8128dc607cf4..89d4c16fbbb5 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -393,8 +393,8 @@ phy_interface_t mv88e6390x_port_max_speed_mode(int port) static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode, bool force) { - u8 lane; u16 cmode; + int lane; u16 reg; int err; @@ -430,7 +430,7 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, return 0; lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane) { + if (lane >= 0) { if (chip->ports[port].serdes_irq) { err = mv88e6xxx_serdes_irq_disable(chip, port, lane); if (err) @@ -459,7 +459,7 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, chip->ports[port].cmode = cmode; lane = mv88e6xxx_serdes_get_lane(chip, port); - if (!lane) + if (lane < 0) return -ENODEV; err = mv88e6xxx_serdes_power_up(chip, port, lane); diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c index 9c07b4f3d345..058cce01c01e 100644 --- a/drivers/net/dsa/mv88e6xxx/serdes.c +++ b/drivers/net/dsa/mv88e6xxx/serdes.c @@ -95,7 +95,7 @@ static int mv88e6xxx_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, return 0; } -int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, bool up) { u16 val, new_val; @@ -117,7 +117,7 @@ int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, } int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, - u8 lane, unsigned int mode, + int lane, unsigned int mode, phy_interface_t interface, const unsigned long *advertise) { @@ -166,7 +166,7 @@ int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, } int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, - u8 lane, struct phylink_link_state *state) + int lane, struct phylink_link_state *state) { u16 lpa, status; int err; @@ -187,7 +187,7 @@ int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, } int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, - u8 lane) + int lane) { u16 bmcr; int err; @@ -200,7 +200,7 @@ int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, } int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, - u8 lane, int speed, int duplex) + int lane, int speed, int duplex) { u16 val, bmcr; int err; @@ -230,10 +230,10 @@ int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, return mv88e6352_serdes_write(chip, MII_BMCR, bmcr); } -u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) +int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) { u8 cmode = chip->ports[port].cmode; - u8 lane = 0; + int lane = -ENODEV; if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASEX) || (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX) || @@ -245,7 +245,7 @@ u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port) { - if (mv88e6xxx_serdes_get_lane(chip, port)) + if (mv88e6xxx_serdes_get_lane(chip, port) >= 0) return true; return false; @@ -354,7 +354,7 @@ static void mv88e6352_serdes_irq_link(struct mv88e6xxx_chip *chip, int port) } irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, - u8 lane) + int lane) { irqreturn_t ret = IRQ_NONE; u16 status; @@ -372,7 +372,7 @@ irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, return ret; } -int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, bool enable) { u16 val = 0; @@ -411,10 +411,10 @@ void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p) } } -u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) +int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) { u8 cmode = chip->ports[port].cmode; - u8 lane = 0; + int lane = -ENODEV; switch (port) { case 5: @@ -428,10 +428,10 @@ u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) return lane; } -u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) +int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) { u8 cmode = chip->ports[port].cmode; - u8 lane = 0; + int lane = -ENODEV; switch (port) { case 9: @@ -451,12 +451,12 @@ u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) return lane; } -u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) +int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) { u8 cmode_port = chip->ports[port].cmode; u8 cmode_port10 = chip->ports[10].cmode; u8 cmode_port9 = chip->ports[9].cmode; - u8 lane = 0; + int lane = -ENODEV; switch (port) { case 2: @@ -527,7 +527,7 @@ u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) } /* Set power up/down for 10GBASE-R and 10GBASE-X4/X2 */ -static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, u8 lane, +static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, int lane, bool up) { u16 val, new_val; @@ -554,7 +554,7 @@ static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, u8 lane, } /* Set power up/down for SGMII and 1000Base-X */ -static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, u8 lane, +static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, int lane, bool up) { u16 val, new_val; @@ -590,7 +590,7 @@ static struct mv88e6390_serdes_hw_stat mv88e6390_serdes_hw_stats[] = { int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port) { - if (mv88e6390_serdes_get_lane(chip, port) == 0) + if (mv88e6390_serdes_get_lane(chip, port) < 0) return 0; return ARRAY_SIZE(mv88e6390_serdes_hw_stats); @@ -602,7 +602,7 @@ int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, struct mv88e6390_serdes_hw_stat *stat; int i; - if (mv88e6390_serdes_get_lane(chip, port) == 0) + if (mv88e6390_serdes_get_lane(chip, port) < 0) return 0; for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) { @@ -639,7 +639,7 @@ int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, int i; lane = mv88e6390_serdes_get_lane(chip, port); - if (lane == 0) + if (lane < 0) return 0; for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) { @@ -650,7 +650,7 @@ int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, return ARRAY_SIZE(mv88e6390_serdes_hw_stats); } -static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, u8 lane) +static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, int lane) { u16 reg; int err; @@ -665,7 +665,7 @@ static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, u8 lane) MV88E6390_PG_CONTROL, reg); } -int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, bool up) { u8 cmode = chip->ports[port].cmode; @@ -690,7 +690,7 @@ int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, } int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, - u8 lane, unsigned int mode, + int lane, unsigned int mode, phy_interface_t interface, const unsigned long *advertise) { @@ -749,7 +749,7 @@ int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, } static int mv88e6390_serdes_pcs_get_state_sgmii(struct mv88e6xxx_chip *chip, - int port, u8 lane, struct phylink_link_state *state) + int port, int lane, struct phylink_link_state *state) { u16 lpa, status; int err; @@ -772,7 +772,7 @@ static int mv88e6390_serdes_pcs_get_state_sgmii(struct mv88e6xxx_chip *chip, } static int mv88e6390_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip, - int port, u8 lane, struct phylink_link_state *state) + int port, int lane, struct phylink_link_state *state) { u16 status; int err; @@ -792,7 +792,7 @@ static int mv88e6390_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip, } int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, - u8 lane, struct phylink_link_state *state) + int lane, struct phylink_link_state *state) { switch (state->interface) { case PHY_INTERFACE_MODE_SGMII: @@ -811,7 +811,7 @@ int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, } int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, - u8 lane) + int lane) { u16 bmcr; int err; @@ -827,7 +827,7 @@ int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, } int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, - u8 lane, int speed, int duplex) + int lane, int speed, int duplex) { u16 val, bmcr; int err; @@ -861,7 +861,7 @@ int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, } static void mv88e6390_serdes_irq_link_sgmii(struct mv88e6xxx_chip *chip, - int port, u8 lane) + int port, int lane) { u16 bmsr; int err; @@ -878,7 +878,7 @@ static void mv88e6390_serdes_irq_link_sgmii(struct mv88e6xxx_chip *chip, } static int mv88e6390_serdes_irq_enable_sgmii(struct mv88e6xxx_chip *chip, - u8 lane, bool enable) + int lane, bool enable) { u16 val = 0; @@ -890,7 +890,7 @@ static int mv88e6390_serdes_irq_enable_sgmii(struct mv88e6xxx_chip *chip, MV88E6390_SGMII_INT_ENABLE, val); } -int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, bool enable) { u8 cmode = chip->ports[port].cmode; @@ -906,7 +906,7 @@ int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, } static int mv88e6390_serdes_irq_status_sgmii(struct mv88e6xxx_chip *chip, - u8 lane, u16 *status) + int lane, u16 *status) { int err; @@ -917,7 +917,7 @@ static int mv88e6390_serdes_irq_status_sgmii(struct mv88e6xxx_chip *chip, } irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, - u8 lane) + int lane) { u8 cmode = chip->ports[port].cmode; irqreturn_t ret = IRQ_NONE; @@ -976,7 +976,7 @@ static const u16 mv88e6390_serdes_regs[] = { int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port) { - if (mv88e6xxx_serdes_get_lane(chip, port) == 0) + if (mv88e6xxx_serdes_get_lane(chip, port) < 0) return 0; return ARRAY_SIZE(mv88e6390_serdes_regs) * sizeof(u16); @@ -990,7 +990,7 @@ void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p) int i; lane = mv88e6xxx_serdes_get_lane(chip, port); - if (lane == 0) + if (lane < 0) return; for (i = 0 ; i < ARRAY_SIZE(mv88e6390_serdes_regs); i++) { diff --git a/drivers/net/dsa/mv88e6xxx/serdes.h b/drivers/net/dsa/mv88e6xxx/serdes.h index 14315f26228a..ed3181e82da9 100644 --- a/drivers/net/dsa/mv88e6xxx/serdes.h +++ b/drivers/net/dsa/mv88e6xxx/serdes.h @@ -73,46 +73,46 @@ #define MV88E6390_PG_CONTROL 0xf010 #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0) -u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); -u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); -u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); -u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); +int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); +int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); +int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); +int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, - u8 lane, unsigned int mode, + int lane, unsigned int mode, phy_interface_t interface, const unsigned long *advertise); int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, - u8 lane, unsigned int mode, + int lane, unsigned int mode, phy_interface_t interface, const unsigned long *advertise); int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, - u8 lane, struct phylink_link_state *state); + int lane, struct phylink_link_state *state); int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, - u8 lane, struct phylink_link_state *state); + int lane, struct phylink_link_state *state); int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, - u8 lane); + int lane); int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, - u8 lane); + int lane); int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, - u8 lane, int speed, int duplex); + int lane, int speed, int duplex); int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, - u8 lane, int speed, int duplex); + int lane, int speed, int duplex); unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port); unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port); -int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, bool on); -int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, bool on); -int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, bool enable); -int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, +int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, bool enable); irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, - u8 lane); + int lane); irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, - u8 lane); + int lane); int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, int port, uint8_t *data); @@ -129,18 +129,18 @@ void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); -/* Return the (first) SERDES lane address a port is using, 0 otherwise. */ -static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip, - int port) +/* Return the (first) SERDES lane address a port is using, -errno otherwise. */ +static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip, + int port) { if (!chip->info->ops->serdes_get_lane) - return 0; + return -EOPNOTSUPP; return chip->info->ops->serdes_get_lane(chip, port); } static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip, - int port, u8 lane) + int port, int lane) { if (!chip->info->ops->serdes_power) return -EOPNOTSUPP; @@ -149,7 +149,7 @@ static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip, } static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip, - int port, u8 lane) + int port, int lane) { if (!chip->info->ops->serdes_power) return -EOPNOTSUPP; @@ -167,7 +167,7 @@ mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) } static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip, - int port, u8 lane) + int port, int lane) { if (!chip->info->ops->serdes_irq_enable) return -EOPNOTSUPP; @@ -176,7 +176,7 @@ static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip, } static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip, - int port, u8 lane) + int port, int lane) { if (!chip->info->ops->serdes_irq_enable) return -EOPNOTSUPP; @@ -185,7 +185,7 @@ static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip, } static inline irqreturn_t -mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane) +mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane) { if (!chip->info->ops->serdes_irq_status) return IRQ_NONE; From patchwork Thu Nov 19 08:04:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavana Sharma X-Patchwork-Id: 11916673 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31191C56201 for ; Thu, 19 Nov 2020 08:05:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BA35B246D1 for ; Thu, 19 Nov 2020 08:05:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=digi.com header.i=@digi.com header.b="h69g/PyN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726557AbgKSIFC (ORCPT ); Thu, 19 Nov 2020 03:05:02 -0500 Received: from outbound-ip24a.ess.barracuda.com ([209.222.82.206]:56708 "EHLO outbound-ip24a.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726182AbgKSIFB (ORCPT ); Thu, 19 Nov 2020 03:05:01 -0500 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10lp2104.outbound.protection.outlook.com [104.47.58.104]) by mx4.us-east-2a.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 19 Nov 2020 08:04:48 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=e/sntEtkqMP5Ck3e+nGZcJHwLC3SIYSeZWjdbIKH6Dkcnv79MbwCcUfjy46w2bQ1kx4pC2kMu3dxwtmRyJxFR+Oj/M1H/7LBwEmYYrFTGzrmtqDA1IGbkF1GS3DsTmqSCyHZLwEZU2RuCaEFG7+ioqHsC4nAHrV8A7p248rXOlyArx0UAJ4pc4Apx5Vqur2/wXnb6Sdv0MzeVy6x5gsg8fGs0vSWkCLidiWx3noUj8peOzygTE0+yVElr7SGEPuOnkPMobWlblL68DI6NRYkgQHZcfyCm2XCCFlQOYAvR2Tes7ZV1FjoAI4UFb7NQk/M/Kpa5J1bbEAQp6/fV4vR9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jkx7s3RpzYLOaKmYLH1V0y5vru0chCfaYkVRGuQQWAA=; b=dtxvfbZ0+pM/5WfEXux9V7sd6ND5avpFUVodESDf9f+QmICZHE3Jvyk2ele6vuw3bsMSYIcGNwbbBT8fYxnxNBHdgZzCo3SOpxlMOuHgMmUtU1D1tICVKlUSe50ncY/IrS0/77alZqYl/N506fWDYPwfPRgZohpO8DXA+Blw0sN0u8hYGczLov2WO/xUQmI/nO3Qx0uveV1gbt9fHZLkHeH9i8NazZXQ0BYkU//YEpXvj9UYzwBNmh/dCrTLT8TCSyS+/oC0/j28Iw/AzGAUOP7dtBfUMxlgSx79Qv7rzYDe/eg9r/ZzXSoufVDUITIOXOF/ta3pUU30PDmoGuZ+tA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=digi.com; dmarc=pass action=none header.from=digi.com; dkim=pass header.d=digi.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digi.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jkx7s3RpzYLOaKmYLH1V0y5vru0chCfaYkVRGuQQWAA=; b=h69g/PyNXxaSIpxtWBkvxWzA6TamNToYxaEEZ7a7bklt9AKAlshgvYro0zJkeg4U/RNUXGsLAX8BMlOpqYCAsUi0FaTNeXH4LHlVIK6WOYIF3Ov/rLZnpUT5RDBwQEVgUZNvVeFJxrQr/exHOm29nuFHJWtzCKSbvjag7lOHgyg= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=digi.com; Received: from MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) by MN2PR10MB4399.namprd10.prod.outlook.com (2603:10b6:208:1d9::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20; Thu, 19 Nov 2020 08:04:47 +0000 Received: from MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32]) by MN2PR10MB4174.namprd10.prod.outlook.com ([fe80::b505:75ae:58c9:eb32%9]) with mapi id 15.20.3564.028; Thu, 19 Nov 2020 08:04:47 +0000 From: Pavana Sharma To: kuba@kernel.org Cc: andrew@lunn.ch, ashkan.boldaji@digi.com, davem@davemloft.net, f.fainelli@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, marek.behun@nic.cz, netdev@vger.kernel.org, pavana.sharma@digi.com, vivien.didelot@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Date: Thu, 19 Nov 2020 18:04:21 +1000 Message-Id: <692ff1bbf56575093019faeed7fda33ef57ebf7c.1605684865.git.pavana.sharma@digi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-Originating-IP: [14.200.39.236] X-ClientProxiedBy: SYAPR01CA0021.ausprd01.prod.outlook.com (2603:10c6:1::33) To MN2PR10MB4174.namprd10.prod.outlook.com (2603:10b6:208:1dd::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (14.200.39.236) by SYAPR01CA0021.ausprd01.prod.outlook.com (2603:10c6:1::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20 via Frontend Transport; Thu, 19 Nov 2020 08:04:42 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 55354322-613c-4cf2-6081-08d88c61c7be X-MS-TrafficTypeDiagnostic: MN2PR10MB4399: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2276; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rsM3sqH0MDgXY/HI/7u1Fl938MGqJ8tj0rBbxfHncZlQ3Xad4NU7Wbsy7L3NJcjbrBdNbXWngJk//YKzmxX3jHFd/jKC6Rval76/6AakSgQEZpFj4kHfpyro3M/mByfEM8Zilck0ScLMX1eigoGe2PBVenls/WNaPk2QXVWZ67MUki+b6+D7xyqi2uDEaU8jktyPUqwzzK9WvyukyskArGNGiaSjmd6kIwxQgnHRMsnf49Kh+Vp7z0XA4ITP+MgFcg5LOd902LaiCVQ+DKGAxfDSebxVqF/qdsZ0RJMifG98rZtWMgsUSA8NVq48yLSE0CSWje5U5ie2HKAoz75TexRx86Zi3UA1wE/Tq7uT5O52B4/6rIzJNPkT6GYiCHeu X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR10MB4174.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(346002)(376002)(366004)(136003)(396003)(39850400004)(7416002)(6486002)(956004)(8676002)(44832011)(26005)(86362001)(6506007)(8936002)(6512007)(6916009)(36756003)(52116002)(478600001)(83380400001)(16526019)(66476007)(66556008)(2906002)(316002)(5660300002)(2616005)(186003)(4326008)(6666004)(30864003)(69590400008)(66946007);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: nXI6bSF9gYaeqbqb6jYRgU1Bg6RrV1/6cIKg5I0vBzdTjHNPVLp9dSQQEc7JW9RZixUXb8KFRZuNzr2fkFAeixi3sXMXh+w7tYCIfhMM+c7bHBrnIP4+3Pk6E9zovlA95CTBBiBSu9mcsLaBe7lxW/PbWaQv/Z7djuSPdcYr1M8UNViA0RRs4TZj2TkBWqm4jXvu/s6HHezzoS0Rx9+QjH25lgP6eHwanYYFO/uFtpGC9wxnhotgj98TLBgcrAkRzMte0O8TUk+y84OdkWAuyWEAB4L3x+o7yZqAo8skl7rDprkfWsOhM+Y4DYXxfhixmgC1QSjrmx2A3t/7yVJsaHsVhBfo0/6NkgnvnDNi8kTPXwxFkn1QB2LhLp4puqWr6r0C0Zhc+eAPy9j7Jg36PtTmGZ7mHFN0Khc7f59z5Px9J9VTuEvAhDkk9j3Qqjt53PKFnhjYtnfDRgPVVLm5nU0jKe+4ssE+cL0p9FSsonobKONE3C9T+E/5sJ+QmMCm868nsCUNhrt+qyQKaQKd0UqtDOTOlY9YN7UPg+G1QJRgpZmnkiquTZiRT9MCWwgoqYgMh+DjwpC4+2tcRIrL2XHSSREFRzo3y3bH3CesiLwyIgCHpDm8wQgYlcnHpBn+pCc3NbNJouCsIgqtScTrBTBkseUNTtDhb+PlhUveaDSsnNBe1xocBfFExZTDIsJryd1GlWjAMezHq61gtK5qpujzIBSQYqaVAQDUVfQaESmK4R9ZxgBBj6c15e7+QMNRtYz5+gmxFYwX1DAtCUKu/p/KAAgvI07gUDUY/wZ1lIYUzhXU664YoGcbxHX+Q3UAFU2XV0BpdkEuq0kWcwQjF7ZZBIJcg8DrSKaDpZpGm+Ov3upxp0yQHWKTXgM+bmXJPNR+DCkDmxIqwON3gPrKsg== X-OriginatorOrg: digi.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55354322-613c-4cf2-6081-08d88c61c7be X-MS-Exchange-CrossTenant-AuthSource: MN2PR10MB4174.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2020 08:04:47.1968 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: abb4cdb7-1b7e-483e-a143-7ebfd1184b9e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zwXnmwkv9JSW17WEf26xC2pbGQlzKA/BcX2ke95lrTmwfDfBw5gckqZhg1CaDluOjeOS16+DTU2GmvV5F9VwtA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR10MB4399 X-BESS-ID: 1605773088-893006-22987-54421-1 X-BESS-VER: 2019.1_20201118.2036 X-BESS-Apparent-Source-IP: 104.47.58.104 X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.228292 [from cloudscan12-147.us-east-2a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 MSGID_FROM_MTA_HEADER META: Message-Id was added by a relay 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS112744 scores of KILL_LEVEL=7.0 tests=MSGID_FROM_MTA_HEADER, BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The Marvell 88E6393X device is a single-chip integration of a 11-port Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers and three 10-Gigabit interfaces. This patch adds functionalities specific to mv88e6393x family (88E6393X, 88E6193X and 88E6191X) Co-developed-by: Ashkan Boldaji Signed-off-by: Ashkan Boldaji Signed-off-by: Pavana Sharma Reported-by: kernel test robot Reported-by: kernel test robot --- Changes in v2: - Fix a warning (Reported-by: kernel test robot ) Changes in v3: - Fix 'unused function' warning Changes in v4-v9: - Incorporated feedback from maintainers. --- drivers/net/dsa/mv88e6xxx/chip.c | 136 ++++++++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 4 + drivers/net/dsa/mv88e6xxx/global1.h | 2 + drivers/net/dsa/mv88e6xxx/global2.h | 8 + drivers/net/dsa/mv88e6xxx/port.c | 234 +++++++++++++++++++++++++++- drivers/net/dsa/mv88e6xxx/port.h | 43 ++++- drivers/net/dsa/mv88e6xxx/serdes.c | 224 ++++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/serdes.h | 39 +++++ 8 files changed, 686 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 57b6ce785629..4bde9754ea8a 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -635,6 +635,24 @@ static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, mv88e6390_phylink_validate(chip, port, mask, state); } +static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, + unsigned long *mask, + struct phylink_link_state *state) +{ + if (port == 0 || port == 9 || port == 10) { + phylink_set(mask, 10000baseT_Full); + phylink_set(mask, 10000baseKR_Full); + phylink_set(mask, 5000baseT_Full); + phylink_set(mask, 2500baseX_Full); + phylink_set(mask, 2500baseT_Full); + } + + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + + mv88e6065_phylink_validate(chip, port, mask, state); +} + static void mv88e6xxx_validate(struct dsa_switch *ds, int port, unsigned long *supported, struct phylink_link_state *state) @@ -3906,6 +3924,55 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { .phylink_validate = mv88e6390_phylink_validate, }; +static const struct mv88e6xxx_ops mv88e6393x_ops = { + /* MV88E6XXX_FAMILY_6393 */ + .setup_errata = mv88e6393x_setup_errata, + .irl_init_all = mv88e6390_g2_irl_init_all, + .get_eeprom = mv88e6xxx_g2_get_eeprom8, + .set_eeprom = mv88e6xxx_g2_set_eeprom8, + .set_switch_mac = mv88e6xxx_g2_set_switch_mac, + .phy_read = mv88e6xxx_g2_smi_phy_read, + .phy_write = mv88e6xxx_g2_smi_phy_write, + .port_set_link = mv88e6xxx_port_set_link, + .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, + .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, + .port_tag_remap = mv88e6390_port_tag_remap, + .port_set_frame_mode = mv88e6351_port_set_frame_mode, + .port_set_egress_floods = mv88e6352_port_set_egress_floods, + .port_set_ether_type = mv88e6393x_port_set_ether_type, + .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, + .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_pause_limit = mv88e6390_port_pause_limit, + .port_set_cmode = mv88e6393x_port_set_cmode, + .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, + .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, + .port_get_cmode = mv88e6352_port_get_cmode, + .stats_snapshot = mv88e6390_g1_stats_snapshot, + .stats_set_histogram = mv88e6390_g1_stats_set_histogram, + .stats_get_sset_count = mv88e6320_stats_get_sset_count, + .stats_get_strings = mv88e6320_stats_get_strings, + .stats_get_stats = mv88e6390_stats_get_stats, + .set_cpu_port = mv88e6393x_port_set_cpu_dest, + .set_egress_port = mv88e6393x_set_egress_port, + .watchdog_ops = &mv88e6390_watchdog_ops, + .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, + .pot_clear = mv88e6xxx_g2_pot_clear, + .reset = mv88e6352_g1_reset, + .rmu_disable = mv88e6390_g1_rmu_disable, + .vtu_getnext = mv88e6390_g1_vtu_getnext, + .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, + .serdes_power = mv88e6393x_serdes_power, + .serdes_get_lane = mv88e6393x_serdes_get_lane, + .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, + .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, + .serdes_irq_enable = mv88e6393x_serdes_irq_enable, + .serdes_irq_status = mv88e6393x_serdes_irq_status, + .gpio_ops = &mv88e6352_gpio_ops, + .avb_ops = &mv88e6390_avb_ops, + .ptp_ops = &mv88e6352_ptp_ops, + .phylink_validate = mv88e6393x_phylink_validate, +}; + static const struct mv88e6xxx_ops mv88e6240_ops = { /* MV88E6XXX_FAMILY_6352 */ .ieee_pri_map = mv88e6085_g1_ieee_pri_map, @@ -4838,6 +4905,52 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .ops = &mv88e6191_ops, }, + [MV88E6191X] = { + .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, + .family = MV88E6XXX_FAMILY_6393, + .name = "Marvell 88E6191X", + .num_databases = 4096, + .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 9, + .max_vid = 8191, + .port_base_addr = 0x0, + .phy_base_addr = 0x0, + .global1_addr = 0x1b, + .global2_addr = 0x1c, + .age_time_coeff = 3750, + .g1_irqs = 10, + .g2_irqs = 14, + .atu_move_port_mask = 0x1f, + .pvt = true, + .multi_chip = true, + .tag_protocol = DSA_TAG_PROTO_DSA, + .ptp_support = true, + .ops = &mv88e6393x_ops, + }, + + [MV88E6193X] = { + .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, + .family = MV88E6XXX_FAMILY_6393, + .name = "Marvell 88E6193X", + .num_databases = 4096, + .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 9, + .max_vid = 8191, + .port_base_addr = 0x0, + .phy_base_addr = 0x0, + .global1_addr = 0x1b, + .global2_addr = 0x1c, + .age_time_coeff = 3750, + .g1_irqs = 10, + .g2_irqs = 14, + .atu_move_port_mask = 0x1f, + .pvt = true, + .multi_chip = true, + .tag_protocol = DSA_TAG_PROTO_DSA, + .ptp_support = true, + .ops = &mv88e6393x_ops, + }, + [MV88E6220] = { .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, .family = MV88E6XXX_FAMILY_6250, @@ -5128,6 +5241,29 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { .ptp_support = true, .ops = &mv88e6390x_ops, }, + + [MV88E6393X] = { + .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, + .family = MV88E6XXX_FAMILY_6393, + .name = "Marvell 88E6393X", + .num_databases = 4096, + .num_ports = 11, /* 10 + Z80 */ + .num_internal_phys = 9, + .max_vid = 8191, + .port_base_addr = 0x0, + .phy_base_addr = 0x0, + .global1_addr = 0x1b, + .global2_addr = 0x1c, + .age_time_coeff = 3750, + .g1_irqs = 10, + .g2_irqs = 14, + .atu_move_port_mask = 0x1f, + .pvt = true, + .multi_chip = true, + .tag_protocol = DSA_TAG_PROTO_DSA, + .ptp_support = true, + .ops = &mv88e6393x_ops, + }, }; static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index d81f586d67e8..2264394633c0 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -63,6 +63,8 @@ enum mv88e6xxx_model { MV88E6190, MV88E6190X, MV88E6191, + MV88E6191X, + MV88E6193X, MV88E6220, MV88E6240, MV88E6250, @@ -75,6 +77,7 @@ enum mv88e6xxx_model { MV88E6352, MV88E6390, MV88E6390X, + MV88E6393X, }; enum mv88e6xxx_family { @@ -90,6 +93,7 @@ enum mv88e6xxx_family { MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ + MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */ }; struct mv88e6xxx_ops; diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h index 1e3546f8b072..6d6c59d594a0 100644 --- a/drivers/net/dsa/mv88e6xxx/global1.h +++ b/drivers/net/dsa/mv88e6xxx/global1.h @@ -22,6 +22,7 @@ #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 #define MV88E6XXX_G1_STS_INIT_READY 0x0800 +#define MV88E6393X_G1_STS_IRQ_DEVICE_2 9 #define MV88E6XXX_G1_STS_IRQ_AVB 8 #define MV88E6XXX_G1_STS_IRQ_DEVICE 7 #define MV88E6XXX_G1_STS_IRQ_STATS 6 @@ -59,6 +60,7 @@ #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800 #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400 #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200 +#define MV88E6393X_G1_CTL1_DEVICE2_EN 0x0200 #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020 diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h index 1f42ee656816..04696cb68971 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.h +++ b/drivers/net/dsa/mv88e6xxx/global2.h @@ -38,9 +38,15 @@ /* Offset 0x02: MGMT Enable Register 2x */ #define MV88E6XXX_G2_MGMT_EN_2X 0x02 +/* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */ +#define MV88E6393X_G2_MACLINK_INT_SRC 0x02 + /* Offset 0x03: MGMT Enable Register 0x */ #define MV88E6XXX_G2_MGMT_EN_0X 0x03 +/* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */ +#define MV88E6393X_G2_MACLINK_INT_MASK 0x03 + /* Offset 0x04: Flow Control Delay Register */ #define MV88E6XXX_G2_FLOW_CTL 0x04 @@ -52,6 +58,8 @@ #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 +#define MV88E6393X_G2_EGRESS_MONITOR_DEST 0x05 + /* Offset 0x06: Device Mapping Table Register */ #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 89d4c16fbbb5..e3737246ba57 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -14,6 +14,7 @@ #include #include "chip.h" +#include "global2.h" #include "port.h" #include "serdes.h" @@ -25,6 +26,14 @@ int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, return mv88e6xxx_read(chip, addr, reg, val); } +int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, + int bit, int val) +{ + int addr = chip->info->port_base_addr + port; + + return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); +} + int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, u16 val) { @@ -222,8 +231,8 @@ static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, return err; reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | - MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | - MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); + MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | + MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); if (alt_bit) reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; @@ -390,6 +399,84 @@ phy_interface_t mv88e6390x_port_max_speed_mode(int port) return PHY_INTERFACE_MODE_NA; } +/* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) */ +int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, + int speed, int duplex) +{ + u16 reg, ctrl; + int err; + + if (speed == SPEED_MAX) + speed = (port > 0 && port < 9) ? 1000 : 10000; + + if (speed == 200 && port != 0) + return -EOPNOTSUPP; + + if (speed >= 2500 && port > 0 && port < 9) + return -EOPNOTSUPP; + + switch (speed) { + case 10: + ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; + break; + case 100: + ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; + break; + case 200: + ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | + MV88E6390_PORT_MAC_CTL_ALTSPEED; + break; + case 1000: + ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; + break; + case 2500: + ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | + MV88E6390_PORT_MAC_CTL_ALTSPEED; + break; + case 5000: + ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | + MV88E6390_PORT_MAC_CTL_ALTSPEED; + break; + case 10000: + case SPEED_UNFORCED: + ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; + break; + default: + return -EOPNOTSUPP; + } + + switch (duplex) { + case DUPLEX_HALF: + ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; + break; + case DUPLEX_FULL: + ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | + MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; + break; + case DUPLEX_UNFORCED: + /* normal duplex detection */ + break; + default: + return -EOPNOTSUPP; + } + + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); + if (err) + return err; + + reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | + MV88E6390_PORT_MAC_CTL_ALTSPEED | + MV88E6390_PORT_MAC_CTL_FORCE_SPEED); + + if (speed != SPEED_UNFORCED) + reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; + + reg |= ctrl; + + return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); + +} + static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode, bool force) { @@ -414,6 +501,9 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, case PHY_INTERFACE_MODE_2500BASEX: cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; break; + case PHY_INTERFACE_MODE_5GBASER: + cmode = MV88E6XXX_PORT_STS_CMODE_5GBASER; + break; case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_XAUI: cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; @@ -421,6 +511,13 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, case PHY_INTERFACE_MODE_RXAUI: cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; break; + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_10GKR: + cmode = MV88E6XXX_PORT_STS_CMODE_10GBASER; + break; + case PHY_INTERFACE_MODE_USXGMII: + cmode = MV88E6XXX_PORT_STS_CMODE_USXGMII; + break; default: cmode = 0; } @@ -505,6 +602,15 @@ int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, return mv88e6xxx_port_set_cmode(chip, port, mode, false); } +int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, + phy_interface_t mode) +{ + if (port != 0 && port != 9 && port != 10) + return -EOPNOTSUPP; + + return mv88e6xxx_port_set_cmode(chip, port, mode, false); +} + static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, int port) { @@ -1128,6 +1234,130 @@ int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); } +/* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ + +static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, u16 pointer, + u8 data) +{ + + int err = 0; + int port; + u16 reg; + + /* Setup per Port policy register */ + for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { + if (dsa_is_unused_port(chip->ds, port)) + continue; + + /* Prevent the use of an invalid port. */ + if (mv88e6xxx_is_invalid_port(chip, port)) { + dev_err(chip->dev, "port %d is invalid\n", port); + return -EINVAL; + } + reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; + err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, reg); + if (err) + return err; + } + return 0; +} + +int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, + enum mv88e6xxx_egress_direction direction, + int port) +{ + u16 ptr; + int err; + + switch (direction) { + case MV88E6XXX_EGRESS_DIR_INGRESS: + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; + err = mv88e6393x_port_policy_write(chip, ptr, port); + if (err) + return err; + break; + case MV88E6XXX_EGRESS_DIR_EGRESS: + ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; + err = mv88e6xxx_g2_write(chip, ptr, port); + if (err) + return err; + break; + } + return 0; +} + +int mv88e6393x_port_set_cpu_dest(struct mv88e6xxx_chip *chip, int port) +{ + u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; + u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | port; + + return mv88e6393x_port_policy_write(chip, ptr, data); +} + +int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) +{ + u16 ptr; + int err; + + /* Consider the frames with reserved multicast destination + * addresses matching 01:80:c2:00:00:00 and + * 01:80:c2:00:00:02 as MGMT. + */ + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; + err = mv88e6393x_port_policy_write(chip, ptr, 0xff); + if (err) + return err; + + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; + err = mv88e6393x_port_policy_write(chip, ptr, 0xff); + if (err) + return err; + + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; + err = mv88e6393x_port_policy_write(chip, ptr, 0xff); + if (err) + return err; + + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; + err = mv88e6393x_port_policy_write(chip, ptr, 0xff); + if (err) + return err; + + return 0; +} + +/* Offset 0x10 & 0x11: EPC */ + +static int mv88e6393x_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) +{ + int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); + + return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); +} + +/* Port Ether type for 6393X family */ + +int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, + u16 etype) +{ + u16 val; + int err; + + err = mv88e6393x_epc_wait_ready(chip, port); + if (err) + return err; + + err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); + if (err) + return err; + + val = MV88E6393X_PORT_EPC_CMD_BUSY | + MV88E6393X_PORT_EPC_CMD_WRITE | + MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; + + return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); +} + /* Offset 0x0f: Port Ether type */ int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h index 44d76ac973f6..2ed1eef15bca 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -49,6 +49,9 @@ #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d +#define MV88E6XXX_PORT_STS_CMODE_5GBASER 0x000c +#define MV88E6XXX_PORT_STS_CMODE_10GBASER 0x000d +#define MV88E6XXX_PORT_STS_CMODE_USXGMII 0x000e #define MV88E6185_PORT_STS_CDUPLEX 0x0008 #define MV88E6185_PORT_STS_CMODE_MASK 0x0007 #define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 @@ -117,6 +120,8 @@ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 +#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920 +#define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 @@ -129,6 +134,7 @@ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 +#define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f /* Offset 0x04: Port Control Register */ @@ -236,6 +242,19 @@ #define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002 #define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003 +/* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ +#define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e +#define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800 +#define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff +#define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0 + /* Offset 0x0F: Port Special Ether Type */ #define MV88E6XXX_PORT_ETH_TYPE 0x0f #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 @@ -243,6 +262,15 @@ /* Offset 0x10: InDiscards Low Counter */ #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 +/* Offset 0x10: Extended Port Control Command */ +#define MV88E6393X_PORT_EPC_CMD 0x10 +#define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 +#define MV88E6393X_PORT_EPC_CMD_WRITE 0x0300 +#define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 + +/* Offset 0x11: Extended Port Control Data */ +#define MV88E6393X_PORT_EPC_DATA 0x11 + /* Offset 0x11: InDiscards High Counter */ #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 @@ -288,7 +316,8 @@ int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, u16 *val); int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, u16 val); - +int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, + int bit, int val); int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, int pause); int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, @@ -312,7 +341,8 @@ int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); - +int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, + int speed, int duplex); phy_interface_t mv88e6341_port_max_speed_mode(int port); phy_interface_t mv88e6390_port_max_speed_mode(int port); phy_interface_t mv88e6390x_port_max_speed_mode(int port); @@ -346,6 +376,13 @@ int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_policy_action action); int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, u16 etype); +int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, + enum mv88e6xxx_egress_direction direction, + int port); +int mv88e6393x_port_set_cpu_dest(struct mv88e6xxx_chip *chip, int port); +int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); +int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, + u16 etype); int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, bool message_port); int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, @@ -362,6 +399,8 @@ int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); +int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, + phy_interface_t mode); int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c index 058cce01c01e..9a6822eaf3b9 100644 --- a/drivers/net/dsa/mv88e6xxx/serdes.c +++ b/drivers/net/dsa/mv88e6xxx/serdes.c @@ -526,6 +526,26 @@ int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) return lane; } +/* Only Ports 0, 9 and 10 have SERDES lanes. Return the SERDES lane address + * a port is using else Returns -ENODEV. + */ +int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) +{ + u8 cmode = chip->ports[port].cmode; + int lane = -ENODEV; + + if (port == 0 || port == 9 || port == 10) { + if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX || + cmode == MV88E6XXX_PORT_STS_CMODE_SGMII || + cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX || + cmode == MV88E6XXX_PORT_STS_CMODE_5GBASER || + cmode == MV88E6XXX_PORT_STS_CMODE_10GBASER || + cmode == MV88E6XXX_PORT_STS_CMODE_USXGMII) + lane = port; + } + return lane; +} + /* Set power up/down for 10GBASE-R and 10GBASE-X4/X2 */ static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, int lane, bool up) @@ -916,6 +936,51 @@ static int mv88e6390_serdes_irq_status_sgmii(struct mv88e6xxx_chip *chip, return err; } +int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, + int lane, bool enable) +{ + u8 cmode = chip->ports[port].cmode; + int err = 0; + + switch (cmode) { + case MV88E6XXX_PORT_STS_CMODE_SGMII: + case MV88E6XXX_PORT_STS_CMODE_1000BASEX: + case MV88E6XXX_PORT_STS_CMODE_2500BASEX: + case MV88E6XXX_PORT_STS_CMODE_5GBASER: + case MV88E6XXX_PORT_STS_CMODE_10GBASER: + err = mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable); + } + + return err; +} + +irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, + int lane) +{ + u8 cmode = chip->ports[port].cmode; + irqreturn_t ret = IRQ_NONE; + u16 status; + int err; + + switch (cmode) { + case MV88E6XXX_PORT_STS_CMODE_SGMII: + case MV88E6XXX_PORT_STS_CMODE_1000BASEX: + case MV88E6XXX_PORT_STS_CMODE_2500BASEX: + case MV88E6XXX_PORT_STS_CMODE_5GBASER: + case MV88E6XXX_PORT_STS_CMODE_10GBASER: + err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status); + if (err) + return ret; + if (status & (MV88E6390_SGMII_INT_LINK_DOWN | + MV88E6390_SGMII_INT_LINK_UP)) { + ret = IRQ_HANDLED; + mv88e6390_serdes_irq_link_sgmii(chip, port, lane); + } + } + + return ret; +} + irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane) { @@ -999,3 +1064,162 @@ void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p) p[i] = reg; } } + +int mv88e6393x_setup_errata(struct mv88e6xxx_chip *chip) +{ + u16 config0, config9, config10; + u16 pcs0, pcs9, pcs10; + int err = 0; + + /* mv88e6393x family errata 3.8 : + * When a SERDES port is operating in 1000BASE-X or SGMII mode link may not + * come up after hardware reset or software reset of SERDES core. + * Workaround is to write SERDES register 4.F074.14 =1 for only those modes + * and 0 in all other modes. + */ + err = mv88e6390_serdes_read(chip, MV88E6393X_PORT0_LANE, MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, &config0); + err = mv88e6390_serdes_read(chip, MV88E6393X_PORT9_LANE, MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, &config9); + err = mv88e6390_serdes_read(chip, MV88E6393X_PORT10_LANE, MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, &config10); + + err = mv88e6390_serdes_read(chip, MV88E6393X_PORT0_LANE, MDIO_MMD_PHYXS, + MV88E6393X_SERDES_POC, &pcs0); + pcs0 &= MV88E6393X_SERDES_POC_PCS_MODE_MASK; + err = mv88e6390_serdes_read(chip, MV88E6393X_PORT9_LANE, MDIO_MMD_PHYXS, + MV88E6393X_SERDES_POC, &pcs9); + pcs9 &= MV88E6393X_SERDES_POC_PCS_MODE_MASK; + err = mv88e6390_serdes_read(chip, MV88E6393X_PORT10_LANE, MDIO_MMD_PHYXS, + MV88E6393X_SERDES_POC, &pcs10); + pcs10 &= MV88E6393X_SERDES_POC_PCS_MODE_MASK; + + if (pcs0 == MV88E6393X_PCS_SELECT_1000BASEX || + pcs0 == MV88E6393X_PCS_SELECT_SGMII_PHY || + pcs0 == MV88E6393X_PCS_SELECT_SGMII_MAC) { + config0 |= MV88E6393X_ERRATA_1000BASEX_SGMII_BIT; + err = mv88e6390_serdes_write(chip, MV88E6393X_PORT0_LANE, + MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, + config0); + } else { + config0 &= ~MV88E6393X_ERRATA_1000BASEX_SGMII_BIT; + err = mv88e6390_serdes_write(chip, MV88E6393X_PORT0_LANE, + MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, + config0); + } + + if (pcs9 == MV88E6393X_PCS_SELECT_1000BASEX || + pcs9 == MV88E6393X_PCS_SELECT_SGMII_PHY || + pcs9 == MV88E6393X_PCS_SELECT_SGMII_MAC) { + config9 |= MV88E6393X_ERRATA_1000BASEX_SGMII_BIT; + err = mv88e6390_serdes_write(chip, MV88E6393X_PORT9_LANE, + MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, + config9); + } else { + config9 &= ~MV88E6393X_ERRATA_1000BASEX_SGMII_BIT; + err = mv88e6390_serdes_write(chip, MV88E6393X_PORT9_LANE, + MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, + config9); + } + + if (pcs10 == MV88E6393X_PCS_SELECT_1000BASEX || + pcs10 == MV88E6393X_PCS_SELECT_SGMII_PHY || + pcs10 == MV88E6393X_PCS_SELECT_SGMII_MAC) { + config10 |= MV88E6393X_ERRATA_1000BASEX_SGMII_BIT; + err = mv88e6390_serdes_write(chip, MV88E6393X_PORT10_LANE, + MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, + config10); + } else { + config10 &= ~MV88E6393X_ERRATA_1000BASEX_SGMII_BIT; + err = mv88e6390_serdes_write(chip, MV88E6393X_PORT10_LANE, + MDIO_MMD_PHYXS, + MV88E6393X_ERRATA_1000BASEX_SGMII, + config10); + } + return err; +} + +static int mv88e6393x_serdes_port_config(struct mv88e6xxx_chip *chip, int lane, + bool on) +{ + u8 cmode = chip->ports[lane].cmode; + u16 config, pcs; + + switch (cmode) { + case MV88E6XXX_PORT_STS_CMODE_1000BASEX: + pcs = MV88E6393X_PCS_SELECT_1000BASEX; + break; + case MV88E6XXX_PORT_STS_CMODE_2500BASEX: + pcs = MV88E6393X_PCS_SELECT_2500BASEX; + break; + case MV88E6XXX_PORT_STS_CMODE_10GBASER: + pcs = MV88E6393X_PCS_SELECT_10GBASER; + break; + default: + pcs = MV88E6393X_PCS_SELECT_1000BASEX; + break; + } + + if (on) { + /* mv88e6393x family errata 3.6 : + * When changing c_mode on Port 0 from [x]MII mode to any + * SERDES mode SERDES will not be operational. + * Workaround: Set Port0 SERDES register 4.F002.5=0 + */ + mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, + MV88E6393X_SERDES_POC, &config); + config &= ~(MV88E6393X_SERDES_POC_PCS_MODE_MASK | + MV88E6393X_SERDES_POC_PDOWN); + config |= pcs; + mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, + MV88E6393X_SERDES_POC, config); + config |= MV88E6393X_SERDES_POC_RESET; + mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, + MV88E6393X_SERDES_POC, config); + + /* mv88e6393x family errata 3.7 : + * When changing cmode on SERDES port from any other mode to + * 1000BASE-X mode the link may not come up due to invalid + * 1000BASE-X advertisement. + * Workaround: Correct advertisement and reset PHY core. + */ + config = MV88E6390_SGMII_ANAR_1000BASEX_FD; + mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, + MV88E6390_SGMII_ANAR, config); + + /* soft reset the PCS/PMA */ + mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, + MV88E6390_SGMII_CONTROL, &config); + config |= MV88E6390_SGMII_CONTROL_RESET; + mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, + MV88E6390_SGMII_CONTROL, config); + } + + return 0; +} + +int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, + bool on) +{ + if (port != 0 && port != 9 && port != 10) + return -EOPNOTSUPP; + + u8 cmode = chip->ports[port].cmode; + + mv88e6393x_serdes_port_config(chip, lane, on); + + switch (cmode) { + case MV88E6XXX_PORT_STS_CMODE_1000BASEX: + case MV88E6XXX_PORT_STS_CMODE_2500BASEX: + return mv88e6390_serdes_power_sgmii(chip, lane, on); + case MV88E6XXX_PORT_STS_CMODE_10GBASER: + return mv88e6390_serdes_power_10g(chip, lane, on); + } + + return 0; +} diff --git a/drivers/net/dsa/mv88e6xxx/serdes.h b/drivers/net/dsa/mv88e6xxx/serdes.h index ed3181e82da9..d508978e5944 100644 --- a/drivers/net/dsa/mv88e6xxx/serdes.h +++ b/drivers/net/dsa/mv88e6xxx/serdes.h @@ -68,15 +68,47 @@ #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10) #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3) #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2) +#define MV88E6390_SGMII_STATUS_AN_ABLE BIT(3) +#define MV88E6390_SGMII_ANAR 0x2004 +#define MV88E6390_SGMII_ANAR_1000BASEX_FD BIT(5) +#define MV88E6390_SGMII_CONTROL 0x2000 +#define MV88E6390_SGMII_CONTROL_RESET BIT(15) +#define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14) +#define MV88E6390_SGMII_CONTROL_PDOWN BIT(11) +#define MV88E6390_SGMII_STATUS 0x2001 /* Packet generator pad packet checker */ #define MV88E6390_PG_CONTROL 0xf010 #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0) +#define MV88E6393X_PORT0_LANE 0x00 +#define MV88E6393X_PORT9_LANE 0x09 +#define MV88E6393X_PORT10_LANE 0x0a + +/* Port Operational Configuration */ +#define MV88E6393X_PCS_SELECT_1000BASEX 0x0000 +#define MV88E6393X_PCS_SELECT_2500BASEX 0x0001 +#define MV88E6393X_PCS_SELECT_SGMII_PHY 0x0002 +#define MV88E6393X_PCS_SELECT_SGMII_MAC 0x0003 +#define MV88E6393X_PCS_SELECT_5GBASER 0x0004 +#define MV88E6393X_PCS_SELECT_10GBASER 0x0005 +#define MV88E6393X_PCS_SELECT_USXGMII_PHY 0x0006 +#define MV88E6393X_PCS_SELECT_USXGMII_MAC 0x0007 + +#define MV88E6393X_SERDES_POC 0xf002 +#define MV88E6393X_SERDES_POC_PCS_MODE_MASK 0x0007 +#define MV88E6393X_SERDES_POC_RESET BIT(15) +#define MV88E6393X_SERDES_POC_PDOWN BIT(5) +#define MV88E6393X_SERDES_POC_ANEG BIT(3) + +#define MV88E6393X_ERRATA_1000BASEX_SGMII 0xF074 +#define MV88E6393X_ERRATA_1000BASEX_SGMII_BIT BIT(14) + int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); +int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, int lane, unsigned int mode, phy_interface_t interface, @@ -105,14 +137,21 @@ int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, bool on); int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, bool on); +int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, + bool on); +int mv88e6393x_setup_errata(struct mv88e6xxx_chip *chip); int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, bool enable); int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, bool enable); +int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, + int lane, bool enable); irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane); irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane); +irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, + int lane); int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, int port, uint8_t *data);