From patchwork Mon Nov 5 21:40:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 10669241 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B34F18FD for ; Mon, 5 Nov 2018 21:40:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6629D29DF5 for ; Mon, 5 Nov 2018 21:40:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5A33629E0F; Mon, 5 Nov 2018 21:40:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF6E629DF5 for ; Mon, 5 Nov 2018 21:40:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387710AbeKFHCB (ORCPT ); Tue, 6 Nov 2018 02:02:01 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:54580 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387580AbeKFHCB (ORCPT ); Tue, 6 Nov 2018 02:02:01 -0500 Received: by mail-wm1-f65.google.com with SMTP id r63-v6so9866925wma.4; Mon, 05 Nov 2018 13:40:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=iM9z2HPieWUeI+aQ1GiKJJvzyCnh3E/L4CodI2yBqy0=; b=M9yUOwD5o9PcLQjRDiCJqGYsIK494Vg5873JgMmKxCLUgeaMnxyQPEr3/xpp6pP4N2 Y2IqARTn9N3RFGKbomMLV4tyjGoMaG2b2B9gvFlw0V4OFPV3WQ4bOiyWpKLdEp/ZyByW olIQXwODiOtS14ME0YASo6yxpCNTr1SxwWeWaW5l5fGFeXieOQ/wrEoeRNE5pHd8qEzd 36AwMIRR0Btqz8EAaU1lUEOE9dl5QAz6P8/s+eFN0LirzRkj8yic9O9WQYkOwNpQz73s pXAr9ZGcuhg4vnwhzQegezUJE6cxcG+6gDm/5ClrDZBteuGSBrb2hNi+RbeK2pFGehkA hGow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=iM9z2HPieWUeI+aQ1GiKJJvzyCnh3E/L4CodI2yBqy0=; b=SzP2ygk9di2p1kYBGZDP2ddrMGEiV/j2EHILqyNSTeWfuzp1HEChS/RqUNqZ8WOOKb zBgiHsYhXuSqfqlNicMAW4y3P8OYpL3pZWJkR/PM56cjvAOFWFhk8tcTuXO3NIuQ/0Vl Ef+NhZjYjRMo8d8qHV26HIX44EMeb4Qwzmo0sDUCMe2TJqL9fpdJUk/sIpAHex+jAc2c PTfeWVDGf3vTce7yPCP4NRqsB7UlxpVvP4FIXC6ig1MOBotuos4YrcmRiudYaDCyKyEl 3r9E8tfFp7YJXynHY7d/3W2TjX7mAXlnt+jpvzKwqi1BxiitTEGQwR52Sd1aMzRkpMe1 JZnQ== X-Gm-Message-State: AGRZ1gLONH+ip8chjtLl49k0I11cjLsZkLlG5p1TR0hdiVFoH0ivsAG5 rC0lNHR0DTsy86v7ucSC96pznUqk X-Google-Smtp-Source: AJdET5c2wvEZZii4iJSMFwukbUwygILWkMfAZmobmoLmzMi9NRA8+V89yRufkSqyFG+s3kkIVD3HPA== X-Received: by 2002:a1c:6754:: with SMTP id b81-v6mr7922705wmc.104.1541454015968; Mon, 05 Nov 2018 13:40:15 -0800 (PST) Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz. [86.49.110.70]) by smtp.gmail.com with ESMTPSA id x139-v6sm228851wme.3.2018.11.05.13.40.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 13:40:15 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Takeshi Kihara , Marek Vasut , Geert Uytterhoeven , Simon Horman , Wolfram Sang , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Date: Mon, 5 Nov 2018 22:40:11 +0100 Message-Id: <20181105214012.11626-1-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Simon Horman Cc: Wolfram Sang Cc: Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 218 +++++++++++++++++++++++++- 1 file changed, 216 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index 1fdafa48479c..97aba270a515 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -2386,6 +2386,174 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; + +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; + +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; + +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; + +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; + +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; + +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; + +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; + +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; + +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; + +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; + +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; + +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; + +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; + +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; + +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; + +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; + +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; + +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; + +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; + +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; + +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; + +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; + +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; + +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; + +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; + +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; + +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; + +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 10), +}; + +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_a_pins[] = { /* PWEN, OVC */ @@ -2434,7 +2602,7 @@ static const unsigned int usb30_id_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[123]; + struct sh_pfc_pin_group common[140]; struct sh_pfc_pin_group automotive[0]; } pinmux_groups = { .common = { @@ -2556,6 +2724,23 @@ static const struct { SH_PFC_PIN_GROUP(scif5_data_c), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), SH_PFC_PIN_GROUP(usb0_a), SH_PFC_PIN_GROUP(usb0_b), SH_PFC_PIN_GROUP(usb0_id), @@ -2763,6 +2948,32 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + static const char * const usb0_groups[] = { "usb0_a", "usb0_b", @@ -2775,7 +2986,7 @@ static const char * const usb30_groups[] = { }; static const struct { - struct sh_pfc_function common[29]; + struct sh_pfc_function common[32]; struct sh_pfc_function automotive[0]; } pinmux_functions = { .common = { @@ -2806,6 +3017,9 @@ static const struct { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb30), } From patchwork Mon Nov 5 21:40:12 2018 Content-Type: text/plain; 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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id x139-v6sm228851wme.3.2018.11.05.13.40.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 13:40:18 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Takeshi Kihara , Marek Vasut , Geert Uytterhoeven , Simon Horman , Wolfram Sang , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org Subject: [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Date: Mon, 5 Nov 2018 22:40:12 +0100 Message-Id: <20181105214012.11626-2-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181105214012.11626-1-marek.vasut+renesas@gmail.com> References: <20181105214012.11626-1-marek.vasut+renesas@gmail.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch supports the {get,set}_io_voltage operations of SDHI. This operates the IOCTRL30 register on the R8A77990 SoC and makes 1.8V/3.3V signal voltage switch possible. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Simon Horman Cc: Wolfram Sang Cc: Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: Yoshihiro Shimoda Acked-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 35 +++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index 97aba270a515..95d478353627 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -23,8 +23,12 @@ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS) /* @@ -3494,6 +3498,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +enum ioctrl_regs { + IOCTRL30, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [IOCTRL30] = { 0xe6060380, }, + { /* sentinel */ }, +}; + +static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) + bit = pin & 0x1f; + + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10)) + bit = (pin & 0x1f) + 19; + + return bit; +} + static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { [0] = RCAR_GP_PIN(2, 23), /* RD# */ @@ -3744,6 +3773,7 @@ static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, } static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { + .pin_to_pocctrl = r8a77990_pin_to_pocctrl, .get_bias = r8a77990_pinmux_get_bias, .set_bias = r8a77990_pinmux_set_bias, }; @@ -3790,6 +3820,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = { .cfg_regs = pinmux_config_regs, .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data),