From patchwork Sun Nov 22 09:55:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11923825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 497B3C71156 for ; Sun, 22 Nov 2020 09:56:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 156B221D91 for ; Sun, 22 Nov 2020 09:56:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jBT0H1Dp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727473AbgKVJ4E (ORCPT ); Sun, 22 Nov 2020 04:56:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727318AbgKVJ4B (ORCPT ); Sun, 22 Nov 2020 04:56:01 -0500 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F37AC0613D2; Sun, 22 Nov 2020 01:56:01 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id m6so15427653wrg.7; Sun, 22 Nov 2020 01:56:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Ub3gKGJwLJRaryXIKn0038/d6bzjLaWe3sRPb09LY0=; b=jBT0H1Dp2FdOl9/WZ1YWZ+a17R3h28nmfNH/n3MTXgBZvp0B0tFBVLrSX1eel3fws7 zczlkEU8MXE3OlLatadk4ioBE2wyEB8xDJuj8AVal3kayTkAnFQnYB9f3jwp+COyd6N8 PCVwR3PayXHMNyY/KZf5lkplIy2q3LQZxjQgRn2JE3ROeoTyc4yRuHDG5iyQavFoZAyx CM6aEhZf6GvySbBfVeqGxijjM/KP7ugxV7qF799TjmM0hrXZKuu5jr578iXyR430Smgw 5adXJq28o3cBGvHc7sMflHk0dzLxBNPuK+4w5d+6yrgtpbVJNiAWWJLAJWMNcBchi+KZ 6YAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Ub3gKGJwLJRaryXIKn0038/d6bzjLaWe3sRPb09LY0=; b=q8HBvBTNT69UAsy/YMP+AsQNaC6lur2lU0reOnp2x6rUR7Ib9DtTOxVzKp0M8wumDB 2CZjQcA/jdI6ki7A+LVDt4S4VMj5J+qjBnvA6YGPKBgG+C95Dv5KZzTYjIvbsMjm4UVP /BeO+zheVfl5bYs4jrvutCeaIqIJ1SltGPh6bmMF3u6N2Erqus+S+kqmBjcrCLVDRG5N VVUCvyLOS53cXU6/NUKZOTa0fcv+jbk+4n/pHMz7DsNMjC42jmP+RT4Ghu117qHvDcSJ PWMKQgCobYgW0wthNH1S26NNTIuNhOj+wqBax8ioiZqVXC04uoK8liqP5FXTQnJCeiH6 iOoQ== X-Gm-Message-State: AOAM530ZaY/G8KHahUrSozeWWRDhu5Du2oqJwD1xkDnv9Idyl6elEYID 8n+qdq3CIGrirtVnGJOwcPdUcp/HIXITqSqU X-Google-Smtp-Source: ABdhPJwRL/xcxAwX7RQbo8ROZ7c59q0dn7A87ObIujR0wFzdpeevrwvC6al2Y2KMHD3wzntxlKexSw== X-Received: by 2002:adf:f083:: with SMTP id n3mr25048052wro.391.1606038960179; Sun, 22 Nov 2020 01:56:00 -0800 (PST) Received: from localhost.localdomain (196.red-83-40-48.dynamicip.rima-tde.net. [83.40.48.196]) by smtp.gmail.com with ESMTPSA id p21sm10593570wma.41.2020.11.22.01.55.58 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Nov 2020 01:55:59 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, linux-clk@vger.kernel.org, evicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name, Rob Herring Subject: [PATCH v4 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Date: Sun, 22 Nov 2020 10:55:51 +0100 Message-Id: <20201122095556.21597-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201122095556.21597-1-sergio.paracuellos@gmail.com> References: <20201122095556.21597-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index 000000000000..1422badcf9de --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Sergio Paracuellos + */ + +#ifndef _DT_BINDINGS_CLK_MT7621_H +#define _DT_BINDINGS_CLK_MT7621_H + +#define MT7621_CLK_XTAL 0 +#define MT7621_CLK_CPU 1 +#define MT7621_CLK_BUS 2 +#define MT7621_CLK_50M 3 +#define MT7621_CLK_125M 4 +#define MT7621_CLK_150M 5 +#define MT7621_CLK_250M 6 +#define MT7621_CLK_270M 7 + +#define MT7621_CLK_HSDMA 8 +#define MT7621_CLK_FE 9 +#define MT7621_CLK_SP_DIVTX 10 +#define MT7621_CLK_TIMER 11 +#define MT7621_CLK_PCM 12 +#define MT7621_CLK_PIO 13 +#define MT7621_CLK_GDMA 14 +#define MT7621_CLK_NAND 15 +#define MT7621_CLK_I2C 16 +#define MT7621_CLK_I2S 17 +#define MT7621_CLK_SPI 18 +#define MT7621_CLK_UART1 19 +#define MT7621_CLK_UART2 20 +#define MT7621_CLK_UART3 21 +#define MT7621_CLK_ETH 22 +#define MT7621_CLK_PCIE0 23 +#define MT7621_CLK_PCIE1 24 +#define MT7621_CLK_PCIE2 25 +#define MT7621_CLK_CRYPTO 26 +#define MT7621_CLK_SHXC 27 + +#define MT7621_CLK_MAX 28 + +#endif /* _DT_BINDINGS_CLK_MT7621_H */ From patchwork Sun Nov 22 09:55:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11923819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED83C64E7B for ; Sun, 22 Nov 2020 09:56:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EEC28221FB for ; Sun, 22 Nov 2020 09:56:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Uh+whNe3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727513AbgKVJ4E (ORCPT ); Sun, 22 Nov 2020 04:56:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726741AbgKVJ4D (ORCPT ); Sun, 22 Nov 2020 04:56:03 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF0C1C0613D2; Sun, 22 Nov 2020 01:56:02 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id r17so15494906wrw.1; Sun, 22 Nov 2020 01:56:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T+KDk+GBhmbsGEu60u7jvpaynFthMi6GIe7Bnot8k+o=; b=Uh+whNe3cPPIgIIpgy9BIHV68Nwaqi3YqAy+wWNN3dB7/Ol31eg5Nm0DXKa2zJflb8 BT3nDDxSAtAoWV1Ana/QMeCYVyBcNdS1JH/lKGuRi63E22SJI0qkXzCvBTpwG9yRFJR8 bQyscJkHZwHVUJVdmtOrtUD8J2S0rwJKTy20+YFXbnAeDcXlf9UKMLgax6T+i7nIVOdt iu3uEfpPWXlIbZAxxOgu12Fv8zuQxPC9931cVQNqvVTEwchIsALeeh2eFpfT0n9qXxn5 CSBpEtKm1gBKAITztqMkfJksdVoJFNx80i7VBUo/F1CKNnmEkUIdqfs1RXTQ9uddNZTT QSNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T+KDk+GBhmbsGEu60u7jvpaynFthMi6GIe7Bnot8k+o=; b=JKcfl+6b6nHTC8Q6mQNssrztqH0jWvjZa/utyTFdDrweiCGumN0np1w/tA0k8hUTMa GIfxsccRxsofCTtsj//1HLihDXUTfbT8QMEcyUiGFZ5doR5u5M7VQR2rDsSrl21Tox/O m7DYwm1tZxGPT2T9NGGx5vE6qNcnCxlYu0q9lq+PrcD2tpqyNnQfqwL/PnOKnvEJaNbR IHmY57T9tGAMUiOmejaTcgcQm+C0IcXVZe9U2TBl3BUnKix+7ja88bCUblGC5RwA7lyo KZOWEkmVZ1SPCVYWZ07N1oHUdzr0F6MCo9W5BXxdbP7J2PWaODHZO/rJUS8a/DZyBLDB 2AeA== X-Gm-Message-State: AOAM531Ok41Bu4r6khfuS6CEWn2bp1zTHNdPfTZAKtosIYKn3+8lBZUd jNGp9XngH3X2WAEIXKv8VFo= X-Google-Smtp-Source: ABdhPJxJKmmkqIMRwUYglxlRGgGbnPcX99HF0yMNKqjzuc0XukFjSUbDrTc4gvqq7AbheWWoaAScow== X-Received: by 2002:adf:eeca:: with SMTP id a10mr24027157wrp.186.1606038961510; Sun, 22 Nov 2020 01:56:01 -0800 (PST) Received: from localhost.localdomain (196.red-83-40-48.dynamicip.rima-tde.net. [83.40.48.196]) by smtp.gmail.com with ESMTPSA id p21sm10593570wma.41.2020.11.22.01.56.00 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Nov 2020 01:56:01 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, linux-clk@vger.kernel.org, evicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name Subject: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation Date: Sun, 22 Nov 2020 10:55:52 +0100 Message-Id: <20201122095556.21597-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201122095556.21597-1-sergio.paracuellos@gmail.com> References: <20201122095556.21597-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml new file mode 100644 index 000000000000..6aca4c1a4a46 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: . + + The mt7621 clock node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "mediatek,mt7621-sysc", "syscon" + + Refer to the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + +properties: + compatible: + const: mediatek,mt7621-clk + + "#clock-cells": + description: + The first cell indicates the clock gate number, see [1] for available + clocks. + const: 1 + + clock-output-names: + maxItems: 8 + +required: + - compatible + - '#clock-cells' + - clock-output-names + +additionalProperties: false + +examples: + - | + #include + + sysc: sysc@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + + pll { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; + }; From patchwork Sun Nov 22 09:55:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11923817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E8E2C64E69 for ; Sun, 22 Nov 2020 09:56:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25D1520936 for ; Sun, 22 Nov 2020 09:56:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LCDJ4mWG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727589AbgKVJ4G (ORCPT ); Sun, 22 Nov 2020 04:56:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727517AbgKVJ4E (ORCPT ); Sun, 22 Nov 2020 04:56:04 -0500 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35A03C0613D2; Sun, 22 Nov 2020 01:56:04 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id s13so14468120wmh.4; Sun, 22 Nov 2020 01:56:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+y5YB6JXd29L54/5VsYH+43g+RS6v+u8YYmdDmRnWgA=; b=LCDJ4mWG9cg8cFa9XdrllVCCZ95cG7iIffCbXTkKuBxEAh4WllGJeR3ktgjTRyJ2lN 0tAs8iRyyLSnaDBU1NX6GF99WRDkkeNcZDZILgUYzyWwAToknV5xsnTrK2YiIIO1ZE99 QNt/bCBGgmwMf38Jpzh/zqCm9qxWYF/GFrlcdRUrqYoFYHYc7+m93Jz7AtiWQxMfvuYY OzU7khoF5vrIgZvleGPiaqXW57cvpy3p+CUtKXGnilY8/Pwb4JtTbN4FKHB8YueSVTrI cICF+DniGZRv8kzja0DDwRCMApI+bJ584L63OcolawYtKKYT0Xg022aXArzwZPoFqTt6 zSpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+y5YB6JXd29L54/5VsYH+43g+RS6v+u8YYmdDmRnWgA=; b=Waspsk7Lb+c3iQ4HNWIfmLMSRt08iAqHaSSokC+ff0Dg4xhtW71K86bqUOMNaOn1Ir jC5WlPEUn95V24jPVwA5QVTS6i09Izabz92UUhRMIO8daWGNVdnk2CpMlBvluVtvWnnY VGKVSPkTYdOZviI3TWwn4t70b3h/uMI0uJr5orAT8lC7rlOZ+sn6oudrDnWXUo4w4aY9 ZSDPGXslLCd3pFPyK4g/CCfyFKgtxbk53ql4AtHd2dmmcdMTKkJoUyonlpURkjoy+MK2 QmtXVv9OMbNv0GKSza4/sh3rto2Zvn09/10XiYGTkI5Ld3vemwC76iOv0jHPLVEjj5KI Jp9A== X-Gm-Message-State: AOAM531tzxye1H9aBlZuhaZHhBrvZCdHq1oniqBsc7JKk2b1Id0bGPbP oCVeF2IGhZyT7unF8btQnKs= X-Google-Smtp-Source: ABdhPJwootAGbojo5uXAgFWbWT7xx0D6n/YQdcLRUb/XYXnxDPbMtewn9itil7ByFlhMNeBF40m3EA== X-Received: by 2002:a1c:9652:: with SMTP id y79mr19015952wmd.71.1606038962872; Sun, 22 Nov 2020 01:56:02 -0800 (PST) Received: from localhost.localdomain (196.red-83-40-48.dynamicip.rima-tde.net. [83.40.48.196]) by smtp.gmail.com with ESMTPSA id p21sm10593570wma.41.2020.11.22.01.56.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Nov 2020 01:56:02 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, linux-clk@vger.kernel.org, evicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name Subject: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC Date: Sun, 22 Nov 2020 10:55:53 +0100 Message-Id: <20201122095556.21597-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201122095556.21597-1-sergio.paracuellos@gmail.com> References: <20201122095556.21597-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. Looking into driver code, and some openWRT patched there are another frequences which are used in some drivers (uart, sd...). According to all of this information the clock plan for this SoC is set as follows: - Main top clock "xtal" from where all the rest of the world is derived. - CPU clock "cpu" derived from "xtal" frequencies and a bunch of register reads and predividers. - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz. - Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz. We also have a buch of gate clocks with their parents: * "hsdma": "150m" * "fe": "250m" * "sp_divtx": "270m" * "timer": "50m" * "pcm": "270m" * "pio": "50m" * "gdma": "bus" * "nand": "125m" * "i2c": "50m" * "i2s": "270m" * "spi": "bus" * "uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m" * "shxc": "50m" With this information the clk driver will provide clock and gates functionality from a a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Signed-off-by: Sergio Paracuellos --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ralink/Kconfig | 14 + drivers/clk/ralink/Makefile | 2 + drivers/clk/ralink/clk-mt7621.c | 435 ++++++++++++++++++++++++++++++++ 5 files changed, 453 insertions(+) create mode 100644 drivers/clk/ralink/Kconfig create mode 100644 drivers/clk/ralink/Makefile create mode 100644 drivers/clk/ralink/clk-mt7621.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c715d4681a0b..5f94c4329033 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" +source "drivers/clk/ralink/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index da8fcf147eb1..6578e167b047 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ +obj-y += ralink/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig new file mode 100644 index 000000000000..7e8697327e0c --- /dev/null +++ b/drivers/clk/ralink/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# MediaTek Mt7621 Clock Driver +# +menu "Clock driver for mediatek mt7621 SoC" + depends on SOC_MT7621 || COMPILE_TEST + +config CLK_MT7621 + bool "Clock driver for MediaTek MT7621" + depends on SOC_MT7621 || COMPILE_TEST + default SOC_MT7621 + help + This driver supports MediaTek MT7621 basic clocks. +endmenu diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile new file mode 100644 index 000000000000..cf6f9216379d --- /dev/null +++ b/drivers/clk/ralink/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c new file mode 100644 index 000000000000..4e929f13fe7c --- /dev/null +++ b/drivers/clk/ralink/clk-mt7621.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek MT7621 Clock Driver + * Author: Sergio Paracuellos + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Configuration registers */ +#define SYSC_REG_SYSTEM_CONFIG0 0x10 +#define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_CUR_CLK_STS 0x44 + +#define MEMC_REG_CPU_PLL 0x648 +#define XTAL_MODE_SEL_MASK 0x7 +#define XTAL_MODE_SEL_SHIFT 6 + +#define CPU_CLK_SEL_MASK 0x3 +#define CPU_CLK_SEL_SHIFT 30 + +#define CUR_CPU_FDIV_MASK 0x1f +#define CUR_CPU_FDIV_SHIFT 8 +#define CUR_CPU_FFRAC_MASK 0x1f +#define CUR_CPU_FFRAC_SHIFT 0 + +#define CPU_PLL_PREDIV_MASK 0x3 +#define CPU_PLL_PREDIV_SHIFT 12 +#define CPU_PLL_FBDIV_MASK 0x7f +#define CPU_PLL_FBDIV_SHIFT 4 + +#define MHZ(x) ((x) * 1000 * 1000) + +struct mt7621_clk_provider { + struct device_node *node; + struct regmap *syscon_regmap; + struct clk_hw_onecell_data *clk_data; +}; + +struct mt7621_clk { + struct mt7621_clk_provider *clk_prov; + struct clk_hw hw; +}; + +struct mt7621_fixed_clk { + u8 idx; + const char *name; + const char *parent_name; + struct mt7621_clk_provider *clk_prov; + unsigned long rate; + struct clk_hw *hw; +}; + +struct mt7621_gate { + u8 idx; + const char *name; + const char *parent_name; + struct mt7621_clk_provider *clk_prov; + u32 bit_idx; + struct clk_hw hw; +}; + +#define GATE(_id, _name, _pname, _shift) \ + { \ + .idx = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .clk_prov = NULL, \ + .bit_idx = _shift \ + } + +static struct mt7621_gate mt7621_gates[] = { + GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)), + GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)), + GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)), + GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)), + GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)), + GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)), + GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)), + GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)), + GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)), + GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)), + GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)), + GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)), + GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)), + GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)), + GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)), + GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)), + GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)), + GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)), + GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)), + GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30)) +}; + +static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw) +{ + return container_of(hw, struct mt7621_gate, hw); +} + +static int mt7621_gate_enable(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *scon = clk_gate->clk_prov->syscon_regmap; + + return regmap_update_bits(scon, SYSC_REG_CLKCFG1, + clk_gate->bit_idx, clk_gate->bit_idx); +} + +static void mt7621_gate_disable(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *scon = clk_gate->clk_prov->syscon_regmap; + + regmap_update_bits(scon, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); +} + +static int mt7621_gate_is_enabled(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *scon = clk_gate->clk_prov->syscon_regmap; + unsigned int val; + + if (regmap_read(scon, SYSC_REG_CLKCFG1, &val)) + return 0; + + return val & clk_gate->bit_idx; +} + +static const struct clk_ops mt7621_gate_ops = { + .enable = mt7621_gate_enable, + .disable = mt7621_gate_disable, + .is_enabled = mt7621_gate_is_enabled, +}; + +static int mt7621_gate_ops_init(struct device_node *np, + struct mt7621_gate *sclk) +{ + struct clk_init_data init = { + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .num_parents = 1, + .parent_names = &sclk->parent_name, + .ops = &mt7621_gate_ops, + .name = sclk->name, + }; + + sclk->hw.init = &init; + return of_clk_hw_register(np, &sclk->hw); +} + +static int mt7621_register_gates(struct mt7621_clk_provider *clk_prov) +{ + struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data; + struct clk_hw **hws = (*clk_data)->hws; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) { + struct mt7621_gate *sclk = &mt7621_gates[i]; + + sclk->clk_prov = clk_prov; + ret = mt7621_gate_ops_init(clk_prov->node, sclk); + if (ret) { + pr_err("Couldn't register clock %s\n", sclk->name); + goto err_clk_unreg; + } + + hws[sclk->idx] = &sclk->hw; + (*clk_data)->num++; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + struct mt7621_gate *sclk = &mt7621_gates[i]; + + clk_hw_unregister(&sclk->hw); + } + return ret; +} + +#define FIXED(_id, _name, _pname, _rate) \ + { \ + .idx = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .clk_prov = NULL, \ + .rate = _rate \ + } + +static struct mt7621_fixed_clk mt7621_fixed_clks[] = { + FIXED(MT7621_CLK_50M, "50m", "xtal", MHZ(50)), + FIXED(MT7621_CLK_125M, "125m", "xtal", MHZ(125)), + FIXED(MT7621_CLK_150M, "150m", "xtal", MHZ(150)), + FIXED(MT7621_CLK_250M, "250m", "xtal", MHZ(250)), + FIXED(MT7621_CLK_270M, "270m", "xtal", MHZ(270)), +}; + +static int mt7621_register_fixed_clocks(struct mt7621_clk_provider *clk_prov) +{ + struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data; + struct clk_hw **hws = (*clk_data)->hws; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) { + struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; + + sclk->clk_prov = clk_prov; + sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, + sclk->parent_name, 0, + sclk->rate); + if (IS_ERR(sclk->hw)) { + pr_err("Couldn't register clock %s\n", sclk->name); + ret = PTR_ERR(sclk->hw); + goto err_clk_unreg; + } + + hws[sclk->idx] = sclk->hw; + (*clk_data)->num++; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; + + clk_hw_unregister_fixed_rate(sclk->hw); + } + return ret; +} + +static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw) +{ + return container_of(hw, struct mt7621_clk, hw); +} + +static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mt7621_clk *clk = to_mt7621_clk(hw); + struct regmap *scon = clk->clk_prov->syscon_regmap; + u32 val; + + regmap_read(scon, SYSC_REG_SYSTEM_CONFIG0, &val); + val = (val >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; + + if (val <= 2) + return MHZ(20); + else if (val <= 5) + return MHZ(40); + + return MHZ(25); +} + +static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + static const u32 prediv_tbl[] = { 0, 1, 2, 2 }; + struct mt7621_clk *clk = to_mt7621_clk(hw); + struct regmap *scon = clk->clk_prov->syscon_regmap; + u32 clkcfg, clk_sel, curclk, ffiv, ffrac; + u32 pll, prediv, fbdiv; + unsigned long cpu_clk; + + regmap_read(scon, SYSC_REG_CLKCFG0, &clkcfg); + clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; + + regmap_read(scon, SYSC_REG_CUR_CLK_STS, &curclk); + ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; + ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; + + switch (clk_sel) { + case 0: + cpu_clk = MHZ(500); + break; + case 1: + pll = rt_memc_r32(MEMC_REG_CPU_PLL); + fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; + prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; + cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; + break; + default: + cpu_clk = xtal_clk; + } + + return cpu_clk / ffiv * ffrac; +} + +static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 4; +} + +#define CLK_BASE(_name, _parent, _recalc) { \ + .init = &(struct clk_init_data) { \ + .name = _name, \ + .ops = &(const struct clk_ops) { \ + .recalc_rate = _recalc, \ + }, \ + .parent_names = (const char *const[]) { _parent }, \ + .num_parents = _parent ? 1 : 0 \ + }, \ +} + +static struct mt7621_clk mt7621_clks_base[] = { + { NULL, CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) }, + { NULL, CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) }, + { NULL, CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) }, +}; + +static int mt7621_register_top_clocks(struct mt7621_clk_provider *clk_prov) +{ + struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data; + struct clk_hw **hws = (*clk_data)->hws; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { + struct mt7621_clk *sclk = &mt7621_clks_base[i]; + + sclk->clk_prov = clk_prov; + ret = of_clk_hw_register(clk_prov->node, &sclk->hw); + if (ret) { + pr_err("Couldn't register top clock %i\n", i); + goto err_clk_unreg; + } + + hws[i] = &sclk->hw; + (*clk_data)->num++; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + struct mt7621_clk *sclk = &mt7621_clks_base[i]; + + clk_hw_unregister(&sclk->hw); + } + return ret; +} + +static void __init mt7621_clk_init(struct device_node *node) +{ + struct mt7621_clk_provider *clk_prov; + struct clk_hw_onecell_data **clk_data; + int i, ret, count; + + clk_prov = kzalloc(sizeof(*clk_prov), GFP_KERNEL); + if (!clk_prov) + return; + + clk_prov->syscon_regmap = syscon_node_to_regmap(node->parent); + if (IS_ERR(clk_prov->syscon_regmap)) { + pr_err("Could not get syscon regmap\n"); + goto free_clk_prov; + } + + clk_prov->node = node; + + clk_data = &clk_prov->clk_data; + count = ARRAY_SIZE(mt7621_clks_base) + + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); + *clk_data = kzalloc(struct_size(*clk_data, hws, count), GFP_KERNEL); + if (!*clk_data) + goto free_clk_prov; + + ret = mt7621_register_top_clocks(clk_prov); + if (ret) { + pr_err("Couldn't register top clocks\n"); + goto free_clk_data; + } + + ret = mt7621_register_fixed_clocks(clk_prov); + if (ret) { + pr_err("Couldn't register fixed clocks\n"); + goto unreg_clk_top; + } + + ret = mt7621_register_gates(clk_prov); + if (ret) { + pr_err("Couldn't register fixed clock gates\n"); + goto unreg_clk_fixed; + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, + clk_prov->clk_data); + if (ret) { + pr_err("Couldn't add clk hw provider\n"); + goto unreg_clk_gates; + } + + return; + +unreg_clk_gates: + for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) { + struct mt7621_gate *sclk = &mt7621_gates[i]; + + clk_hw_unregister(&sclk->hw); + } + +unreg_clk_fixed: + for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) { + struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; + + clk_hw_unregister_fixed_rate(sclk->hw); + } + +unreg_clk_top: + for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { + struct mt7621_clk *sclk = &mt7621_clks_base[i]; + + clk_hw_unregister(&sclk->hw); + } + +free_clk_data: + kfree(clk_prov->clk_data); + +free_clk_prov: + kfree(clk_prov); +} + +CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-clk", mt7621_clk_init); + +MODULE_AUTHOR("Sergio Paracuellos "); +MODULE_DESCRIPTION("Mediatek Mt7621 clock driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Nov 22 09:55:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11923821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0755CC64E7C for ; Sun, 22 Nov 2020 09:56:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDD0C21973 for ; Sun, 22 Nov 2020 09:56:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HZ9OppMb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727646AbgKVJ4J (ORCPT ); Sun, 22 Nov 2020 04:56:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727318AbgKVJ4F (ORCPT ); Sun, 22 Nov 2020 04:56:05 -0500 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DCCDC0613CF; Sun, 22 Nov 2020 01:56:05 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id 10so15055380wml.2; Sun, 22 Nov 2020 01:56:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=34c/ORCVvKeqOFHhpB6vUqWtlqnfaCl8EHETq+kfQnc=; b=HZ9OppMbRFhsSZtBEXaVZOorhERtMMs/AkkCrlOwmY9yI6Yf1zIYnoOYZ3ceTl1pw/ J9mqmeMbM/XOCH9ddHV8wOQDgdNUM7jpTJhGyeZ1CrGJgDur2xN5Mtr2W/FNDoXVHsTA qn72WbknS2Sc3oHjsUyZFTqvdch5yyL46C1TkeIsbWKqF8c129Hz/mtuXY2r3fwwG19K nGcqG5Wakk5S4LN4X2Dlh+p4JQsBN8BOys8nAoJ+KjKCh7JnqaymGA4Ti3muF/ALgVId t5qdxGwQ+s6agOi1uq/EzJTbjvMSMKJWWZDfqEOZoJ6kMHbJ6i78FUF8qUwd9hKmukjJ TeVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=34c/ORCVvKeqOFHhpB6vUqWtlqnfaCl8EHETq+kfQnc=; b=AWFofWDHqmfSOUm2nLo/fSNB0IGcv/JY3Ujidr/80QybAHYHTGU4HCr4ZfJidbnKmM Mu7VntwBPk2KhjQOgXiVZFuQj7ewAm34d/zwdWpxUHiCCC6bD9siXYiUtKcVTwhP7I4i hPz+wsTzWbtGlb/6jr1J1BmG1V60aaMf610XQBNTAPavoR+ejpNEPcRMT1Ph+sjx4Ajo vebVYhx8AXnjfNWx0TvaFA86H1xeJ97kN57KjJWuSPqrGd+PtezhpSAXF1+XFKN0DA56 AL4NhZo93TJWysBfzIkBRYLv7r5omdAZ0Zix08rYlptX6YO9F2bH7hwzJPJFXsz4Y/EQ VHtw== X-Gm-Message-State: AOAM532dUQNooqELWCyO+L3H8Ql/KYKfeMJvQNy0NHi3pzBwuJPGjJOo EpYrBCHzw2+pMTSxYXy6+ko= X-Google-Smtp-Source: ABdhPJyoz2wKHJsubf2UrBMB8U9DVoWcZQSJcmhGk4VVpWN1P2rzDHxfJx4/VrzZCTyaE/pnbGfjoQ== X-Received: by 2002:a1c:205:: with SMTP id 5mr17760812wmc.7.1606038964354; Sun, 22 Nov 2020 01:56:04 -0800 (PST) Received: from localhost.localdomain (196.red-83-40-48.dynamicip.rima-tde.net. [83.40.48.196]) by smtp.gmail.com with ESMTPSA id p21sm10593570wma.41.2020.11.22.01.56.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Nov 2020 01:56:03 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, linux-clk@vger.kernel.org, evicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name Subject: [PATCH v4 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Date: Sun, 22 Nov 2020 10:55:54 +0100 Message-Id: <20201122095556.21597-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201122095556.21597-1-sergio.paracuellos@gmail.com> References: <20201122095556.21597-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/gbpc1.dts | 11 ---- drivers/staging/mt7621-dts/mt7621.dtsi | 75 ++++++++++++-------------- 2 files changed, 35 insertions(+), 51 deletions(-) diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts index a7c0d3115d72..7716d0efe524 100644 --- a/drivers/staging/mt7621-dts/gbpc1.dts +++ b/drivers/staging/mt7621-dts/gbpc1.dts @@ -100,17 +100,6 @@ partition@50000 { }; }; -&sysclock { - compatible = "fixed-clock"; - /* This is normally 1/4 of cpuclock */ - clock-frequency = <225000000>; -}; - -&cpuclock { - compatible = "fixed-clock"; - clock-frequency = <900000000>; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 82aa93634eda..35cfda8f6faf 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,5 +1,6 @@ #include #include +#include / { #address-cells = <1>; @@ -27,27 +28,6 @@ aliases { serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* This is normally 1/4 of cpuclock */ - clock-frequency = <220000000>; - }; - - mmc_clock: mmc_clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; mmc_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; @@ -76,8 +56,16 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; + compatible = "mtk,mt7621-sysc", "syscon"; reg = <0x0 0x100>; + + pll: pll { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; }; wdt: wdt@100 { @@ -100,8 +88,8 @@ i2c: i2c@900 { compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysclock>; - + clocks = <&pll MT7621_CLK_I2C>; + clock-names = "i2c"; resets = <&rstctrl 16>; reset-names = "i2c"; @@ -118,8 +106,8 @@ i2s: i2s@a00 { compatible = "mediatek,mt7621-i2s"; reg = <0xa00 0x100>; - clocks = <&sysclock>; - + clocks = <&pll MT7621_CLK_I2S>; + clock-names = "i2s"; resets = <&rstctrl 17>; reset-names = "i2s"; @@ -155,8 +143,8 @@ uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; - clock-frequency = <50000000>; + clocks = <&pll MT7621_CLK_UART1>; + clock-names = "uart1"; interrupt-parent = <&gic>; interrupts = ; @@ -172,7 +160,8 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_SPI>; + clock-names = "spi"; resets = <&rstctrl 18>; reset-names = "spi"; @@ -188,6 +177,8 @@ gdma: gdma@2800 { compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; + clocks = <&pll MT7621_CLK_GDMA>; + clock-names = "gdma"; resets = <&rstctrl 14>; reset-names = "dma"; @@ -205,6 +196,8 @@ hsdma: hsdma@7000 { compatible = "mediatek,mt7621-hsdma"; reg = <0x7000 0x1000>; + clocks = <&pll MT7621_CLK_HSDMA>; + clock-names = "hsdma"; resets = <&rstctrl 5>; reset-names = "hsdma"; @@ -315,11 +308,6 @@ rstctrl: rstctrl { #reset-cells = <1>; }; - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -338,7 +326,8 @@ sdhci: sdhci@1E130000 { pinctrl-0 = <&sdhci_pins>; pinctrl-1 = <&sdhci_pins>; - clocks = <&mmc_clock &mmc_clock>; + clocks = <&pll MT7621_CLK_SHXC>, + <&pll MT7621_CLK_50M>; clock-names = "source", "hclk"; interrupt-parent = <&gic>; @@ -353,7 +342,7 @@ xhci: xhci@1E1C0000 { 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_XTAL>; clock-names = "sys_ck"; interrupt-parent = <&gic>; @@ -372,7 +361,7 @@ gic: interrupt-controller@1fbc0000 { timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; @@ -385,6 +374,9 @@ nand: nand@1e003000 { 0x1e003800 0x800>; #address-cells = <1>; #size-cells = <1>; + + clocks = <&pll MT7621_CLK_NAND>; + clock-names = "nand"; }; ethsys: syscon@1e000000 { @@ -398,8 +390,9 @@ ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysclock>; - clock-names = "ethif"; + clocks = <&pll MT7621_CLK_FE>, + <&pll MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; #address-cells = <1>; #size-cells = <0>; @@ -532,7 +525,9 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clocks = <&pll MT7621_CLK_PCIE0>, + <&pll MT7621_CLK_PCIE1>, + <&pll MT7621_CLK_PCIE2>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2"; From patchwork Sun Nov 22 09:55:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11923823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A820FC64E90 for ; Sun, 22 Nov 2020 09:56:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 772F62137B for ; Sun, 22 Nov 2020 09:56:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Iov1hSHi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727698AbgKVJ4M (ORCPT ); Sun, 22 Nov 2020 04:56:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727634AbgKVJ4H (ORCPT ); Sun, 22 Nov 2020 04:56:07 -0500 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3AA8C0613D2; Sun, 22 Nov 2020 01:56:06 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id w24so14480657wmi.0; Sun, 22 Nov 2020 01:56:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pH4YiFa3zIrW5cBsHONER3WL/ieQbB97y8DpDIKkWFI=; b=Iov1hSHiHu+XHsVKC76tIQefz8RyYifIOEPd+qZhGln//cGkhaG4HeNg+ML6ooWvC4 GdJRSC9fCzRSCqQFjx6/34cUs8EfZxHTJwBgLNfuNViUHX8oj+4zUVh6d+hrth78Rpv1 VwkXBFSSuY8wif+tZ0jZcH0r2+de4S0vhtFs6pIsjOjZn9vKezpWvaZ8VBqt+ZQYd0hW FIxepQaF2Wn+usjPOxgAoIfWecbkxOYBpt+uahdcjO55e2StrmeUuYEiQY7xaxBoX0mw SEbo0CGuv6ei/JwfzGKtgtnz8TliR+IsCWbyd7QGkqrMy8l4YFNzWn6iLlPDQhB4SySV 801g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pH4YiFa3zIrW5cBsHONER3WL/ieQbB97y8DpDIKkWFI=; b=p+vHb1pdyn8FQYVEuqWrQ9ij/NN+7UQuEuc/fbtKGjZS3N0bJRaXLpcyYy/eruOJ+k YlF++w4JP8QQKon0GpQwIrE30QWbnoL82KC8u8SbQMfzUJKXIJ+I61bGUMQdhETAzEu4 66HNwFGE2SHQVLCbGztBt2c6Ejs09B/77jWiBHmtK2I6LgLi73gavPy2Pe6raT6jecW3 dysROR6TwmkDIH9r+6/v4l0DYRix0ZTDMdjlmCdb27deQoXADba3Qdxy8htRehagNsyf moM3I/VDth4cE87NGqZMQ+PuGBJoTtMkmT6x7KAOBbN/3PBSDU3fycnCOfiJmskrfr2h 2hwQ== X-Gm-Message-State: AOAM531r1ZNz2YpgejuGo2JG9XcxtTcl5a+tPBAoNRS3evVxpap9jk9U 9DV4lRHJZJ70qB5wt+0uP5Y= X-Google-Smtp-Source: ABdhPJwBIQt/L/k/aduacdDbcS7Xsuy1ptvmYy41XoYrrgkAcVfE/zDgbGKj6Ms235bc75jyiZRoow== X-Received: by 2002:a1c:63d7:: with SMTP id x206mr18804956wmb.34.1606038965656; Sun, 22 Nov 2020 01:56:05 -0800 (PST) Received: from localhost.localdomain (196.red-83-40-48.dynamicip.rima-tde.net. [83.40.48.196]) by smtp.gmail.com with ESMTPSA id p21sm10593570wma.41.2020.11.22.01.56.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Nov 2020 01:56:05 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, linux-clk@vger.kernel.org, evicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name Subject: [PATCH v4 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Date: Sun, 22 Nov 2020 10:55:55 +0100 Message-Id: <20201122095556.21597-6-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201122095556.21597-1-sergio.paracuellos@gmail.com> References: <20201122095556.21597-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 6 +++--- drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index ca0ac607b0f3..5d74fc1c96ac 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void) void __init ralink_of_remap(void) { - rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); - rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); + rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); + rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); if (!rt_sysc_membase || !rt_memc_membase) panic("Failed to remap core resources"); @@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) { name = "MT7621"; - soc_info->compatible = "mtk,mt7621-soc"; + soc_info->compatible = "mediatek,mt7621-soc"; } else { panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1); } diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 35cfda8f6faf..8fc311703beb 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -56,7 +56,7 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc", "syscon"; + compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; pll: pll { @@ -69,7 +69,7 @@ pll: pll { }; wdt: wdt@100 { - compatible = "mtk,mt7621-wdt"; + compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; }; @@ -125,17 +125,17 @@ i2s: i2s@a00 { }; memc: memc@5000 { - compatible = "mtk,mt7621-memc"; + compatible = "mediatek,mt7621-memc"; reg = <0x5000 0x1000>; }; cpc: cpc@1fbf0000 { - compatible = "mtk,mt7621-cpc"; + compatible = "mediatek,mt7621-cpc"; reg = <0x1fbf0000 0x8000>; }; mc: mc@1fbf8000 { - compatible = "mtk,mt7621-mc"; + compatible = "mediatek,mt7621-mc"; reg = <0x1fbf8000 0x8000>; }; @@ -368,7 +368,7 @@ timer { nand: nand@1e003000 { status = "disabled"; - compatible = "mtk,mt7621-nand"; + compatible = "mediatek,mt7621-nand"; bank-width = <2>; reg = <0x1e003000 0x800 0x1e003800 0x800>; From patchwork Sun Nov 22 09:55:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11923829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EBB9C5519F for ; Sun, 22 Nov 2020 09:56:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E24342224F for ; Sun, 22 Nov 2020 09:56:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QM/vOEu8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727685AbgKVJ4M (ORCPT ); Sun, 22 Nov 2020 04:56:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727517AbgKVJ4I (ORCPT ); Sun, 22 Nov 2020 04:56:08 -0500 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 262A1C0613D3; Sun, 22 Nov 2020 01:56:08 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id 1so14468730wme.3; Sun, 22 Nov 2020 01:56:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g0CHHJRFLkJgpWDc0kWpwLPadBEpgRbUEt1rTCDH2OM=; b=QM/vOEu84chd8mToZdajKu9RssxQXHCnUjUoXlPNMo+GlfRh3Q/dFonAVhdhnK4/en lMWOn/Q9Dj1HpQmmEj9RVFWzBYOpUj0ZcdaCheQas1lK2Gc3kYFhomBnbJgAXdAZOZfS Xuk4tmaIjT0X8y9urRS4vkvm7BhOTBUwWZtVB/RY5Pcpr9FqtwTezSvT/2yWYQbeSHS3 cuiklLs+HhdI2Awk5hDCcuKakSTCDy9J+fp/1X/OqP4+uYBbAp6h9SpDe3FV5LphwoK9 ED0HWdQJxbv32DJtVh9L3OX0sAYkefqzA2k8iDF463vLzl2OpozpkiMemYSIVRa110aH lQzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g0CHHJRFLkJgpWDc0kWpwLPadBEpgRbUEt1rTCDH2OM=; b=sn5hpSi4FCU3y1s2UfesaK/s1W5+WrmNcOUh0x6vQKcAPzoMySGxC2B5fmqFEl3RAZ UkQP5QoqcSTecs9FgS7MCg9BilLXZS8WJ/Dcujw5AR3hL+GyDUnB929cGmiocwUTr3iV Xb4S4OAcM5coPmfgxjoG0dh+OCtyb0wUs981HUoMUDNJR+16oQxnNeo82wNKN2fRocO5 I6jTwyiodDWTVe7s4wkniKEFIGPfA1CDAFcuWuBzuylo47yMVDIq/4LNOUAMh/DxraCz jd0cTHNxetpnbdPh+haVw5lQEXh2xYlmM02lqINcTs3uTwmjy6FTQVsMHfxvXNsuHFm1 KdDg== X-Gm-Message-State: AOAM5337jkmrDksbpRxwlhJAPzftq22gq1Wc0zLuuFy8obyP+1Y0PYxc BQBYa+X4U+GTf9JDKl7p7J0= X-Google-Smtp-Source: ABdhPJxp3A0DQalRpG59cJRBY8DqpvXBtw/5bNQayIpkHdNJ42AqfdelkZyrvHAVKpsKqC9PR2ya2g== X-Received: by 2002:a05:600c:2159:: with SMTP id v25mr6450376wml.155.1606038966972; Sun, 22 Nov 2020 01:56:06 -0800 (PST) Received: from localhost.localdomain (196.red-83-40-48.dynamicip.rima-tde.net. [83.40.48.196]) by smtp.gmail.com with ESMTPSA id p21sm10593570wma.41.2020.11.22.01.56.05 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Nov 2020 01:56:06 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, linux-clk@vger.kernel.org, evicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name Subject: [PATCH v4 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Date: Sun, 22 Nov 2020 10:55:56 +0100 Message-Id: <20201122095556.21597-7-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201122095556.21597-1-sergio.paracuellos@gmail.com> References: <20201122095556.21597-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f1f088a29bc2..30822ad6837c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11142,6 +11142,12 @@ L: linux-wireless@vger.kernel.org S: Maintained F: drivers/net/wireless/mediatek/mt7601u/ +MEDIATEK MT7621 CLOCK DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml +F: drivers/clk/ralink/clk-mt7621.c + MEDIATEK MT7621/28/88 I2C DRIVER M: Stefan Roese L: linux-i2c@vger.kernel.org