From patchwork Tue Jul 31 22:44:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10551505 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B250E96FA for ; Tue, 31 Jul 2018 22:44:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A261429600 for ; Tue, 31 Jul 2018 22:44:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 964922B329; Tue, 31 Jul 2018 22:44:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D08BB2B326 for ; Tue, 31 Jul 2018 22:44:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732718AbeHAA1S (ORCPT ); Tue, 31 Jul 2018 20:27:18 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35952 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732563AbeHAA1R (ORCPT ); Tue, 31 Jul 2018 20:27:17 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D7DF060714; Tue, 31 Jul 2018 22:44:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533077084; bh=hIikZFeJwSAsQuu13Jv6oMfWXL41xeEyjfDNEyH8N4k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BIBKZuEvdwHQIYT11bxSP0ihyzz/4JvPwewu+zGs2k5HreAFlg5rvHj3s5cLREtpX GvGQvLSEeey4FSF3F7OKFN11G2SlCeq897Kdy0ntq3iAd/fsw4VAE3gjR3r1D2BO4U HTIqStlyIaWQTIVZ0OdFPBgsGl2XAynUnLJGz0VM= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BF05D60481; Tue, 31 Jul 2018 22:44:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533077083; bh=hIikZFeJwSAsQuu13Jv6oMfWXL41xeEyjfDNEyH8N4k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BebyPh2A768cftGd9S+fRmauVhybm6jQyV1vMRt6UKFqneu53gWxb7z3WMpbLO4Ga zhDMwymygvI6Cvloka/cOFgzXTG0tXmavmgw3cnkjxshvNPcHBIxlOwtaO2pYAm0CL paV3W9xy4PMbqD6Af+sxQhaQauxsYXZ5h3tt2+3w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BF05D60481 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, sboyd@chromium.org, evgreen@chromium.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, Lina Iyer Subject: [PATCH RFC 1/4] drivers: pinctrl: qcom: add wakeup capability to GPIO Date: Tue, 31 Jul 2018 16:44:18 -0600 Message-Id: <20180731224421.29062-2-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180731224421.29062-1-ilina@codeaurora.org> References: <20180731224421.29062-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on domain can wakeup the SoC, when interrupts and GPIOs are routed to the its interrupt controller. Select GPIOs that are deemed wakeup capable are routed to specific PDC pins. The PDC wakes up the GIC and replays the interrupt at the GIC and the interrupt handler for the GPIO is invoked. Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC IRQ when the GPIO's IRQ is enabled. Signed-off-by: Lina Iyer --- drivers/pinctrl/qcom/pinctrl-msm.c | 163 +++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 14 +++ 2 files changed, 177 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 0e22f52b2a19..39c3934712f7 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -71,6 +71,13 @@ struct msm_pinctrl { const struct msm_pinctrl_soc_data *soc; void __iomem *regs; + struct list_head pdc_irqs; +}; + +struct wakeup_gpio_irq_map { + struct list_head list; + unsigned gpio; + unsigned pdc_irq; }; static int msm_get_groups_count(struct pinctrl_dev *pctldev) @@ -558,6 +565,39 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) #define msm_gpio_dbg_show NULL #endif +static int msm_gpio_get_pdc_pin(struct msm_pinctrl *pctrl, unsigned hwirq) +{ + struct msm_pinctrl_pdc_map *map = pctrl->soc->pdc_map; + int i; + + for (i = 0; i < pctrl->soc->npdc_pins; i++) { + if (map[i].hwirq == hwirq) + return map[i].pdc_pin; + } + + return -ENOTCONN; +} + +static struct irq_data *msm_get_pdc_irq_data(struct irq_data *d) +{ + struct wakeup_gpio_irq_map *p; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct irq_data *data = NULL; + unsigned long flags; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + list_for_each_entry(p, &pctrl->pdc_irqs, list) { + if (p->gpio == d->hwirq) { + data = irq_get_irq_data(p->pdc_irq); + break; + } + } + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return data; +} + static const struct gpio_chip msm_gpio_template = { .direction_input = msm_gpio_direction_input, .direction_output = msm_gpio_direction_output, @@ -687,6 +727,11 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) const struct msm_pingroup *g; unsigned long flags; u32 val; + struct irq_data *pdc_irqd = msm_get_pdc_irq_data(d); + + // TODO: Lock PDC irq chip and set type? + if (pdc_irqd) + pdc_irqd->chip->irq_set_type(pdc_irqd, type); g = &pctrl->soc->groups[d->hwirq]; @@ -779,9 +824,13 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; + struct irq_data *pdc_irqd = msm_get_pdc_irq_data(d); raw_spin_lock_irqsave(&pctrl->lock, flags); + if (pdc_irqd) + irq_set_irq_wake(pdc_irqd->irq, on); + irq_set_irq_wake(pctrl->irq, on); raw_spin_unlock_irqrestore(&pctrl->lock, flags); @@ -863,6 +912,117 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; } +static irqreturn_t wake_irq_gpio_handler(int irq, void *data) +{ + struct irq_data *irqd = data; + struct irq_desc *desc = irq_data_to_desc(irqd); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + int irq_pin = irq_find_mapping(gc->irq.domain, irqd->hwirq); + + chained_irq_enter(chip, desc); + generic_handle_irq(irq_pin); + chained_irq_exit(chip, desc); + + return IRQ_HANDLED; +} + +static int msm_gpio_pdc_pin_request(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct platform_device *pdev = to_platform_device(pctrl->dev); + unsigned pin, npins, irq; + struct wakeup_gpio_irq_map *p; + unsigned long flags, trigger; + const char *pin_name; + int i, ret; + + pin = msm_gpio_get_pdc_pin(pctrl, d->hwirq); + if (pin < 0) + return 0; + + npins = platform_irq_count(pdev); + if (npins <= 0) + return npins; + + for (i = 0; i < npins; i++) { + irq = platform_get_irq(pdev, i); + if (irq >= 0 && pin == irq_get_irq_data(irq)->hwirq) + break; + } + if (i == npins) + return 0; + + pin_name = kasprintf(GFP_KERNEL, "gpio-%lu", d->hwirq); + if (!pin_name) + return -ENOMEM; + + trigger = irqd_get_trigger_type(d) | IRQF_ONESHOT | IRQF_NO_SUSPEND; + ret = request_irq(irq, wake_irq_gpio_handler, trigger, pin_name, d); + if (ret) { + pr_warn("GPIO-%lu could not be set up as wakeup", d->hwirq); + return ret; + } + + p = kzalloc(sizeof(p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + p->pdc_irq = irq; + p->gpio = d->hwirq; + raw_spin_lock_irqsave(&pctrl->lock, flags); + list_add(&p->list, &pctrl->pdc_irqs); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_pdc_pin_release(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct wakeup_gpio_irq_map *p, *n, *t = NULL; + unsigned long flags; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + list_for_each_entry_safe(p, n, &pctrl->pdc_irqs, list) { + if (p->gpio == d->hwirq) { + list_del(&p->list); + t = p; + break; + } + } + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + if (t) { + free_irq(t->pdc_irq, NULL); + kfree(t); + } + + return 0; +} + +static int msm_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { + dev_err(gc->parent,"unable to lock HW IRQ %lu for IRQ\n", + irqd_to_hwirq(d)); + return -EINVAL; + } + + return msm_gpio_pdc_pin_request(d); +} + +static void msm_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + msm_gpio_pdc_pin_release(d); + gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); +} + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; @@ -887,6 +1047,9 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; + pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; + pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + INIT_LIST_HEAD(&pctrl->pdc_irqs); ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 9b9feea540ff..5b7f3160affe 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -97,6 +97,16 @@ struct msm_pingroup { unsigned intr_detection_width:5; }; +/** + * struct msm_pinctrl_pdc_map - Map GPIOs to PDC pins on RPMH based SoCs + * @hwirq: The GPIO that is mapped. + * @pdc_pin: The PDC pin to with the GPIO IRQ line is routed. + */ +struct msm_pinctrl_pdc_map { + u32 hwirq; + u32 pdc_pin; +}; + /** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. @@ -107,6 +117,8 @@ struct msm_pingroup { * @ngroups: The numbmer of entries in @groups. * @ngpio: The number of pingroups the driver should expose as GPIOs. * @pull_no_keeper: The SoC does not support keeper bias. + * @pdc_map: The map of GPIOs to the always-on PDC interrupt lines. + * @npdc_pins: The number of GPIOs mapped to the PDC pins in @pdc_map. */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -117,6 +129,8 @@ struct msm_pinctrl_soc_data { unsigned ngroups; unsigned ngpios; bool pull_no_keeper; + struct msm_pinctrl_pdc_map *pdc_map; + unsigned npdc_pins; }; int msm_pinctrl_probe(struct platform_device *pdev, From patchwork Tue Jul 31 22:44:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10551511 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A24513B8 for ; Tue, 31 Jul 2018 22:45:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A81C29600 for ; Tue, 31 Jul 2018 22:45:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1CF942B329; Tue, 31 Jul 2018 22:45:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B53E129600 for ; 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Tue, 31 Jul 2018 22:44:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533077084; bh=8eAHQ1vLx6Z/tpcxc68++JtizbhnvsGaa4M4kyZn/V8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jErrDCgCXdyQNWfxEHfyb9pSv9s03z4UThuPkd+0X9oGaAjwgcxrpifuM74ZKoHZ7 DZHKChXfo3JXKJCRomvVo/68II1PQZRj9pS0v6wcLUHIUhlpBiDa3u7ffPCxKdoO9p gHydDCH+NGSp7yqqPwZ3QMHEszTWqJsro+0dGS2A= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E44D9606AC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, sboyd@chromium.org, evgreen@chromium.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, Lina Iyer Subject: [PATCH RFC 2/4] drivers: pinctrl: qcom: add wakeup gpio map for sdm845 Date: Tue, 31 Jul 2018 16:44:19 -0600 Message-Id: <20180731224421.29062-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180731224421.29062-1-ilina@codeaurora.org> References: <20180731224421.29062-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add GPIO to PDC pin map for the SDM845 SoC. Signed-off-by: Lina Iyer --- drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 2ab7a8885757..e93660922dc2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1277,6 +1277,80 @@ static const struct msm_pingroup sdm845_groups[] = { UFS_RESET(ufs_reset, 0x99f000), }; +static struct msm_pinctrl_pdc_map sdm845_wakeup_gpios[] = { + {1, 30}, + {3, 31}, + {5, 32}, + {10, 33}, + {11, 34}, + {20, 35}, + {22, 36}, + {24, 37}, + {26, 38}, + {30, 39}, + {32, 41}, + {34, 42}, + {36, 43}, + {37, 44}, + {38, 45}, + {39, 46}, + {40, 47}, + {43, 49}, + {44, 50}, + {46, 51}, + {48, 52}, + {52, 54}, + {53, 55}, + {54, 56}, + {56, 57}, + {57, 58}, + {58, 59}, + {59, 60}, + {60, 61}, + {61, 62}, + {62, 63}, + {63, 64}, + {64, 65}, + {66, 66}, + {68, 67}, + {71, 68}, + {73, 69}, + {77, 70}, + {78, 71}, + {79, 72}, + {80, 73}, + {84, 74}, + {85, 75}, + {86, 76}, + {88, 77}, + {91, 79}, + {92, 80}, + {95, 81}, + {96, 82}, + {97, 83}, + {101, 84}, + {103, 85}, + {104, 86}, + {115, 90}, + {116, 91}, + {117, 92}, + {118, 93}, + {119, 94}, + {120, 95}, + {121, 96}, + {122, 97}, + {123, 98}, + {124, 99}, + {125, 100}, + {127, 102}, + {128, 103}, + {129, 104}, + {130, 105}, + {132, 106}, + {133, 107}, + {145, 108}, +}; + static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .pins = sdm845_pins, .npins = ARRAY_SIZE(sdm845_pins), @@ -1285,6 +1359,8 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), .ngpios = 150, + .pdc_map = sdm845_wakeup_gpios, + .npdc_pins = ARRAY_SIZE(sdm845_wakeup_gpios), }; static int sdm845_pinctrl_probe(struct platform_device *pdev) From patchwork Tue Jul 31 22:44:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10551509 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76E30139A for ; Tue, 31 Jul 2018 22:45:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 678EE29600 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, sboyd@chromium.org, evgreen@chromium.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, Lina Iyer Subject: [PATCH RFC 3/4] arm64: dts: msm: add PDC device bindings for sdm845 Date: Tue, 31 Jul 2018 16:44:20 -0600 Message-Id: <20180731224421.29062-4-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180731224421.29062-1-ilina@codeaurora.org> References: <20180731224421.29062-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PDC interrupt controller device bindings for SDM845. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2acc17ce1a9c..8ccce42885c1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1213,6 +1213,15 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + timer@17c90000 { #address-cells = <1>; #size-cells = <1>; From patchwork Tue Jul 31 22:44:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10551507 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 687BD13BB for ; Tue, 31 Jul 2018 22:44:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5929D29600 for ; Tue, 31 Jul 2018 22:44:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D4102B329; Tue, 31 Jul 2018 22:44:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF21929600 for ; Tue, 31 Jul 2018 22:44:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732788AbeHAA1U (ORCPT ); Tue, 31 Jul 2018 20:27:20 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36202 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732701AbeHAA1T (ORCPT ); Tue, 31 Jul 2018 20:27:19 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C7D17602D7; Tue, 31 Jul 2018 22:44:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533077087; bh=CkVqqPXhxoYUJzX4cYejKdu34f63CVroviRU9raEtOI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QINk+XX/cck8c3xhvYK7V/qeTMw28dtR1ABzoLVgbjxGYxY1bRXk41MWHlTUp5N+5 HMlpQA5UDD8wdN0FAoIWUfZSqGtVllKU3IFgvkEwNiqnDkBlcaV6uD0vC9Vw6HFCfp cvzlGYXgNVmshgqaVWKYEORISreikUwkZrlJwzQU= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2F42E60B7A; Tue, 31 Jul 2018 22:44:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533077087; bh=CkVqqPXhxoYUJzX4cYejKdu34f63CVroviRU9raEtOI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QINk+XX/cck8c3xhvYK7V/qeTMw28dtR1ABzoLVgbjxGYxY1bRXk41MWHlTUp5N+5 HMlpQA5UDD8wdN0FAoIWUfZSqGtVllKU3IFgvkEwNiqnDkBlcaV6uD0vC9Vw6HFCfp cvzlGYXgNVmshgqaVWKYEORISreikUwkZrlJwzQU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2F42E60B7A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, sboyd@chromium.org, evgreen@chromium.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, Lina Iyer Subject: [PATCH RFC 4/4] arm64: dts: qcom: add wake up interrupts for GPIOs Date: Tue, 31 Jul 2018 16:44:21 -0600 Message-Id: <20180731224421.29062-5-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180731224421.29062-1-ilina@codeaurora.org> References: <20180731224421.29062-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GPIOs that are wakeup capable have interrupt lines that are routed to the always-on interrupt controller (PDC) in parallel to the pinctrl. The interrupts listed here are the wake up lines corresponding to GPIOs. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8ccce42885c1..96ef18ced85b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -720,6 +720,75 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts-extended = <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 32 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 36 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 37 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 38 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 39 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 41 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 42 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 43 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 44 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 45 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 49 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 52 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 54 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 56 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 57 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 58 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 59 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 60 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 61 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 62 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 63 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 64 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 65 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 66 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 67 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 69 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 70 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 71 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 72 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 73 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 74 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 75 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 79 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 80 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 81 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 82 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 83 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 84 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 85 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 86 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 91 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 95 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 97 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 98 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 99 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 100 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 102 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 103 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 104 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 105 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 106 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 107 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 108 IRQ_TYPE_LEVEL_HIGH>; qup_i2c0_default: qup-i2c0-default { pinmux {