From patchwork Wed Nov 25 17:26:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11931957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5ECDC56202 for ; Wed, 25 Nov 2020 17:27:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80D032158C for ; Wed, 25 Nov 2020 17:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730695AbgKYR1T (ORCPT ); Wed, 25 Nov 2020 12:27:19 -0500 Received: from out28-122.mail.aliyun.com ([115.124.28.122]:38094 "EHLO out28-122.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732764AbgKYR1S (ORCPT ); Wed, 25 Nov 2020 12:27:18 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.09484112|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0808659-0.00140225-0.917732;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047212;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=13;RT=13;SR=0;TI=SMTPD_---.J.BPrxs_1606325224; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.J.BPrxs_1606325224) by smtp.aliyun-inc.com(10.147.41.137); Thu, 26 Nov 2020 01:27:12 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: sboyd@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com, paul@crapouillou.net Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, yanfei.li@ingenic.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 1/4] clk: JZ4780: Add function for disable the second core. Date: Thu, 26 Nov 2020 01:26:15 +0800 Message-Id: <20201125172618.112707-2-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> References: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add "jz4780_core1_disable()" for disable the second core of JZ4780, prepare for later commits. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil --- drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index 0268d23..dcca74e 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw) return 0; } +static void jz4780_core1_disable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + unsigned long flags; + u32 lcr, clkgr1; + + spin_lock_irqsave(&cgu->lock, flags); + + lcr = readl(cgu->base + CGU_REG_LCR); + lcr |= LCR_PD_SCPU; + writel(lcr, cgu->base + CGU_REG_LCR); + + clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); + clkgr1 |= CLKGR1_CORE1; + writel(clkgr1, cgu->base + CGU_REG_CLKGR1); + + spin_unlock_irqrestore(&cgu->lock, flags); +} + static const struct clk_ops jz4780_core1_ops = { .enable = jz4780_core1_enable, + .disable = jz4780_core1_disable, }; static const s8 pll_od_encoding[16] = { From patchwork Wed Nov 25 17:26:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11931961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E239BC64E90 for ; Wed, 25 Nov 2020 17:27:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A17D0206D9 for ; Wed, 25 Nov 2020 17:27:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732189AbgKYR1R (ORCPT ); Wed, 25 Nov 2020 12:27:17 -0500 Received: from out28-172.mail.aliyun.com ([115.124.28.172]:33115 "EHLO out28-172.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732765AbgKYR1Q (ORCPT ); Wed, 25 Nov 2020 12:27:16 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1504881|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.00850855-0.00378725-0.987704;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047190;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=13;RT=13;SR=0;TI=SMTPD_---.J.BPrxs_1606325224; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.J.BPrxs_1606325224) by smtp.aliyun-inc.com(10.147.41.137); Thu, 26 Nov 2020 01:27:13 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: sboyd@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com, paul@crapouillou.net Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, yanfei.li@ingenic.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 2/4] dt-bindings: clock: Add missing clocks for Ingenic SoCs. Date: Thu, 26 Nov 2020 01:26:16 +0800 Message-Id: <20201125172618.112707-3-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> References: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add CIM, AIC, DMIC clocks bindings for the X1000 SoC, and CIM, AIC, DMIC, I2S clocks for the X1830 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Acked-by: Rob Herring --- include/dt-bindings/clock/x1000-cgu.h | 3 +++ include/dt-bindings/clock/x1830-cgu.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index f187e07..fa92257 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -50,5 +50,8 @@ #define X1000_CLK_PDMA 35 #define X1000_CLK_EXCLK_DIV512 36 #define X1000_CLK_RTC 37 +#define X1000_CLK_CIM 38 +#define X1000_CLK_AIC 39 +#define X1000_CLK_DMIC 40 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h index 8845537..3732507 100644 --- a/include/dt-bindings/clock/x1830-cgu.h +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -53,5 +53,9 @@ #define X1830_CLK_OST 38 #define X1830_CLK_EXCLK_DIV512 39 #define X1830_CLK_RTC 40 +#define X1830_CLK_CIM 41 +#define X1830_CLK_AIC 42 +#define X1830_CLK_DMIC 43 +#define X1830_CLK_I2S 44 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ From patchwork Wed Nov 25 17:26:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11931959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E097C6379D for ; Wed, 25 Nov 2020 17:27:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04865221FD for ; Wed, 25 Nov 2020 17:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731413AbgKYR1X (ORCPT ); Wed, 25 Nov 2020 12:27:23 -0500 Received: from out28-172.mail.aliyun.com ([115.124.28.172]:51470 "EHLO out28-172.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732774AbgKYR1T (ORCPT ); Wed, 25 Nov 2020 12:27:19 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436282|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.00371057-1.20985e-05-0.996277;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047203;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=13;RT=13;SR=0;TI=SMTPD_---.J.BPrxs_1606325224; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.J.BPrxs_1606325224) by smtp.aliyun-inc.com(10.147.41.137); Thu, 26 Nov 2020 01:27:14 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: sboyd@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com, paul@crapouillou.net Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, yanfei.li@ingenic.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 3/4] clk: Ingenic: Add missing clocks for Ingenic SoCs. Date: Thu, 26 Nov 2020 01:26:17 +0800 Message-Id: <20201125172618.112707-4-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> References: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add CIM, AIC, DMIC clocks for the X1000 SoC, and CIM, AIC, DMIC, I2S clocks for the X1830 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- drivers/clk/ingenic/x1000-cgu.c | 19 ++++ drivers/clk/ingenic/x1830-cgu.c | 189 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 9aa20b5..d340bcd 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -360,6 +360,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .mux = { CGU_REG_SSICDR, 30, 1 }, }, + [X1000_CLK_CIM] = { + "cim", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .mux = { CGU_REG_CIMCDR, 31, 1 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, 29, 28, 27 }, + }, + [X1000_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { X1000_CLK_EXCLK }, @@ -411,6 +418,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 9 }, }, + [X1000_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, @@ -429,6 +442,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 16 }, }, + [X1000_CLK_DMIC] = { + "dmic", CGU_CLK_GATE, + .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + [X1000_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index 950aee2..e76e82c 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -52,6 +52,15 @@ #define USBPCR_SIDDQ BIT(21) #define USBPCR_OTG_DISABLE BIT(20) +/* bits within the I2SCDR register */ +#define I2SCDR_I2PCS_SHIFT 30 +#define I2SCDR_I2PCS_MASK (0x3 << I2SCDR_I2PCS_SHIFT) +#define I2SCDR_I2SDIV_M_SHIFT 20 +#define I2SCDR_I2SDIV_M_MASK (0x1ff << I2SCDR_I2SDIV_M_SHIFT) +#define I2SCDR_I2SDIV_N_SHIFT 0 +#define I2SCDR_I2SDIV_N_MASK (0xfffff << I2SCDR_I2SDIV_N_SHIFT) +#define I2SCDR_CE_I2S BIT(29) + static struct ingenic_cgu *cgu; static int x1830_usb_phy_enable(struct clk_hw *hw) @@ -89,6 +98,157 @@ static const struct clk_ops x1830_otg_phy_ops = { .is_enabled = x1830_usb_phy_is_enabled, }; +static u8 x1830_i2s_get_parent(struct clk_hw *hw) +{ + u32 i2scdr; + + i2scdr = readl(cgu->base + CGU_REG_I2SCDR); + + return (i2scdr & I2SCDR_I2PCS_MASK) >> I2SCDR_I2PCS_SHIFT; +} + +static int x1830_i2s_set_parent(struct clk_hw *hw, u8 idx) +{ + writel(idx << I2SCDR_I2PCS_SHIFT, cgu->base + CGU_REG_I2SCDR); + + return 0; +} + +static unsigned long x1830_i2s_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned m, n; + u32 i2scdr; + + i2scdr = readl(cgu->base + CGU_REG_I2SCDR); + + m = (i2scdr & I2SCDR_I2SDIV_M_MASK) >> I2SCDR_I2SDIV_M_SHIFT; + n = (i2scdr & I2SCDR_I2SDIV_N_MASK) >> I2SCDR_I2SDIV_N_SHIFT; + + return div_u64((u64)parent_rate * m, n); +} + +static unsigned long x1830_i2s_calc(unsigned long rate, unsigned long parent_rate, + unsigned *pm, unsigned *pn) +{ + u64 curr_delta, curr_m, curr_n, delta, m, n; + + if ((parent_rate % rate == 0) && ((parent_rate / rate) > 1)) { + m = 1; + n = parent_rate / rate; + goto out; + } + + delta = rate; + + /* + * The length of M is 9 bits, its value must be between 1 and 511. + * The length of N is 20 bits, its value must be between 2 and 1048575, + * and must not be less than 2 times of the value of M. + */ + for (curr_m = 511; curr_m >= 1; curr_m--) { + curr_n = parent_rate * curr_m; + curr_delta = do_div(curr_n, rate); + + if (curr_n < 2 * curr_m || curr_n > 1048575) + continue; + + if (curr_delta == 0) + break; + + if (curr_delta < delta) { + m = curr_m; + n = curr_n; + delta = curr_delta; + } + } + +out: + if (pm) + *pm = m; + if (pn) + *pn = n; + + return div_u64((u64)parent_rate * m, n); +} + +static long x1830_i2s_round_rate(struct clk_hw *hw, unsigned long req_rate, + unsigned long *prate) +{ + return x1830_i2s_calc(req_rate, *prate, NULL, NULL); +} + +static int x1830_i2s_set_rate(struct clk_hw *hw, unsigned long req_rate, + unsigned long parent_rate) +{ + unsigned long rate; + unsigned m, n; + u32 ctl; + + /* + * The parent clock rate of I2S must not be lower than 2 times + * of the target clock rate. + */ + if (parent_rate < 2 * req_rate) + return -EINVAL; + + rate = x1830_i2s_calc(req_rate, parent_rate, &m, &n); + if (rate != req_rate) + pr_info("%s: request I2S rate %luHz, actual %luHz\n", __func__, + req_rate, rate); + + ctl = readl(cgu->base + CGU_REG_I2SCDR); + ctl &= ~I2SCDR_I2SDIV_M_MASK; + ctl |= m << I2SCDR_I2SDIV_M_SHIFT; + ctl &= ~I2SCDR_I2SDIV_N_MASK; + ctl |= n << I2SCDR_I2SDIV_N_SHIFT; + writel(ctl, cgu->base + CGU_REG_I2SCDR); + + return 0; +} + +static int x1830_i2s_enable(struct clk_hw *hw) +{ + u32 ctl; + + ctl = readl(cgu->base + CGU_REG_I2SCDR); + ctl |= I2SCDR_CE_I2S; + writel(ctl, cgu->base + CGU_REG_I2SCDR); + + return 0; +} + +static void x1830_i2s_disable(struct clk_hw *hw) +{ + u32 ctl; + + ctl = readl(cgu->base + CGU_REG_I2SCDR); + ctl &= ~I2SCDR_CE_I2S; + writel(ctl, cgu->base + CGU_REG_I2SCDR); +} + +static int x1830_i2s_is_enabled(struct clk_hw *hw) +{ + u32 ctl; + + ctl = readl(cgu->base + CGU_REG_I2SCDR); + + return !!(ctl & I2SCDR_CE_I2S); +} + +static const struct clk_ops x1830_i2s_ops = { + .get_parent = x1830_i2s_get_parent, + .set_parent = x1830_i2s_set_parent, + + .recalc_rate = x1830_i2s_recalc_rate, + .round_rate = x1830_i2s_round_rate, + .set_rate = x1830_i2s_set_rate, + + .enable = x1830_i2s_enable, + .disable = x1830_i2s_disable, + .is_enabled = x1830_i2s_is_enabled, +}; + static const s8 pll_od_encoding[64] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, -1, -1, -1, -1, -1, -1, -1, 0x4, @@ -201,7 +361,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { }, }, - /* Custom (SoC-specific) OTG PHY */ + /* Custom (SoC-specific) */ [X1830_CLK_OTGPHY] = { "otg_phy", CGU_CLK_CUSTOM, @@ -209,6 +369,13 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .custom = { &x1830_otg_phy_ops }, }, + [X1830_CLK_I2S] = { + "i2s", CGU_CLK_CUSTOM, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .custom = { &x1830_i2s_ops }, + }, + /* Muxes & dividers */ [X1830_CLK_SCLKA] = { @@ -329,6 +496,14 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .mux = { CGU_REG_SSICDR, 29, 1 }, }, + [X1830_CLK_CIM] = { + "cim", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_CIMCDR, 30, 2 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, 29, 28, 27 }, + }, + [X1830_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { X1830_CLK_EXCLK }, @@ -386,6 +561,18 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .gate = { CGU_REG_CLKGR0, 9 }, }, + [X1830_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 11 }, + }, + + [X1830_CLK_DMIC] = { + "dmic", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 12 }, + }, + [X1830_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, From patchwork Wed Nov 25 17:26:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11931963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C1D1C71156 for ; Wed, 25 Nov 2020 17:27:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0FB95206D9 for ; Wed, 25 Nov 2020 17:27:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732774AbgKYR10 (ORCPT ); Wed, 25 Nov 2020 12:27:26 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:45942 "EHLO out28-97.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731336AbgKYR1T (ORCPT ); Wed, 25 Nov 2020 12:27:19 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436293|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.0180627-0.000172114-0.981765;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047187;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=13;RT=13;SR=0;TI=SMTPD_---.J.BPrxs_1606325224; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.J.BPrxs_1606325224) by smtp.aliyun-inc.com(10.147.41.137); Thu, 26 Nov 2020 01:27:15 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: sboyd@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com, paul@crapouillou.net Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, yanfei.li@ingenic.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 4/4] clk: Ingenic: Fill unused bits in parents and reformat code. Date: Thu, 26 Nov 2020 01:26:18 +0800 Message-Id: <20201125172618.112707-5-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> References: <20201125172618.112707-1-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org 1.Fill unused bits in parents in jz4780-cgu.c, x1000-cgu.c, and x1830-cgu.c, these bits should be filled with -1. 2.Reformat code, add missing blank lines, remove unnecessary tabs, and align code. Signed-off-by: 周琰杰 (Zhou Yanjie) --- drivers/clk/ingenic/jz4780-cgu.c | 12 +++--- drivers/clk/ingenic/x1000-cgu.c | 20 +++++----- drivers/clk/ingenic/x1830-cgu.c | 83 ++++++++++++++++++++-------------------- 3 files changed, 60 insertions(+), 55 deletions(-) diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index dcca74e..1b61eaa 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -178,6 +178,7 @@ static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); spin_unlock_irqrestore(&cgu->lock, flags); + return 0; } @@ -188,6 +189,7 @@ static int jz4780_otg_phy_enable(struct clk_hw *hw) writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); + return 0; } @@ -215,9 +217,9 @@ static const struct clk_ops jz4780_otg_phy_ops = { .round_rate = jz4780_otg_phy_round_rate, .set_rate = jz4780_otg_phy_set_rate, - .enable = jz4780_otg_phy_enable, - .disable = jz4780_otg_phy_disable, - .is_enabled = jz4780_otg_phy_is_enabled, + .enable = jz4780_otg_phy_enable, + .disable = jz4780_otg_phy_disable, + .is_enabled = jz4780_otg_phy_is_enabled, }; static int jz4780_core1_enable(struct clk_hw *hw) @@ -544,13 +546,13 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, - .parents = { JZ4780_CLK_EXCLK }, + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .fixdiv = { 512 }, }, [JZ4780_CLK_RTC] = { "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK }, + .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK, -1, -1 }, .mux = { CGU_REG_OPCR, 2, 1}, }, diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index d340bcd..fe2e274 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -126,6 +126,7 @@ static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); spin_unlock_irqrestore(&cgu->lock, flags); + return 0; } @@ -136,6 +137,7 @@ static int x1000_usb_phy_enable(struct clk_hw *hw) writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); + return 0; } @@ -163,9 +165,9 @@ static const struct clk_ops x1000_otg_phy_ops = { .round_rate = x1000_otg_phy_round_rate, .set_rate = x1000_otg_phy_set_rate, - .enable = x1000_usb_phy_enable, - .disable = x1000_usb_phy_disable, - .is_enabled = x1000_usb_phy_is_enabled, + .enable = x1000_usb_phy_enable, + .disable = x1000_usb_phy_disable, + .is_enabled = x1000_usb_phy_is_enabled, }; static const s8 pll_od_encoding[8] = { @@ -298,7 +300,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_MAC] = { "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, .mux = { CGU_REG_MACCDR, 31, 1 }, .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 25 }, @@ -306,7 +308,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_LCD] = { "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, .mux = { CGU_REG_LPCDR, 31, 1 }, .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, .gate = { CGU_REG_CLKGR, 23 }, @@ -314,7 +316,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, .mux = { CGU_REG_MSC0CDR, 31, 1 }, }, @@ -350,7 +352,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_SSIPLL_DIV2] = { "ssi_pll_div2", CGU_CLK_FIXDIV, - .parents = { X1000_CLK_SSIPLL }, + .parents = { X1000_CLK_SSIPLL, -1, -1, -1 }, .fixdiv = { 2 }, }, @@ -369,13 +371,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, - .parents = { X1000_CLK_EXCLK }, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .fixdiv = { 512 }, }, [X1000_CLK_RTC] = { "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK }, + .parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK, -1, -1 }, .mux = { CGU_REG_OPCR, 2, 1}, .gate = { CGU_REG_CLKGR, 27 }, }, diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index e76e82c..4d6cca5 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -15,51 +15,51 @@ #include "pm.h" /* CGU register offsets */ -#define CGU_REG_CPCCR 0x00 -#define CGU_REG_CPPCR 0x0c -#define CGU_REG_APLL 0x10 -#define CGU_REG_MPLL 0x14 -#define CGU_REG_CLKGR0 0x20 -#define CGU_REG_OPCR 0x24 -#define CGU_REG_CLKGR1 0x28 -#define CGU_REG_DDRCDR 0x2c -#define CGU_REG_USBPCR 0x3c -#define CGU_REG_USBRDT 0x40 -#define CGU_REG_USBVBFIL 0x44 -#define CGU_REG_USBPCR1 0x48 -#define CGU_REG_MACCDR 0x54 -#define CGU_REG_EPLL 0x58 -#define CGU_REG_I2SCDR 0x60 -#define CGU_REG_LPCDR 0x64 -#define CGU_REG_MSC0CDR 0x68 -#define CGU_REG_I2SCDR1 0x70 -#define CGU_REG_SSICDR 0x74 -#define CGU_REG_CIMCDR 0x7c -#define CGU_REG_MSC1CDR 0xa4 -#define CGU_REG_CMP_INTR 0xb0 -#define CGU_REG_CMP_INTRE 0xb4 -#define CGU_REG_DRCG 0xd0 -#define CGU_REG_CPCSR 0xd4 -#define CGU_REG_VPLL 0xe0 -#define CGU_REG_MACPHYC 0xe8 +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_CPPCR 0x0c +#define CGU_REG_APLL 0x10 +#define CGU_REG_MPLL 0x14 +#define CGU_REG_CLKGR0 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_CLKGR1 0x28 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBRDT 0x40 +#define CGU_REG_USBVBFIL 0x44 +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_MACCDR 0x54 +#define CGU_REG_EPLL 0x58 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_I2SCDR1 0x70 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7c +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_VPLL 0xe0 +#define CGU_REG_MACPHYC 0xe8 /* bits within the OPCR register */ -#define OPCR_GATE_USBPHYCLK BIT(23) -#define OPCR_SPENDN0 BIT(7) -#define OPCR_SPENDN1 BIT(6) +#define OPCR_GATE_USBPHYCLK BIT(23) +#define OPCR_SPENDN0 BIT(7) +#define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ -#define USBPCR_SIDDQ BIT(21) -#define USBPCR_OTG_DISABLE BIT(20) +#define USBPCR_SIDDQ BIT(21) +#define USBPCR_OTG_DISABLE BIT(20) /* bits within the I2SCDR register */ -#define I2SCDR_I2PCS_SHIFT 30 -#define I2SCDR_I2PCS_MASK (0x3 << I2SCDR_I2PCS_SHIFT) +#define I2SCDR_I2PCS_SHIFT 30 +#define I2SCDR_I2PCS_MASK (0x3 << I2SCDR_I2PCS_SHIFT) #define I2SCDR_I2SDIV_M_SHIFT 20 #define I2SCDR_I2SDIV_M_MASK (0x1ff << I2SCDR_I2SDIV_M_SHIFT) #define I2SCDR_I2SDIV_N_SHIFT 0 #define I2SCDR_I2SDIV_N_MASK (0xfffff << I2SCDR_I2SDIV_N_SHIFT) -#define I2SCDR_CE_I2S BIT(29) +#define I2SCDR_CE_I2S BIT(29) static struct ingenic_cgu *cgu; @@ -70,6 +70,7 @@ static int x1830_usb_phy_enable(struct clk_hw *hw) writel((readl(reg_opcr) | OPCR_SPENDN0) & ~OPCR_GATE_USBPHYCLK, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); + return 0; } @@ -93,9 +94,9 @@ static int x1830_usb_phy_is_enabled(struct clk_hw *hw) } static const struct clk_ops x1830_otg_phy_ops = { - .enable = x1830_usb_phy_enable, - .disable = x1830_usb_phy_disable, - .is_enabled = x1830_usb_phy_is_enabled, + .enable = x1830_usb_phy_enable, + .disable = x1830_usb_phy_disable, + .is_enabled = x1830_usb_phy_is_enabled, }; static u8 x1830_i2s_get_parent(struct clk_hw *hw) @@ -486,7 +487,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_SSIPLL_DIV2] = { "ssi_pll_div2", CGU_CLK_FIXDIV, - .parents = { X1830_CLK_SSIPLL }, + .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, .fixdiv = { 2 }, }, @@ -506,13 +507,13 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, - .parents = { X1830_CLK_EXCLK }, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .fixdiv = { 512 }, }, [X1830_CLK_RTC] = { "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK }, + .parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK, -1, -1 }, .mux = { CGU_REG_OPCR, 2, 1}, .gate = { CGU_REG_CLKGR0, 29 }, },