From patchwork Wed Nov 25 19:25:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11932099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F34D0C6379D for ; Wed, 25 Nov 2020 19:26:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 900192075A for ; Wed, 25 Nov 2020 19:26:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="hdVkoaKO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727939AbgKYT0F (ORCPT ); Wed, 25 Nov 2020 14:26:05 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4389 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727886AbgKYT0E (ORCPT ); Wed, 25 Nov 2020 14:26:04 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 25 Nov 2020 11:26:04 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 25 Nov 2020 19:26:02 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 25 Nov 2020 19:25:58 +0000 From: Vidya Sagar To: , , , , , , , , CC: , , , , , , Subject: [PATCH] PCI: tegra: Read "dbi" base address to program in application logic Date: Thu, 26 Nov 2020 00:55:54 +0530 Message-ID: <20201125192554.5401-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606332364; bh=JWEIVMl/77bu7Q+BVjyybEbxe5MdS6MrC/6uj772QPg=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:X-NVConfidentiality: MIME-Version:Content-Type; b=hdVkoaKOWf2K3iNdsk4GNjg9JAXIX8mjLhwUl9zs/cy3Ikza4uqq6GGvDckE8MqL4 YT466FnFMNDfAZL0b4vD/hEX7hTlcgcuU5Cv6na9guprzE7sLjE8tJtlFuLtVopIs2 azKxk7e0K3nHjYqtcG/4DaEjjNCtKEBKbVpRV8ltNrDIMmKtwU56l4fjRB6Eo1W287 Qhg3gOdyFEOyl3aq8WR/PK+HAvT6moyikB1xoCCNJK2Bpl7zaNbKRGRAGn54tYZQKb qIGyIbZt2LTZQ71wypNaX2s42xyGzSiVBjvvOEWOzfezWakLnQAOGvR67KfgxySl7Y kXEi27jy74+WA== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PCIe controller in Tegra194 requires the "dbi" region base address to be programmed in one of the application logic registers to enable CPU access to the "dbi" region. But, commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code") moved the code that reads the whereabouts of "dbi" region to the common code causing the existing code in pcie-tegra194.c file to program NULL in the application logic registers. This is causing null pointer dereference when the "dbi" registers are accessed. This issue is fixed by explicitly reading the "dbi" base address from DT node. Fixes: a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code") Signed-off-by: Vidya Sagar Tested-by: Thierry Reding Acked-by: Thierry Reding --- drivers/pci/controller/dwc/pcie-tegra194.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index fa54d9aaa430..ac2225175087 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1053,9 +1053,16 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) { + struct platform_device *pdev = to_platform_device(pcie->dev); struct device_node *np = pcie->dev->of_node; int ret; + pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + if (!pcie->dbi_res) { + dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); + return -ENODEV; + } + ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); if (ret < 0) { dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);