From patchwork Thu Nov 26 15:51:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11934285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 040C7C63798 for ; Thu, 26 Nov 2020 15:53:15 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F0D221D40 for ; Thu, 26 Nov 2020 15:53:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8F0D221D40 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.38695.71443 (Exim 4.92) (envelope-from ) id 1kiJZw-0004Cw-PY; Thu, 26 Nov 2020 15:53:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 38695.71443; Thu, 26 Nov 2020 15:53:04 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kiJZw-0004Cp-Lg; Thu, 26 Nov 2020 15:53:04 +0000 Received: by outflank-mailman (input) for mailman id 38695; Thu, 26 Nov 2020 15:53:03 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kiJZv-0004Ch-LO for xen-devel@lists.xenproject.org; Thu, 26 Nov 2020 15:53:03 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id d1e24fff-4259-4dc0-a40e-aafde6250990; Thu, 26 Nov 2020 15:53:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 923E131B; Thu, 26 Nov 2020 07:53:02 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C7A693F23F; Thu, 26 Nov 2020 07:53:01 -0800 (PST) Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kiJZv-0004Ch-LO for xen-devel@lists.xenproject.org; Thu, 26 Nov 2020 15:53:03 +0000 X-Inumbo-ID: d1e24fff-4259-4dc0-a40e-aafde6250990 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id d1e24fff-4259-4dc0-a40e-aafde6250990; Thu, 26 Nov 2020 15:53:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 923E131B; Thu, 26 Nov 2020 07:53:02 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C7A693F23F; Thu, 26 Nov 2020 07:53:01 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 1/7] xen/arm: Add ID registers and complete cpufinfo Date: Thu, 26 Nov 2020 15:51:03 +0000 Message-Id: <181f3157e2895498b09790d02555e5530adec6ad.1606317985.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add definition and entries in cpuinfo for ID registers introduced in newer Arm Architecture reference manual: - ID_PFR2: processor feature register 2 - ID_DFR1: debug feature register 1 - ID_MMFR4 and ID_MMFR5: Memory model feature registers 4 and 5 - ID_ISA6: ISA Feature register 6 Add more bitfield definitions in PFR fields of cpuinfo. Add MVFR2 register definition for aarch32. Add mvfr values in cpuinfo. Add some registers definition for arm64 in sysregs as some are not always know by compilers. Initialize the new values added in cpuinfo in identify_cpu during init. Signed-off-by: Bertrand Marquis --- xen/arch/arm/cpufeature.c | 16 ++++++++ xen/include/asm-arm/arm64/sysregs.h | 22 +++++++++++ xen/include/asm-arm/cpregs.h | 10 +++++ xen/include/asm-arm/cpufeature.h | 61 +++++++++++++++++++++++++---- 4 files changed, 101 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 44126dbf07..c0adf848c5 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -114,13 +114,17 @@ void identify_cpu(struct cpuinfo_arm *c) c->mm64.bits[0] = READ_SYSREG64(ID_AA64MMFR0_EL1); c->mm64.bits[1] = READ_SYSREG64(ID_AA64MMFR1_EL1); + c->mm64.bits[2] = READ_SYSREG64(ID_AA64MMFR2_EL1); c->isa64.bits[0] = READ_SYSREG64(ID_AA64ISAR0_EL1); c->isa64.bits[1] = READ_SYSREG64(ID_AA64ISAR1_EL1); + + c->zfr64.bits[0] = READ_SYSREG64(ID_AA64ZFR0_EL1); #endif c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); + c->pfr32.bits[2] = READ_SYSREG32(ID_PFR2_EL1); c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); @@ -130,6 +134,8 @@ void identify_cpu(struct cpuinfo_arm *c) c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); + c->mm32.bits[4] = READ_SYSREG32(ID_MMFR4_EL1); + c->mm32.bits[5] = READ_SYSREG32(ID_MMFR5_EL1); c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); c->isa32.bits[1] = READ_SYSREG32(ID_ISAR1_EL1); @@ -137,6 +143,16 @@ void identify_cpu(struct cpuinfo_arm *c) c->isa32.bits[3] = READ_SYSREG32(ID_ISAR3_EL1); c->isa32.bits[4] = READ_SYSREG32(ID_ISAR4_EL1); c->isa32.bits[5] = READ_SYSREG32(ID_ISAR5_EL1); + c->isa32.bits[6] = READ_SYSREG32(ID_ISAR6_EL1); + +#ifdef CONFIG_ARM_64 + c->mvfr.bits[0] = READ_SYSREG64(MVFR0_EL1); + c->mvfr.bits[1] = READ_SYSREG64(MVFR1_EL1); + c->mvfr.bits[2] = READ_SYSREG64(MVFR2_EL1); +#else + c->mvfr.bits[0] = READ_CP32(MVFR0); + c->mvfr.bits[1] = READ_CP32(MVFR1); +#endif } /* diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index c60029d38f..fd0b25b9c7 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -57,6 +57,28 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) +/* + * Define ID coprocessor registers if they are not + * already defined by the compiler. + * + * Values picked from linux kernel + */ +#ifndef ID_AA64MMFR2_EL1 +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#endif +#ifndef ID_PFR2_EL1 +#define ID_PFR2_EL1 S3_0_C0_C3_4 +#endif +#ifndef ID_MMFR5_EL1 +#define ID_MMFR5_EL1 S3_0_C0_C3_6 +#endif +#ifndef ID_ISAR6_EL1 +#define ID_ISAR6_EL1 S3_0_C0_C2_7 +#endif +#ifndef ID_AA64ZFR0_EL1 +#define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 +#endif + /* Access to system registers */ #define READ_SYSREG32(name) ((uint32_t)READ_SYSREG64(name)) diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 8fd344146e..aa8fc1d4a3 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -63,6 +63,7 @@ #define FPSID p10,7,c0,c0,0 /* Floating-Point System ID Register */ #define FPSCR p10,7,c1,c0,0 /* Floating-Point Status and Control Register */ #define MVFR0 p10,7,c7,c0,0 /* Media and VFP Feature Register 0 */ +#define MVFR1 p10,7,c6,c0,0 /* Media and VFP Feature Register 1 */ #define FPEXC p10,7,c8,c0,0 /* Floating-Point Exception Control Register */ #define FPINST p10,7,c9,c0,0 /* Floating-Point Instruction Register */ #define FPINST2 p10,7,c10,c0,0 /* Floating-point Instruction Register 2 */ @@ -108,18 +109,23 @@ #define MPIDR p15,0,c0,c0,5 /* Multiprocessor Affinity Register */ #define ID_PFR0 p15,0,c0,c1,0 /* Processor Feature Register 0 */ #define ID_PFR1 p15,0,c0,c1,1 /* Processor Feature Register 1 */ +#define ID_PFR2 p15,0,c0,c3,4 /* Processor Feature Register 2 */ #define ID_DFR0 p15,0,c0,c1,2 /* Debug Feature Register 0 */ +#define ID_DFR1 p15,0,c0,c3,5 /* Debug Feature Register 1 */ #define ID_AFR0 p15,0,c0,c1,3 /* Auxiliary Feature Register 0 */ #define ID_MMFR0 p15,0,c0,c1,4 /* Memory Model Feature Register 0 */ #define ID_MMFR1 p15,0,c0,c1,5 /* Memory Model Feature Register 1 */ #define ID_MMFR2 p15,0,c0,c1,6 /* Memory Model Feature Register 2 */ #define ID_MMFR3 p15,0,c0,c1,7 /* Memory Model Feature Register 3 */ +#define ID_MMFR4 p15,0,c0,c2,6 /* Memory Model Feature Register 4 */ +#define ID_MMFR5 p15,0,c0,c3,6 /* Memory Model Feature Register 5 */ #define ID_ISAR0 p15,0,c0,c2,0 /* ISA Feature Register 0 */ #define ID_ISAR1 p15,0,c0,c2,1 /* ISA Feature Register 1 */ #define ID_ISAR2 p15,0,c0,c2,2 /* ISA Feature Register 2 */ #define ID_ISAR3 p15,0,c0,c2,3 /* ISA Feature Register 3 */ #define ID_ISAR4 p15,0,c0,c2,4 /* ISA Feature Register 4 */ #define ID_ISAR5 p15,0,c0,c2,5 /* ISA Feature Register 5 */ +#define ID_ISAR6 p15,0,c0,c2,7 /* ISA Feature Register 6 */ #define CCSIDR p15,1,c0,c0,0 /* Cache Size ID Registers */ #define CLIDR p15,1,c0,c0,1 /* Cache Level ID Register */ #define CSSELR p15,2,c0,c0,0 /* Cache Size Selection Register */ @@ -318,12 +324,16 @@ #define ID_ISAR3_EL1 ID_ISAR3 #define ID_ISAR4_EL1 ID_ISAR4 #define ID_ISAR5_EL1 ID_ISAR5 +#define ID_ISAR6_EL1 ID_ISAR6 #define ID_MMFR0_EL1 ID_MMFR0 #define ID_MMFR1_EL1 ID_MMFR1 #define ID_MMFR2_EL1 ID_MMFR2 #define ID_MMFR3_EL1 ID_MMFR3 +#define ID_MMFR4_EL1 ID_MMFR4 +#define ID_MMFR5_EL1 ID_MMFR5 #define ID_PFR0_EL1 ID_PFR0 #define ID_PFR1_EL1 ID_PFR1 +#define ID_PFR2_EL1 ID_PFR2 #define IFSR32_EL2 IFSR #define MDCR_EL2 HDCR #define MIDR_EL1 MIDR diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index c7b5052992..1862c14e37 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -148,6 +148,7 @@ struct cpuinfo_arm { union { uint64_t bits[2]; struct { + /* PFR0 */ unsigned long el0:4; unsigned long el1:4; unsigned long el2:4; @@ -155,9 +156,23 @@ struct cpuinfo_arm { unsigned long fp:4; /* Floating Point */ unsigned long simd:4; /* Advanced SIMD */ unsigned long gic:4; /* GIC support */ - unsigned long __res0:28; + unsigned long ras:4; + unsigned long sve:4; + unsigned long sel2:4; + unsigned long mpam:4; + unsigned long amu:4; + unsigned long dit:4; + unsigned long __res0:4; unsigned long csv2:4; - unsigned long __res1:4; + unsigned long cvs3:4; + + /* PFR1 */ + unsigned long bt:4; + unsigned long ssbs:4; + unsigned long mte:4; + unsigned long ras_frac:4; + unsigned long mpam_frac:4; + unsigned long __res1:44; }; } pfr64; @@ -170,7 +185,7 @@ struct cpuinfo_arm { } aux64; union { - uint64_t bits[2]; + uint64_t bits[3]; struct { unsigned long pa_range:4; unsigned long asid_bits:4; @@ -190,6 +205,8 @@ struct cpuinfo_arm { unsigned long pan:4; unsigned long __res1:8; unsigned long __res2:32; + + unsigned long __res3:64; }; } mm64; @@ -197,6 +214,10 @@ struct cpuinfo_arm { uint64_t bits[2]; } isa64; + struct { + uint64_t bits[1]; + } zfr64; + #endif /* @@ -204,20 +225,33 @@ struct cpuinfo_arm { * when running in 32-bit mode. */ union { - uint32_t bits[2]; + uint32_t bits[3]; struct { + /* PFR0 */ unsigned long arm:4; unsigned long thumb:4; unsigned long jazelle:4; unsigned long thumbee:4; - unsigned long __res0:16; + unsigned long csv2:4; + unsigned long amu:4; + unsigned long dit:4; + unsigned long ras:4; + /* PFR1 */ unsigned long progmodel:4; unsigned long security:4; unsigned long mprofile:4; unsigned long virt:4; unsigned long gentimer:4; - unsigned long __res1:12; + unsigned long sec_frac:4; + unsigned long virt_frac:4; + unsigned long gic:4; + + /* PFR2 */ + unsigned long csv3:4; + unsigned long ssbs:4; + unsigned long ras_frac:4; + unsigned long __res2:20; }; } pfr32; @@ -230,12 +264,23 @@ struct cpuinfo_arm { } aux32; struct { - uint32_t bits[4]; + uint32_t bits[6]; } mm32; struct { - uint32_t bits[6]; + uint32_t bits[7]; } isa32; + +#ifdef CONFIG_ARM_64 + struct { + uint64_t bits[3]; + } mvfr; +#else + /* Only MVFR0 and MVFR1 exist on armv7 */ + struct { + uint32_t bits[2]; + } mvfr; +#endif }; extern struct cpuinfo_arm boot_cpu_data; From patchwork Thu Nov 26 15:51:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11934287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 830E9C63697 for ; Thu, 26 Nov 2020 15:53:18 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3831E21D40 for ; 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Thu, 26 Nov 2020 15:53:08 +0000 X-Inumbo-ID: 82f708c1-3d7d-41ff-933d-f670bfb3023d Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 82f708c1-3d7d-41ff-933d-f670bfb3023d; Thu, 26 Nov 2020 15:53:03 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 74EAD1516; Thu, 26 Nov 2020 07:53:03 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C5C943F23F; Thu, 26 Nov 2020 07:53:02 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 2/7] xen/arm: Add arm64 ID registers definitions Date: Thu, 26 Nov 2020 15:51:04 +0000 Message-Id: <5609f33f446fa08f83109a2f6f96b53cff672d4b.1606151462.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add coprocessor registers definitions for all ID registers trapped through the TID3 bit of HSR. Those are the one that will be emulated in Xen to only publish to guests the features that are supported by Xen and that are accessible to guests. Signed-off-by: Bertrand Marquis --- xen/include/asm-arm/arm64/hsr.h | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hsr.h index ca931dd2fe..e691d41c17 100644 --- a/xen/include/asm-arm/arm64/hsr.h +++ b/xen/include/asm-arm/arm64/hsr.h @@ -110,6 +110,43 @@ #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) +/* Those registers are used when HCR_EL2.TID3 is set */ +#define HSR_SYSREG_ID_PFR0_EL1 HSR_SYSREG(3,0,c0,c1,0) +#define HSR_SYSREG_ID_PFR1_EL1 HSR_SYSREG(3,0,c0,c1,1) +#define HSR_SYSREG_ID_PFR2_EL1 HSR_SYSREG(3,0,c0,c3,4) +#define HSR_SYSREG_ID_DFR0_EL1 HSR_SYSREG(3,0,c0,c1,2) +#define HSR_SYSREG_ID_DFR1_EL1 HSR_SYSREG(3,0,c0,c3,5) +#define HSR_SYSREG_ID_AFR0_EL1 HSR_SYSREG(3,0,c0,c1,3) +#define HSR_SYSREG_ID_MMFR0_EL1 HSR_SYSREG(3,0,c0,c1,4) +#define HSR_SYSREG_ID_MMFR1_EL1 HSR_SYSREG(3,0,c0,c1,5) +#define HSR_SYSREG_ID_MMFR2_EL1 HSR_SYSREG(3,0,c0,c1,6) +#define HSR_SYSREG_ID_MMFR3_EL1 HSR_SYSREG(3,0,c0,c1,7) +#define HSR_SYSREG_ID_MMFR4_EL1 HSR_SYSREG(3,0,c0,c2,6) +#define HSR_SYSREG_ID_MMFR5_EL1 HSR_SYSREG(3,0,c0,c3,6) +#define HSR_SYSREG_ID_ISAR0_EL1 HSR_SYSREG(3,0,c0,c2,0) +#define HSR_SYSREG_ID_ISAR1_EL1 HSR_SYSREG(3,0,c0,c2,1) +#define HSR_SYSREG_ID_ISAR2_EL1 HSR_SYSREG(3,0,c0,c2,2) +#define HSR_SYSREG_ID_ISAR3_EL1 HSR_SYSREG(3,0,c0,c2,3) +#define HSR_SYSREG_ID_ISAR4_EL1 HSR_SYSREG(3,0,c0,c2,4) +#define HSR_SYSREG_ID_ISAR5_EL1 HSR_SYSREG(3,0,c0,c2,5) +#define HSR_SYSREG_ID_ISAR6_EL1 HSR_SYSREG(3,0,c0,c2,7) +#define HSR_SYSREG_MVFR0_EL1 HSR_SYSREG(3,0,c0,c3,0) +#define HSR_SYSREG_MVFR1_EL1 HSR_SYSREG(3,0,c0,c3,1) +#define HSR_SYSREG_MVFR2_EL1 HSR_SYSREG(3,0,c0,c3,2) + +#define HSR_SYSREG_ID_AA64PFR0_EL1 HSR_SYSREG(3,0,c0,c4,0) +#define HSR_SYSREG_ID_AA64PFR1_EL1 HSR_SYSREG(3,0,c0,c4,1) +#define HSR_SYSREG_ID_AA64DFR0_EL1 HSR_SYSREG(3,0,c0,c5,0) +#define HSR_SYSREG_ID_AA64DFR1_EL1 HSR_SYSREG(3,0,c0,c5,1) +#define HSR_SYSREG_ID_AA64ISAR0_EL1 HSR_SYSREG(3,0,c0,c6,0) +#define HSR_SYSREG_ID_AA64ISAR1_EL1 HSR_SYSREG(3,0,c0,c6,1) +#define HSR_SYSREG_ID_AA64MMFR0_EL1 HSR_SYSREG(3,0,c0,c7,0) +#define HSR_SYSREG_ID_AA64MMFR1_EL1 HSR_SYSREG(3,0,c0,c7,1) +#define HSR_SYSREG_ID_AA64MMFR2_EL1 HSR_SYSREG(3,0,c0,c7,2) +#define HSR_SYSREG_ID_AA64AFR0_EL1 HSR_SYSREG(3,0,c0,c5,4) +#define HSR_SYSREG_ID_AA64AFR1_EL1 HSR_SYSREG(3,0,c0,c5,5) +#define HSR_SYSREG_ID_AA64ZFR0_EL1 HSR_SYSREG(3,0,c0,c4,4) + #endif /* __ASM_ARM_ARM64_HSR_H */ /* From patchwork Thu Nov 26 15:51:05 2020 Content-Type: text/plain; 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Thu, 26 Nov 2020 07:53:04 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A85963F23F; Thu, 26 Nov 2020 07:53:03 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 3/7] xen/arm: create a cpuinfo structure for guest Date: Thu, 26 Nov 2020 15:51:05 +0000 Message-Id: <538c6319adadd9944187fcb9df52f66af079cf13.1606151462.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Create a cpuinfo structure for guest and mask into it the features that we do not support in Xen or that we do not want to publish to guests. Modify some values in the cpuinfo structure for guests to mask some features which we do not want to allow to guests (like AMU) or we do not support (like SVE). The code is trying to group together registers modifications for the same feature to be able in the long term to easily enable/disable a feature depending on user parameters or add other registers modification in the same place (like enabling/disabling HCR bits). Signed-off-by: Bertrand Marquis --- xen/arch/arm/cpufeature.c | 51 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpufeature.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 835c48ca28..4cc4ebc78a 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -24,6 +24,8 @@ DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS); +struct cpuinfo_arm __read_mostly guest_cpuinfo; + void update_cpu_capabilities(const struct arm_cpu_capabilities *caps, const char *info) { @@ -155,6 +157,55 @@ void identify_cpu(struct cpuinfo_arm *c) #endif } +/* + * This function is creating a cpuinfo structure with values modified to mask + * all cpu features that should not be published to guest. + * The created structure is then used to provide ID registers values to guests. + */ +static int __init create_guest_cpuinfo(void) +{ + /* + * TODO: The code is currently using only the features detected on the boot + * core. In the long term we should try to compute values containing only + * features supported by all cores. + */ + identify_cpu(&guest_cpuinfo); + +#ifdef CONFIG_ARM_64 + /* Disable MPAM as xen does not support it */ + guest_cpuinfo.pfr64.mpam = 0; + guest_cpuinfo.pfr64.mpam_frac = 0; + + /* Disable SVE as Xen does not support it */ + guest_cpuinfo.pfr64.sve = 0; + guest_cpuinfo.zfr64.bits[0] = 0; + + /* Disable MTE as Xen does not support it */ + guest_cpuinfo.pfr64.mte = 0; +#endif + + /* Disable AMU */ +#ifdef CONFIG_ARM_64 + guest_cpuinfo.pfr64.amu = 0; +#endif + guest_cpuinfo.pfr32.amu = 0; + + /* Disable RAS as Xen does not support it */ +#ifdef CONFIG_ARM_64 + guest_cpuinfo.pfr64.ras = 0; + guest_cpuinfo.pfr64.ras_frac = 0; +#endif + guest_cpuinfo.pfr32.ras = 0; + guest_cpuinfo.pfr32.ras_frac = 0; + + return 0; +} +/* + * This function needs to be run after all smp are started to have + * cpuinfo structures for all cores. + */ +__initcall(create_guest_cpuinfo); + /* * Local variables: * mode: C diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 1862c14e37..f03aca3d90 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -290,6 +290,8 @@ extern void identify_cpu(struct cpuinfo_arm *); extern struct cpuinfo_arm cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] +extern struct cpuinfo_arm guest_cpuinfo; + #endif /* __ASSEMBLY__ */ #endif From patchwork Thu Nov 26 15:51:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11934291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 864FAC63697 for ; Thu, 26 Nov 2020 15:53:23 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 37B8021D40 for ; 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Thu, 26 Nov 2020 15:53:13 +0000 X-Inumbo-ID: f0c60b78-2f02-4709-a42d-d384f03bdf94 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id f0c60b78-2f02-4709-a42d-d384f03bdf94; Thu, 26 Nov 2020 15:53:05 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39FEB1516; Thu, 26 Nov 2020 07:53:05 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8AF283F23F; Thu, 26 Nov 2020 07:53:04 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 4/7] xen/arm: Add handler for ID registers on arm64 Date: Thu, 26 Nov 2020 15:51:06 +0000 Message-Id: <2db0532f50eafdce50b62b22b58ae04072a4a56a.1606151462.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add vsysreg emulation for registers trapped when TID3 bit is activated in HSR. The emulation is returning the value stored in cpuinfo_guest structure for most values and the hardware value for registers not stored in the structure (those are mostly registers existing only as a provision for feature use but who have no definition right now). Signed-off-by: Bertrand Marquis --- xen/arch/arm/arm64/vsysreg.c | 49 ++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 8a85507d9d..970ef51603 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -69,6 +69,14 @@ TVM_REG(CONTEXTIDR_EL1) break; \ } +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg,field,offset) \ + case HSR_SYSREG_##reg: \ + { \ + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -259,6 +267,47 @@ void do_sysreg(struct cpu_user_regs *regs, */ return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0_EL1, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1_EL1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2_EL1, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0_EL1, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1_EL1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0_EL1, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0_EL1, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1_EL1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2_EL1, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3_EL1, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4_EL1, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5_EL1, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0_EL1, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1_EL1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2_EL1, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3_EL1, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4_EL1, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5_EL1, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6_EL1, isa32, 6) + GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0) + GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1) + GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2) + GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0) + GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1) + GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0) + GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1) + GENERATE_TID3_INFO(ID_AA64ISAR0_EL1, isa64, 0) + GENERATE_TID3_INFO(ID_AA64ISAR1_EL1, isa64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR0_EL1, mm64, 0) + GENERATE_TID3_INFO(ID_AA64MMFR1_EL1, mm64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2) + GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0) + GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1) + GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0) + /* * HCR_EL2.TIDCP * From patchwork Thu Nov 26 15:51:07 2020 Content-Type: text/plain; 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Thu, 26 Nov 2020 15:53:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C7B331B; Thu, 26 Nov 2020 07:53:06 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6D6863F23F; Thu, 26 Nov 2020 07:53:05 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 5/7] xen/arm: Add handler for cp15 ID registers Date: Thu, 26 Nov 2020 15:51:07 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add support for emulation of cp15 based ID registers (on arm32 or when running a 32bit guest on arm64). The handlers are returning the values stored in the guest_cpuinfo structure. In the current status the MVFR registers are no supported. Signed-off-by: Bertrand Marquis --- xen/arch/arm/vcpreg.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index cdc91cdf5b..d0c6406f34 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -155,6 +155,14 @@ TVM_REG32(CONTEXTIDR, CONTEXTIDR_EL1) break; \ } +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg,field,offset) \ + case HSR_CPREG32(reg): \ + { \ + return handle_ro_read_val(regs, regidx, cp32.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp32 cp32 = hsr.cp32; @@ -286,6 +294,33 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6, isa32, 6) + /* MVFR registers are in cp10 no cp15 */ + /* * HCR_EL2.TIDCP * From patchwork Thu Nov 26 15:51:08 2020 Content-Type: text/plain; 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Thu, 26 Nov 2020 07:53:06 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4F7FA3F23F; Thu, 26 Nov 2020 07:53:06 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 6/7] xen/arm: Add CP10 exception support to handle VMFR Date: Thu, 26 Nov 2020 15:51:08 +0000 Message-Id: <18f51a4276f50e270f80d1d7d13b156509233cac.1606151462.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add support for cp10 exceptions decoding to be able to emulate the values for VMFR0 and VMFR1 when TID3 bit of HSR is activated. This is required for aarch32 guests accessing VMFR0 and VMFR1 using vmrs and vmsr instructions. Signed-off-by: Bertrand Marquis --- xen/arch/arm/traps.c | 5 +++++ xen/arch/arm/vcpreg.c | 38 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/traps.h | 1 + 4 files changed, 45 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 22bd1bd4c6..28d9d64558 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2097,6 +2097,11 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) perfc_incr(trap_cp14_dbg); do_cp14_dbg(regs, hsr); break; + case HSR_EC_CP10: + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); + perfc_incr(trap_cp10); + do_cp10(regs, hsr); + break; case HSR_EC_CP: GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index d0c6406f34..9d6a36ca5d 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -634,6 +634,44 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) inject_undef_exception(regs, hsr); } +void do_cp10(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * HSR.TID3 is trapping access to MVFR register used to identify the + * VFP/Simd using VMRS/VMSR instructions. + * In this case MVFR2 is not supported as the instruction does not support + * it. + * Exception encoding is using MRC/MCR standard with the reg field in Crn + * as are declared MVFR0 and MVFR1 in cpregs.h + */ + GENERATE_TID3_INFO(MVFR0, mvfr, 0) + GENERATE_TID3_INFO(MVFR1, mvfr, 1) + + default: + gdprintk(XENLOG_ERR, + "%s p10, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + + advance_pc(regs, hsr); +} + void do_cp(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp cp = hsr.cp; diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index 6a83185163..31f071222b 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -11,6 +11,7 @@ PERFCOUNTER(trap_cp15_64, "trap: cp15 64-bit access") PERFCOUNTER(trap_cp14_32, "trap: cp14 32-bit access") PERFCOUNTER(trap_cp14_64, "trap: cp14 64-bit access") PERFCOUNTER(trap_cp14_dbg, "trap: cp14 dbg access") +PERFCOUNTER(trap_cp10, "trap: cp10 access") PERFCOUNTER(trap_cp, "trap: cp access") PERFCOUNTER(trap_smc32, "trap: 32-bit smc") PERFCOUNTER(trap_hvc32, "trap: 32-bit hvc") diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 997c37884e..c4a3d0fb1b 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -62,6 +62,7 @@ void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp10(struct cpu_user_regs *regs, const union hsr hsr); void do_cp(struct cpu_user_regs *regs, const union hsr hsr); /* SMCCC handling */ From patchwork Thu Nov 26 15:51:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11934295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E05C5C63798 for ; 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Thu, 26 Nov 2020 15:53:23 +0000 X-Inumbo-ID: a4884ce1-4f93-440f-a742-a98e93937557 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id a4884ce1-4f93-440f-a742-a98e93937557; Thu, 26 Nov 2020 15:53:08 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D67FA31B; Thu, 26 Nov 2020 07:53:07 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 330C63F23F; Thu, 26 Nov 2020 07:53:07 -0800 (PST) From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH 7/7] xen/arm: Activate TID3 in HCR_EL2 Date: Thu, 26 Nov 2020 15:51:09 +0000 Message-Id: <4d48107fb864222aa6f32ebf691e169a14c3e6b9.1606151462.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Activate TID3 bit in HSR register when starting a guest. This will trap all coprecessor ID registers so that we can give to guest values corresponding to what they can actually use and mask some features to guests even though they would be supported by the underlying hardware (like SVE or MPAM). Signed-off-by: Bertrand Marquis --- xen/arch/arm/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 28d9d64558..c1a9ad6056 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -98,7 +98,7 @@ register_t get_default_hcr_flags(void) { return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| (vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) | - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); + HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); } static enum {