From patchwork Fri Nov 27 14:15:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 11936419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2D5BC63798 for ; Fri, 27 Nov 2020 14:25:51 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7339621D7A for ; Fri, 27 Nov 2020 14:25:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="3U+zQlkw"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="raaH+hf0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7339621D7A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZiJyultdatJ7gIvYxo8vuqVbEpFIKrVnKd3XKa7YuCA=; b=3U+zQlkwgR/J2aiy0IsRBEfbZ nkZsba6KaY1n2vhE/uJlYMGSmEkIOIoE+Pt7YSXThpwyTQFV20RNFtZuaWV09P/LJNhlc4Ri4i0BY xXtidPCclQFB7dKnDHDqBpGYBQk8l1uYNtNPcJu6R2MMewV8hFl6tIwRmpN4guBTyQ5zKEUkcnkVI jgMRY8o07BPoYV93vJ5Mq8IjgFqYxQf6TCmomfTQWRIwK36zf9eZCxmHcOGxqK0VNb5DOIPIgTc1/ kO3sgNIVSpaUyB5gla/Y35fM8LEDzg/+FEHyw0FlrdpKH0IKRgU6Y3dOc4HLXcLvGH53Bo76cRzFR 0K4F17rBA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kieh0-0001DW-Eg; Fri, 27 Nov 2020 14:25:46 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiegu-0001BO-Ay; Fri, 27 Nov 2020 14:25:41 +0000 X-UUID: 6f198943fdc44e5bbff859155be812a2-20201127 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=cTb/P/g1NKmtcCLpR16U3BIG3MESWcm6IG1Z/CQgAWI=; b=raaH+hf0/eCDGD84sq86maqIorCdBHWqsYJwwI/lx1xz/ZYlqsGMFlce3df/gI9ULW9yWUoE8G/VDaDyZMmAm0rdqGPSX92aojBZUOVbpAZMgrisGa18cUU0NSATMCtRi2Wptvnqz6dmE5ICimBJ1XycTFEAGQXnIkLNs2pBUWQ=; X-UUID: 6f198943fdc44e5bbff859155be812a2-20201127 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1982670556; Fri, 27 Nov 2020 06:25:58 -0800 Received: from MTKMBS09N2.mediatek.inc (172.21.101.94) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 06:15:34 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 22:15:33 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 27 Nov 2020 22:15:32 +0800 From: Hanks Chen To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Matthias Brugger , Russell King , Catalin Marinas , Will Deacon , Mark Rutland Subject: [PATCH v1 1/3] irqchip/gic: enable irq target all Date: Fri, 27 Nov 2020 22:15:29 +0800 Message-ID: <1606486531-25719-2-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> References: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201127_092540_540929_4B262A80 X-CRM114-Status: GOOD ( 25.44 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: CC Hwang , Kuohong Wang , Hanks Chen , Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Support for interrupt distribution design for SMP system solutions. With this feature enabled ,the SPI interrupts would be routed to all the cores rather than boot core to achieve better load balance of interrupt handling. That is, interrupts might be serviced simultaneously on different CPUs. Signed-off-by: Hanks Chen --- drivers/irqchip/Kconfig | 12 ++++ drivers/irqchip/irq-gic-v3.c | 107 +++++++++++++++++++++-------- include/linux/irqchip/arm-gic-v3.h | 1 + kernel/irq/cpuhotplug.c | 22 ++++++ kernel/irq/manage.c | 7 ++ 5 files changed, 122 insertions(+), 27 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c6098eee0c7c..c88ee7731e92 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -597,4 +597,16 @@ config MST_IRQ help Support MStar Interrupt Controller. +config ARM_IRQ_TARGET_ALL + bool "Distribute interrupts across processors on SMP system" + depends on SMP && ARM_GIC_V3 + help + Support for interrupt distribution design for + SMP system solutions. With this feature enabled ,the + SPI interrupts would be routed to all the cores rather + than boot cpu to achieve better load balance of interrupt + handling + + If you don't know what to do here, say N. + endmenu diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 16fecc0febe8..62a878ce4681 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -381,6 +381,12 @@ static inline bool gic_supports_nmi(void) static_branch_likely(&supports_pseudo_nmis); } +static inline bool gic_supports_1n(void) +{ + return (IS_ENABLED(CONFIG_ARM_IRQ_TARGET_ALL) && + ~(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_No1N)); +} + static int gic_irq_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool val) { @@ -716,6 +722,7 @@ static void __init gic_dist_init(void) { unsigned int i; u64 affinity; + void __iomem *base = gic_data.dist_base; u32 val; @@ -759,16 +766,27 @@ static void __init gic_dist_init(void) /* Enable distributor with ARE, Group1 */ writel_relaxed(val, base + GICD_CTLR); - /* - * Set all global interrupts to the boot CPU only. ARE must be - * enabled. - */ - affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); - for (i = 32; i < GIC_LINE_NR; i++) - gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); + if (!gic_supports_1n()) { + /* + * Set all global interrupts to the boot CPU only. ARE must be + * enabled. + */ + affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); + for (i = 32; i < GIC_LINE_NR; i++) + gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); - for (i = 0; i < GIC_ESPI_NR; i++) - gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); + for (i = 0; i < GIC_ESPI_NR; i++) + gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); + } else { + /* default set target all for all SPI */ + for (i = 32; i < GIC_LINE_NR; i++) + gic_write_irouter(GICD_IROUTER_SPI_MODE_ANY, + base + GICD_IROUTER + i * 8); + + for (i = 0; i < GIC_ESPI_NR; i++) + gic_write_irouter(GICD_IROUTER_SPI_MODE_ANY, + base + GICD_IROUTERnE + i * 8); + } } static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) @@ -1191,29 +1209,64 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, if (gic_irq_in_rdist(d)) return -EINVAL; - /* If interrupt was enabled, disable it first */ - enabled = gic_peek_irq(d, GICD_ISENABLER); - if (enabled) - gic_mask_irq(d); + if (!gic_supports_1n()) { + /* If interrupt was enabled, disable it first */ + enabled = gic_peek_irq(d, GICD_ISENABLER); + if (enabled) + gic_mask_irq(d); - offset = convert_offset_index(d, GICD_IROUTER, &index); - reg = gic_dist_base(d) + offset + (index * 8); - val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); + offset = convert_offset_index(d, GICD_IROUTER, &index); + reg = gic_dist_base(d) + offset + (index * 8); + val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); - gic_write_irouter(val, reg); + gic_write_irouter(val, reg); - /* - * If the interrupt was enabled, enabled it again. Otherwise, - * just wait for the distributor to have digested our changes. - */ - if (enabled) - gic_unmask_irq(d); - else - gic_dist_wait_for_rwp(); + /* + * If the interrupt was enabled, enabled it again. Otherwise, + * just wait for the distributor to have digested our changes. + */ + if (enabled) + gic_unmask_irq(d); + else + gic_dist_wait_for_rwp(); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + } else { + /* + * no need to update when: + * input mask is equal to the current setting + */ + if (cpumask_equal(irq_data_get_affinity_mask(d), mask_val)) + return IRQ_SET_MASK_OK_NOCOPY; + + /* If interrupt was enabled, disable it first */ + enabled = gic_peek_irq(d, GICD_ISENABLER); + if (enabled) + gic_mask_irq(d); + + offset = convert_offset_index(d, GICD_IROUTER, &index); + reg = gic_dist_base(d) + offset + (index * 8); - irq_data_update_effective_affinity(d, cpumask_of(cpu)); + /* GICv3 supports target is 1 or all */ + if (cpumask_weight(mask_val) > 1) + val = GICD_IROUTER_SPI_MODE_ANY; + else + val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); + + gic_write_irouter(val, reg); + + /* + * If the interrupt was enabled, enabled it again. Otherwise, + * just wait for the distributor to have digested our changes. + */ + if (enabled) + gic_unmask_irq(d); + else + gic_dist_wait_for_rwp(); + } - return IRQ_SET_MASK_OK_DONE; + return IRQ_SET_MASK_OK; } #else #define gic_set_affinity NULL diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index f6d092fdb93d..c24336d506a3 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -80,6 +80,7 @@ #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) #define GICD_TYPER_RSS (1U << 26) +#define GICD_TYPER_No1N (1U << 25) #define GICD_TYPER_LPIS (1U << 17) #define GICD_TYPER_MBIS (1U << 16) #define GICD_TYPER_ESPI (1U << 8) diff --git a/kernel/irq/cpuhotplug.c b/kernel/irq/cpuhotplug.c index 02236b13b359..779512e44960 100644 --- a/kernel/irq/cpuhotplug.c +++ b/kernel/irq/cpuhotplug.c @@ -87,6 +87,18 @@ static bool migrate_one_irq(struct irq_desc *desc) return false; } +#ifdef CONFIG_ARM_IRQ_TARGET_ALL + /* + * No move required, if interrupt is 1 of N IRQ. + * write current cpu_online_mask into affinity mask. + */ + if (cpumask_weight(desc->irq_common_data.affinity) > 1) { + cpumask_copy(desc->irq_common_data.affinity, cpu_online_mask); + + return false; + } +#endif + /* * Complete an eventually pending irq move cleanup. If this * interrupt was moved in hard irq context, then the vectors need @@ -191,6 +203,16 @@ static void irq_restore_affinity_of_irq(struct irq_desc *desc, unsigned int cpu) struct irq_data *data = irq_desc_get_irq_data(desc); const struct cpumask *affinity = irq_data_get_affinity_mask(data); +#ifdef CONFIG_ARM_IRQ_TARGET_ALL + /* + * No restore required, if interrupt is 1 of N IRQ. + */ + if (cpumask_weight(affinity) > 1) { + cpumask_set_cpu(cpu, irq_data_get_affinity_mask(data)); + return; + } +#endif + if (!irqd_affinity_is_managed(data) || !desc->action || !irq_data_get_irq_chip(data) || !cpumask_test_cpu(cpu, affinity)) return; diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index c460e0496006..770b97e326bd 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -270,7 +270,14 @@ int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, switch (ret) { case IRQ_SET_MASK_OK: case IRQ_SET_MASK_OK_DONE: +#ifndef CONFIG_ARM_IRQ_TARGET_ALL cpumask_copy(desc->irq_common_data.affinity, mask); +#else + if (cpumask_weight(mask) > 1) + cpumask_copy(desc->irq_common_data.affinity, cpu_online_mask); + else + cpumask_copy(desc->irq_common_data.affinity, mask); +#endif fallthrough; case IRQ_SET_MASK_OK_NOCOPY: irq_validate_effective_affinity(data); From patchwork Fri Nov 27 14:15:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 11936423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EDB3C63798 for ; Fri, 27 Nov 2020 14:26:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E71292222C for ; Fri, 27 Nov 2020 14:26:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QFsI5dCB"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="k7+ZI/Kq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E71292222C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=egFum8BzduUizmorSWZEFl/kXhF0qpA9j+6zBwbAHGM=; b=QFsI5dCBDZiZsaMrIVkXiO4Nz KYeNLM3wUqnDlkbcdJD1lNbn2fpf9a5XVbpmMmpM5mP7K/SBPLBXItJHnLon1zqO4CSilfRuy6//3 BGg3rSLf1pPzladsSEqMqjdBVTvSBsGtlORSxYlBxVdf9FV5C2PrWeyiTn8bQiqrmXgGw9sG+yvv/ okl7gCgA3p3aN1yWyahjB4O1uvQ3mPXdBnepzCAJ/k4z7plp1CF+9kS+o+2lsxoinU8sKFTGITAaa F9zvQQtJdLtb8a9boDrVOKNbo8n4CDUsTTQDDfmfWagZ9sUt3ac+SygkyahJ4ZGXHHYJAGEtrsl4B kcCr2/oFQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiehD-0001IK-Q8; Fri, 27 Nov 2020 14:25:59 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiegz-0001C6-Do; Fri, 27 Nov 2020 14:25:47 +0000 X-UUID: 3d7c0365bf07454e8d3dcdf06a5c26e2-20201127 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=71IL+fjPy5tcd4qRDjG/PsF6skVBO1wgnu8pe3WvDSw=; b=k7+ZI/KqUwIUZkUf8u8BKCvTVnNkLcmzrfPkylsxDwGFhNzTtVfccm5VAnC0b4JGDTK5KxLEbdwFRMjVKdiVar4VzZq6K46mADfKYWzzlydehzL7XOwT64iHdijR6Mx/MPEeOks0m0XnlovOVdKKMT+VFV/NxehflXR30AbaM8s=; X-UUID: 3d7c0365bf07454e8d3dcdf06a5c26e2-20201127 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 433722771; Fri, 27 Nov 2020 06:25:58 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 06:15:35 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 22:15:32 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 27 Nov 2020 22:15:33 +0800 From: Hanks Chen To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Matthias Brugger , Russell King , Catalin Marinas , Will Deacon , Mark Rutland Subject: [PATCH v1 2/3] arm: disable irq on cpu shutdown flow Date: Fri, 27 Nov 2020 22:15:30 +0800 Message-ID: <1606486531-25719-3-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> References: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 51FF224ED26ADDFF5E1372E7DC0ED8DD164EB61E564AED9D7CBF5263AC81A60A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201127_092545_729078_DA84708B X-CRM114-Status: GOOD ( 13.12 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: CC Hwang , Kuohong Wang , Hanks Chen , Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Disable irq on cpu shutdown flow to ensure interrupts did not bother this cpu after status as offline. To avoid suspicious RCU usage [0:swapper/0]RCU used illegally from offline CPU! ... [0:swapper/0]lockdep: [name:lockdep&]cpu_id = 0, cpu_is_offline = 1 Signed-off-by: Hanks Chen --- arch/arm/kernel/smp.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 48099c6e1e4a..6b8f72490320 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -262,6 +262,12 @@ int __cpu_disable(void) remove_cpu_topology(cpu); #endif + /* + * we disable irq here to ensure interrupts + * did not bother this cpu after status as offline. + */ + local_irq_disable(); + /* * Take this CPU offline. Once we clear this, we can't return, * and we must not schedule until we're ready to give up the cpu. @@ -600,11 +606,11 @@ static void ipi_cpu_stop(unsigned int cpu) raw_spin_unlock(&stop_lock); } - set_cpu_online(cpu, false); - local_fiq_disable(); local_irq_disable(); + set_cpu_online(cpu, false); + while (1) { cpu_relax(); wfe(); From patchwork Fri Nov 27 14:15:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 11936421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E789BC2D0E4 for ; Fri, 27 Nov 2020 14:26:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88E1221D7A for ; Fri, 27 Nov 2020 14:26:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="xa5qSC36"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="dHTGjqst" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 88E1221D7A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jbDMVU66Zg/smWWV7UdmqahROe1q7NpYpqqIHQfkdio=; b=xa5qSC3696ZpWt3oXkcjPlY4J n6JHZ+EX3L760mTHSh68OIj85KShPUmoVROYKJZkwfPZJiyAtVHjc453YEzKgZtl7NYHFxr0jdqCj GDmZ4UCt3Q1g4VAPUHW5B6amDkpeMVYCBVLgCkpfkc1Faz2xbIwj4mqEjUyD9MZjlPG/NlwGP5toA +X4okUU42YhbEJUvu/m5I8DN2o/LvnUYo0MEYPtCFKdpDf1l0B+YjJtp4paf90ObK7yZOXSlt9cg2 hBR4yKYkbXyvCfm3G0V5pk63SXiA+E1+Jsewevp+IFV1Rzxphheef/y7y+8i5al+81MPWhAELBT43 1gjxDDdYg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiehF-0001J3-UF; Fri, 27 Nov 2020 14:26:01 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiegz-0001CM-DY; Fri, 27 Nov 2020 14:25:47 +0000 X-UUID: 50f984392b66476981425540b8125e97-20201127 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nIo5YHk8C7QN9WuW+9uAQyOWMwm8/8NtFJJbZ3U6lko=; b=dHTGjqst9fSI/WWb4tYhq0yu+1k5/OmP9mTyXUI7fGHnvnN6RHbkNRWLLV3ZrAmUr0U4w8DeVkJEBdqfOnhCH2lZuOkDQWhDEkQMY6perBp5e2f4Dvi6PgvCD74FnhmKCs6UmsLBkEX+OVKnAouRF/U50V4LVoPaZdOFH1uGcdk=; X-UUID: 50f984392b66476981425540b8125e97-20201127 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 269171504; Fri, 27 Nov 2020 06:25:58 -0800 Received: from MTKMBS09N1.mediatek.inc (172.21.101.35) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 06:15:33 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 22:15:32 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 27 Nov 2020 22:15:33 +0800 From: Hanks Chen To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Matthias Brugger , Russell King , Catalin Marinas , Will Deacon , Mark Rutland Subject: [PATCH v1 3/3] arm64: disable irq on cpu shutdown flow Date: Fri, 27 Nov 2020 22:15:31 +0800 Message-ID: <1606486531-25719-4-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> References: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201127_092545_694076_58ECEFAE X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: CC Hwang , Kuohong Wang , Hanks Chen , Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Disable irq on cpu shutdown flow to ensure interrupts did not bother this cpu after status as offline. To avoid suspicious RCU usage (0)[0:swapper/0]RCU used illegally from offline CPU! ... (0)[0:swapper/0]lockdep: [name:lockdep&]cpu_id = 0, cpu_is_offline = 1 Signed-off-by: Hanks Chen --- arch/arm64/kernel/smp.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 82e75fc2c903..27a6553fa86f 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -308,6 +308,12 @@ int __cpu_disable(void) remove_cpu_topology(cpu); numa_remove_cpu(cpu); + /* + * we disable irq here to ensure interrupts + * did not bother this cpu after status as offline. + */ + local_irq_disable(); + /* * Take this CPU offline. Once we clear this, we can't return, * and we must not schedule until we're ready to give up the cpu. @@ -842,9 +848,10 @@ void arch_irq_work_raise(void) static void local_cpu_stop(void) { + local_daif_mask(); + set_cpu_online(smp_processor_id(), false); - local_daif_mask(); sdei_mask_local_cpu(); cpu_park_loop(); }