From patchwork Sun Nov 29 23:07:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Patchwork-Id: 11939411 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60C12C64E8A for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EF3C2084C for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727543AbgK2XIb (ORCPT ); Sun, 29 Nov 2020 18:08:31 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33986 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726777AbgK2XIb (ORCPT ); Sun, 29 Nov 2020 18:08:31 -0500 Received: by mail-wr1-f67.google.com with SMTP id k14so13093807wrn.1 for ; Sun, 29 Nov 2020 15:08:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wdEq2gl8a+PAeDGUba3SmwX1K8uJGnFaaAqpMDssDWo=; b=kEWl5V3lgFkXYBgiljW0vSbymGvC4efJeDNgxy81ZlHcrZLXK0PfZDBWhwhLyoK3o3 HnAI171us9pK5lFoklmaLs/BbNVcRRMe3AmYiUSlfyRp54SAT6onqEBZrPUDnt2omJPf DhDABqEMRTqyAIBN3OpIH+DoV+2gy41MMwz08bxwnz7x6XGZ8Z1EGnLA3lGGzruqFY4O 5VXFqIY7KCW/mGirLWyFXKswpoFD8crTZWdhQA2eyDhPWXmiL32tZTzhkBBM1R9ojgyB zCQZ70uWgruYrGBHDTpcHXz47eISc48Z6Za24J+YR3OAcSPP4+V7zYPv8CVtSDxFwLxm oOeg== X-Gm-Message-State: AOAM531lv2EPIvBFb7fXYw1rGsRz2sSxGhSN/1vLn2LuHY2hC0lBhBLM XDXQdmABzyE+yOyXZ7123is= X-Google-Smtp-Source: ABdhPJzemcgSIWckEmLG/WoWTheRZkQseBG6J/lGXVepGvFFOylFGIo2a+IOWOYyZ2ycSEeUpAhqng== X-Received: by 2002:adf:ead1:: with SMTP id o17mr25556413wrn.396.1606691267941; Sun, 29 Nov 2020 15:07:47 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:47 -0800 (PST) From: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 1/5] PCI: Unify ECAM constants in native PCI Express drivers Date: Sun, 29 Nov 2020 23:07:39 +0000 Message-Id: <20201129230743.3006978-2-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add ECAM-related constants to provide a set of standard constants defining memory address shift values to the byte-level address that can be used to access the PCI Express Configuration Space, and then move native PCI Express controller drivers to use the newly introduced definitions retiring driver-specific ones. Refactor pci_ecam_map_bus() function to use newly added constants so that limits to the bus, device function and offset (now limited to 4K as per the specification) are in place to prevent the defective or malicious caller from supplying incorrect configuration offset and thus targeting the wrong device when accessing extended configuration space. This refactor also allows for the ".bus_shit" initialisers to be dropped when the user is not using a custom value as a default value will be used as per the PCI Express Specification. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński Reviewed-by: Jon Derrick --- drivers/pci/controller/dwc/pcie-al.c | 12 ++------- drivers/pci/controller/dwc/pcie-hisi.c | 2 -- drivers/pci/controller/pci-aardvark.c | 13 +++------- drivers/pci/controller/pci-host-generic.c | 1 - drivers/pci/controller/pci-thunder-ecam.c | 1 - drivers/pci/controller/pcie-brcmstb.c | 16 ++---------- drivers/pci/controller/pcie-rockchip-host.c | 27 ++++++++++----------- drivers/pci/controller/pcie-rockchip.h | 8 +----- drivers/pci/controller/pcie-tango.c | 1 - drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++----- drivers/pci/controller/pcie-xilinx.c | 11 ++------- drivers/pci/controller/vmd.c | 11 ++++----- drivers/pci/ecam.c | 23 ++++++++++++------ include/linux/pci-ecam.h | 27 +++++++++++++++++++++ 14 files changed, 73 insertions(+), 89 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index f973fbca90cf..af9e51ab1af8 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -76,7 +76,6 @@ static int al_pcie_init(struct pci_config_window *cfg) } const struct pci_ecam_ops al_pcie_ops = { - .bus_shift = 20, .init = al_pcie_init, .pci_ops = { .map_bus = al_pcie_map_bus, @@ -138,8 +137,6 @@ struct al_pcie { struct al_pcie_target_bus_cfg target_bus_cfg; }; -#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12) - #define to_al_pcie(x) dev_get_drvdata((x)->dev) static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) @@ -226,11 +223,6 @@ static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg; unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask; unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; - void __iomem *pci_base_addr; - - pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base + - (busnr_ecam << 20) + - PCIE_ECAM_DEVFN(devfn)); if (busnr_reg != target_bus_cfg->reg_val) { dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n", @@ -241,7 +233,7 @@ static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, target_bus_cfg->reg_mask); } - return pci_base_addr + where; + return pp->va_cfg0_base + PCIE_ECAM_OFFSET(busnr_ecam, devfn, where); } static struct pci_ops al_child_pci_ops = { @@ -264,7 +256,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) target_bus_cfg = &pcie->target_bus_cfg; - ecam_bus_mask = (pcie->ecam_size >> 20) - 1; + ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1; if (ecam_bus_mask > 255) { dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n"); ecam_bus_mask = 255; diff --git a/drivers/pci/controller/dwc/pcie-hisi.c b/drivers/pci/controller/dwc/pcie-hisi.c index 5ca86796d43a..8fc5960faf28 100644 --- a/drivers/pci/controller/dwc/pcie-hisi.c +++ b/drivers/pci/controller/dwc/pcie-hisi.c @@ -100,7 +100,6 @@ static int hisi_pcie_init(struct pci_config_window *cfg) } const struct pci_ecam_ops hisi_pcie_ops = { - .bus_shift = 20, .init = hisi_pcie_init, .pci_ops = { .map_bus = hisi_pcie_map_bus, @@ -135,7 +134,6 @@ static int hisi_pcie_platform_init(struct pci_config_window *cfg) } static const struct pci_ecam_ops hisi_pcie_platform_ops = { - .bus_shift = 20, .init = hisi_pcie_platform_init, .pci_ops = { .map_bus = hisi_pcie_map_bus, diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0be485a25327..1043e54c73bd 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -164,14 +165,6 @@ #define PCIE_CONFIG_WR_TYPE0 0xa #define PCIE_CONFIG_WR_TYPE1 0xb -#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) -#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) -#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) -#define PCIE_CONF_REG(reg) ((reg) & 0xffc) -#define PCIE_CONF_ADDR(bus, devfn, where) \ - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) - #define PIO_RETRY_CNT 500 #define PIO_RETRY_DELAY 2 /* 2 us*/ @@ -687,7 +680,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_CONF_ADDR(bus->number, devfn, where); + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); @@ -748,7 +741,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_CONF_ADDR(bus->number, devfn, where); + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); diff --git a/drivers/pci/controller/pci-host-generic.c b/drivers/pci/controller/pci-host-generic.c index b51977abfdf1..63865aeb636b 100644 --- a/drivers/pci/controller/pci-host-generic.c +++ b/drivers/pci/controller/pci-host-generic.c @@ -49,7 +49,6 @@ static void __iomem *pci_dw_ecam_map_bus(struct pci_bus *bus, } static const struct pci_ecam_ops pci_dw_ecam_bus_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_dw_ecam_map_bus, .read = pci_generic_config_read, diff --git a/drivers/pci/controller/pci-thunder-ecam.c b/drivers/pci/controller/pci-thunder-ecam.c index 7e8835fee5f7..f964fd26f7e0 100644 --- a/drivers/pci/controller/pci-thunder-ecam.c +++ b/drivers/pci/controller/pci-thunder-ecam.c @@ -346,7 +346,6 @@ static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn, } const struct pci_ecam_ops pci_thunder_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = thunder_ecam_config_read, diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index bea86899bd5d..7fc80fd6f13f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -127,11 +128,7 @@ #define MSI_INT_MASK_CLR 0x14 #define PCIE_EXT_CFG_DATA 0x8000 - #define PCIE_EXT_CFG_INDEX 0x9000 -#define PCIE_EXT_BUSNUM_SHIFT 20 -#define PCIE_EXT_SLOT_SHIFT 15 -#define PCIE_EXT_FUNC_SHIFT 12 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 @@ -695,15 +692,6 @@ static bool brcm_pcie_link_up(struct brcm_pcie *pcie) return dla && plu; } -/* Configuration space read/write support */ -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) -{ - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) - | (busnr << PCIE_EXT_BUSNUM_SHIFT) - | (reg & ~3); -} - static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, int where) { @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, return PCI_SLOT(devfn) ? NULL : base + where; /* For devices, write to the config space index register */ - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); return base + PCIE_EXT_CFG_DATA + where; } diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index 9705059523a6..f1d08a1b1591 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -157,12 +157,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - u32 busdev; + void __iomem *addr; - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); - if (!IS_ALIGNED(busdev, size)) { + if (!IS_ALIGNED((uintptr_t)addr, size)) { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -175,11 +174,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, AXI_WRAPPER_TYPE1_CFG); if (size == 4) { - *val = readl(rockchip->reg_base + busdev); + *val = readl(addr); } else if (size == 2) { - *val = readw(rockchip->reg_base + busdev); + *val = readw(addr); } else if (size == 1) { - *val = readb(rockchip->reg_base + busdev); + *val = readb(addr); } else { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; @@ -191,11 +190,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - u32 busdev; + void __iomem *addr; - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); - if (!IS_ALIGNED(busdev, size)) + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + + if (!IS_ALIGNED((uintptr_t)addr, size)) return PCIBIOS_BAD_REGISTER_NUMBER; if (pci_is_root_bus(bus->parent)) @@ -206,11 +205,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, AXI_WRAPPER_TYPE1_CFG); if (size == 4) - writel(val, rockchip->reg_base + busdev); + writel(val, addr); else if (size == 2) - writew(val, rockchip->reg_base + busdev); + writew(val, addr); else if (size == 1) - writeb(val, rockchip->reg_base + busdev); + writeb(val, addr); else return PCIBIOS_BAD_REGISTER_NUMBER; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index c7d0178fc8c2..1650a5087450 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -13,6 +13,7 @@ #include #include +#include /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -178,13 +179,6 @@ #define MIN_AXI_ADDR_BITS_PASSED 8 #define PCIE_RC_SEND_PME_OFF 0x11960 #define ROCKCHIP_VENDOR_ID 0x1d87 -#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20) -#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15) -#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12) -#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0) -#define PCIE_ECAM_ADDR(bus, dev, func, reg) \ - (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \ - PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) #define PCIE_LINK_IS_L2(x) \ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) #define PCIE_LINK_UP(x) \ diff --git a/drivers/pci/controller/pcie-tango.c b/drivers/pci/controller/pcie-tango.c index d093a8ce4bb1..62a061f1d62e 100644 --- a/drivers/pci/controller/pcie-tango.c +++ b/drivers/pci/controller/pcie-tango.c @@ -208,7 +208,6 @@ static int smp8759_config_write(struct pci_bus *bus, unsigned int devfn, } static const struct pci_ecam_ops smp8759_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = smp8759_config_read, diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index f3cf7d61924f..7f29c2fdcd51 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -124,8 +125,6 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define ECAM_BUS_LOC_SHIFT 20 -#define ECAM_DEV_LOC_SHIFT 12 #define NWL_ECAM_VALUE_DEFAULT 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) @@ -240,15 +239,11 @@ static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct nwl_pcie *pcie = bus->sysdata; - int relbus; if (!nwl_pcie_valid_device(bus, devfn)) return NULL; - relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | - (devfn << ECAM_DEV_LOC_SHIFT); - - return pcie->ecam_base + relbus + where; + return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c index 8523be61bba5..fa5baeb82653 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -86,10 +87,6 @@ /* Phy Status/Control Register definitions */ #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) -/* ECAM definitions */ -#define ECAM_BUS_NUM_SHIFT 20 -#define ECAM_DEV_NUM_SHIFT 12 - /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 128 @@ -183,15 +180,11 @@ static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct xilinx_pcie_port *port = bus->sysdata; - int relbus; if (!xilinx_pcie_valid_device(bus, devfn)) return NULL; - relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | - (devfn << ECAM_DEV_NUM_SHIFT); - - return port->reg_base + relbus + where; + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index f375c21ceeb1..1361a79bd1e7 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -328,15 +329,13 @@ static void vmd_remove_irq_domain(struct vmd_dev *vmd) static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { - char __iomem *addr = vmd->cfgbar + - ((bus->number - vmd->busn_start) << 20) + - (devfn << 12) + reg; + unsigned int busnr_ecam = bus->number - vmd->busn_start; + u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); - if ((addr - vmd->cfgbar) + len >= - resource_size(&vmd->dev->resource[VMD_CFGBAR])) + if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) return NULL; - return addr; + return vmd->cfgbar + offset; } /* diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c index b54d32a31669..59f91d434859 100644 --- a/drivers/pci/ecam.c +++ b/drivers/pci/ecam.c @@ -131,25 +131,36 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct pci_config_window *cfg = bus->sysdata; + unsigned int bus_shift = cfg->ops->bus_shift; unsigned int devfn_shift = cfg->ops->bus_shift - 8; unsigned int busn = bus->number; void __iomem *base; + u32 bus_offset, devfn_offset; if (busn < cfg->busr.start || busn > cfg->busr.end) return NULL; busn -= cfg->busr.start; - if (per_bus_mapping) + if (per_bus_mapping) { base = cfg->winp[busn]; - else - base = cfg->win + (busn << cfg->ops->bus_shift); - return base + (devfn << devfn_shift) + where; + busn = 0; + } else + base = cfg->win; + + if (cfg->ops->bus_shift) { + bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift; + devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift; + where &= PCIE_ECAM_REG_MASK; + + return base + (bus_offset | devfn_offset | where); + } + + return base + PCIE_ECAM_OFFSET(busn, devfn, where); } EXPORT_SYMBOL_GPL(pci_ecam_map_bus); /* ECAM ops */ const struct pci_ecam_ops pci_generic_ecam_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read, @@ -161,7 +172,6 @@ EXPORT_SYMBOL_GPL(pci_generic_ecam_ops); #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) /* ECAM ops for 32-bit access only (non-compliant) */ const struct pci_ecam_ops pci_32b_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read32, @@ -171,7 +181,6 @@ const struct pci_ecam_ops pci_32b_ops = { /* ECAM ops for 32-bit read only (non-compliant) */ const struct pci_ecam_ops pci_32b_read_ops = { - .bus_shift = 20, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = pci_generic_config_read32, diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 033ce74f02e8..65d3d83015c3 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -9,6 +9,33 @@ #include #include +/* + * Memory address shift values for the byte-level address that + * can be used when accessing the PCI Express Configuration Space. + */ + +/* + * Enhanced Configuration Access Mechanism (ECAM) + * + * See PCI Express Base Specification, Revision 5.0, Version 1.0, + * Section 7.2.2, Table 7-1, p. 677. + */ +#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ +#define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */ + +#define PCIE_ECAM_BUS_MASK 0xff +#define PCIE_ECAM_DEVFN_MASK 0xff +#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ + +#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) +#define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT) +#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) + +#define PCIE_ECAM_OFFSET(bus, devfn, where) \ + (PCIE_ECAM_BUS(bus) | \ + PCIE_ECAM_DEVFN(devfn) | \ + PCIE_ECAM_REG(where)) + /* * struct to hold pci ops and bus shift of the config window * for a PCI controller. From patchwork Sun Nov 29 23:07:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Patchwork-Id: 11939403 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45D49C64E7B for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E8C52223F for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727433AbgK2XIb (ORCPT ); Sun, 29 Nov 2020 18:08:31 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46775 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbgK2XIb (ORCPT ); Sun, 29 Nov 2020 18:08:31 -0500 Received: by mail-wr1-f68.google.com with SMTP id g14so13027028wrm.13 for ; Sun, 29 Nov 2020 15:08:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C4ZAbgOviSl5kwTV38A0mgojnuMMJBX6cIDk0sTmaeo=; b=pdu6HEGFLTC9Oyku55Hw0/kqS2v42OW9q4gpNX1KD1K0/q6G6CXeNHX2q62rb9Am6j 55Vrm2kC/NjxRtyMvzfcAsuIhczYBRhKfFJLGmrEF9SnUg6+AT8gtqfnuAs3uU85M/Zp LaWO/JISpvJeJapijCbD8X0IllbWhPHf9nseN5RZoWLDGWJ8lCGx15/+3m49saRdUvSb OetMzsu+fVS5C4hsIhBeycLLHQrmR+K9M+T46Po/FLY2ifNnRGH6o+LeQefiyl4Os6lo lfrQFwbOImhrkxP8TViP3G1z5U0eFithHXokXfnOoSTptGyvZl15eVfB31BnV2GBEWfN gElw== X-Gm-Message-State: AOAM532C5YRCP4LWN2XF2Ar1r2OK3YwncohlwP8kZGVwY6pNcSDIlhB3 LM9L+4kfbrOvtjuBTDvd2mA= X-Google-Smtp-Source: ABdhPJyc10rS86sUCkCS7JwDecOpIFDWRywvD2p3TPef9gz9BjYexnZrT+fR1+MqL8LVO9fcgPl/QQ== X-Received: by 2002:adf:fd0e:: with SMTP id e14mr24090769wrr.119.1606691269434; Sun, 29 Nov 2020 15:07:49 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:48 -0800 (PST) From: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 2/5] PCI: thunder-pem: Add constant for custom ".bus_shit" initialiser Date: Sun, 29 Nov 2020 23:07:40 +0000 Message-Id: <20201129230743.3006978-3-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a custom constant for the ".bus_shit" initialiser to capture a non-standard platform-specific ECAM bus shift value. Standard values otherwise defined in the PCI Express Specification are available in the include/linux/pci-ecam.h. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/pci-thunder-pem.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-thunder-pem.c b/drivers/pci/controller/pci-thunder-pem.c index 3f847969143e..1a3f70ac61fc 100644 --- a/drivers/pci/controller/pci-thunder-pem.c +++ b/drivers/pci/controller/pci-thunder-pem.c @@ -19,6 +19,15 @@ #define PEM_CFG_WR 0x28 #define PEM_CFG_RD 0x30 +/* + * Enhanced Configuration Access Mechanism (ECAM) + * + * N.B. This is a non-standard platform-specific ECAM bus shift value. For + * standard values defined in the PCI Express Base Specification see + * include/linux/pci-ecam.h. + */ +#define THUNDER_PCIE_ECAM_BUS_SHIFT 24 + struct thunder_pem_pci { u32 ea_entry[3]; void __iomem *pem_reg_base; @@ -404,7 +413,7 @@ static int thunder_pem_acpi_init(struct pci_config_window *cfg) } const struct pci_ecam_ops thunder_pem_ecam_ops = { - .bus_shift = 24, + .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT, .init = thunder_pem_acpi_init, .pci_ops = { .map_bus = pci_ecam_map_bus, @@ -441,7 +450,7 @@ static int thunder_pem_platform_init(struct pci_config_window *cfg) } static const struct pci_ecam_ops pci_thunder_pem_ops = { - .bus_shift = 24, + .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT, .init = thunder_pem_platform_init, .pci_ops = { .map_bus = pci_ecam_map_bus, From patchwork Sun Nov 29 23:07:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Patchwork-Id: 11939405 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77A78C71155 for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F4A62224A for ; Sun, 29 Nov 2020 23:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727691AbgK2XId (ORCPT ); Sun, 29 Nov 2020 18:08:33 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44538 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbgK2XId (ORCPT ); Sun, 29 Nov 2020 18:08:33 -0500 Received: by mail-wr1-f68.google.com with SMTP id 64so13064696wra.11 for ; Sun, 29 Nov 2020 15:08:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w7DrLBT8KBYKfbvtR7994XDirbE4jnXzlQLSoJlL9lc=; b=Z14E7mDO1eaRmbZRdiA2D93K66tckvBISHxzDbVb6Z/uL59Ueb+JqDs47RIkbng6Tq MLSoR8ZiCX505+I1qvKSK+czeLoK3nUQg/xeagijmEF//SuVyRmYIdCajQQqwwB1fs1/ aB8nxWwzoPsArDFoNIDhC2newJjn/VHM8rGhrCRbAI4oneCzWDl8y4P/JsCaYDgK+ejs GxHt7LZ1e4z4GndWNKipwVIE6r53PJQMlUtimDL1PfnPoT4/ABPpeZaqzUPq+ZlX9yfc 1XP+07+Wmy6SxJT6DLEId5Ta3oNO8JT7l3TG0XXy7rQpTccNNEvpPSnN3LVoUJLjM8Vy Yf4w== X-Gm-Message-State: AOAM530+Ud6ySUKsS0FLTcNTDwvFQTzYHDpFZUQ9buGcSc1qqPEzTWYB TKFQE+5X1qfZccoBJZ9EP74= X-Google-Smtp-Source: ABdhPJwdjGj7iDsGU1B5WR1LxkaOGB+ic6Eu0jtLWAlHXS2/EdXYuqT/jY33YywMRM935NcuXWVL6A== X-Received: by 2002:a5d:65ca:: with SMTP id e10mr24605112wrw.42.1606691270924; Sun, 29 Nov 2020 15:07:50 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:50 -0800 (PST) From: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 3/5] PCI: iproc: Convert to use the new ECAM constants Date: Sun, 29 Nov 2020 23:07:41 +0000 Message-Id: <20201129230743.3006978-4-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Change interface of the function iproc_pcie_map_ep_cfg_reg() so that use of PCI_SLOT() and PCI_FUNC() macros and most of the local ECAM-specific constants can be dropped, and the new PCIE_ECAM_OFFSET() macro can be used instead. Use the ALIGN_DOWN() macro to ensure that PCI Express ECAM offset is always 32 bit aligned. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/pcie-iproc.c | 31 ++++++++--------------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 905e93808243..503662380ff8 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -39,16 +40,8 @@ #define CFG_IND_ADDR_MASK 0x00001ffc -#define CFG_ADDR_BUS_NUM_SHIFT 20 -#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 -#define CFG_ADDR_DEV_NUM_SHIFT 15 -#define CFG_ADDR_DEV_NUM_MASK 0x000f8000 -#define CFG_ADDR_FUNC_NUM_SHIFT 12 -#define CFG_ADDR_FUNC_NUM_MASK 0x00007000 -#define CFG_ADDR_REG_NUM_SHIFT 2 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc -#define CFG_ADDR_CFG_TYPE_SHIFT 0 -#define CFG_ADDR_CFG_TYPE_MASK 0x00000003 +#define CFG_ADDR_CFG_TYPE_1 1 #define SYS_RC_INTX_MASK 0xf @@ -459,19 +452,15 @@ static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus, static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, unsigned int busno, - unsigned int slot, - unsigned int fn, + unsigned int devfn, int where) { u16 offset; u32 val; /* EP device access */ - val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | - (slot << CFG_ADDR_DEV_NUM_SHIFT) | - (fn << CFG_ADDR_FUNC_NUM_SHIFT) | - (where & CFG_ADDR_REG_NUM_MASK) | - (1 & CFG_ADDR_CFG_TYPE_MASK); + val = ALIGN_DOWN(PCIE_ECAM_OFFSET(busno, devfn, where), 4) | + CFG_ADDR_CFG_TYPE_1; iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); @@ -574,8 +563,6 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { struct iproc_pcie *pcie = iproc_data(bus); - unsigned int slot = PCI_SLOT(devfn); - unsigned int fn = PCI_FUNC(devfn); unsigned int busno = bus->number; void __iomem *cfg_data_p; unsigned int data; @@ -590,7 +577,7 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, return ret; } - cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); + cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); if (!cfg_data_p) return PCIBIOS_DEVICE_NOT_FOUND; @@ -631,13 +618,11 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, int busno, unsigned int devfn, int where) { - unsigned slot = PCI_SLOT(devfn); - unsigned fn = PCI_FUNC(devfn); u16 offset; /* root complex access */ if (busno == 0) { - if (slot > 0 || fn > 0) + if (PCIE_ECAM_DEVFN(devfn) > 0) return NULL; iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, @@ -649,7 +634,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, return (pcie->base + offset); } - return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); + return iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); } static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, From patchwork Sun Nov 29 23:07:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Patchwork-Id: 11939407 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F88CC71156 for ; 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Sun, 29 Nov 2020 15:07:52 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:52 -0800 (PST) From: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 4/5] PCI: vmd: Update type of the __iomem pointers Date: Sun, 29 Nov 2020 23:07:42 +0000 Message-Id: <20201129230743.3006978-5-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use "void __iomem" instead "char __iomem" pointer type when working with the accessor functions (with names like readb() or writel(), etc.) to better match a given accessor function signature where commonly the address pointing to an I/O memory region would be a "void __iomem" pointer. Related: https://lwn.net/Articles/102232/ Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński Reviewed-by: Jon Derrick --- drivers/pci/controller/vmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 1361a79bd1e7..59fa9a94860f 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -95,7 +95,7 @@ struct vmd_dev { struct pci_dev *dev; spinlock_t cfg_lock; - char __iomem *cfgbar; + void __iomem *cfgbar; int msix_count; struct vmd_irq_list *irqs; @@ -326,7 +326,7 @@ static void vmd_remove_irq_domain(struct vmd_dev *vmd) } } -static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, +static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, unsigned int devfn, int reg, int len) { unsigned int busnr_ecam = bus->number - vmd->busn_start; @@ -346,7 +346,7 @@ static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, int len, u32 *value) { struct vmd_dev *vmd = vmd_from_bus(bus); - char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); + void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); unsigned long flags; int ret = 0; @@ -381,7 +381,7 @@ static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, int len, u32 value) { struct vmd_dev *vmd = vmd_from_bus(bus); - char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); + void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); unsigned long flags; int ret = 0; From patchwork Sun Nov 29 23:07:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= X-Patchwork-Id: 11939409 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCDB7C64E90 for ; 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Sun, 29 Nov 2020 15:07:54 -0800 (PST) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id d2sm24831005wrn.43.2020.11.29.15.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 15:07:53 -0800 (PST) From: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH v6 5/5] PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c Date: Sun, 29 Nov 2020 23:07:43 +0000 Message-Id: <20201129230743.3006978-6-kw@linux.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201129230743.3006978-1-kw@linux.com> References: <20201129230743.3006978-1-kw@linux.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Removed unused ".bus_shift" initialisers from pci-xgene.c as xgene_pcie_map_bus() did not use these. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/pci-xgene.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c index 8e0db84f089d..85e7c98265e8 100644 --- a/drivers/pci/controller/pci-xgene.c +++ b/drivers/pci/controller/pci-xgene.c @@ -257,7 +257,6 @@ static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) } const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { - .bus_shift = 16, .init = xgene_v1_pcie_ecam_init, .pci_ops = { .map_bus = xgene_pcie_map_bus, @@ -272,7 +271,6 @@ static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) } const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { - .bus_shift = 16, .init = xgene_v2_pcie_ecam_init, .pci_ops = { .map_bus = xgene_pcie_map_bus,