From patchwork Mon Nov 30 04:05:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11939681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1805C63777 for ; Mon, 30 Nov 2020 04:06:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5CCD820657 for ; Mon, 30 Nov 2020 04:06:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="q1UIqqBW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5CCD820657 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:53914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kjaSl-0007oH-9u for qemu-devel@archiver.kernel.org; Sun, 29 Nov 2020 23:06:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kjaRW-0006oF-9t; Sun, 29 Nov 2020 23:05:38 -0500 Received: from mail-io1-xd41.google.com ([2607:f8b0:4864:20::d41]:37341) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kjaRU-0001Vi-Ji; Sun, 29 Nov 2020 23:05:37 -0500 Received: by mail-io1-xd41.google.com with SMTP id k3so2512532ioq.4; Sun, 29 Nov 2020 20:05:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=an0/kxvJGr8CHzaGma67N3U3miPtoKBKBFeQIvPK02E=; b=q1UIqqBWr8+8+tNcpvrA6WaJchoRC2GKV26ThMztTKdyMEl4h9hbhO/vRU+THFVD4i x1eNHFLdB9rXwCcpfsrBJjzPIVcY/3z4sWS64BWhAlaQrQLuIQPVU5c41pbohHPJ9LE8 LTVaOqbagW7WgEslhtlO6Ql1xpxdk13sg4pS5RYF/I2cC7ou5ytbgkMZHH03qHDg/+j+ AHcr1IXZ15fEsXDW9O7dF5j4kzBEgCWaHTgtkBsS16Re1wSv9PBbEIfCX8ynVgAB4KsM D6leiixHfsqEw6GENALt44OATF8yMan6I8fK5FsHmPOsbQhJua0WhKhSMqfI3TmFFjC8 txaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=an0/kxvJGr8CHzaGma67N3U3miPtoKBKBFeQIvPK02E=; b=BwepGGVR4xuQ+Sd25w1EeX6dp++IXHO+sOsoG5lB9lJ9lqIxfgxoAaRBKOndmiVD/S H7wqLj4Gcw42c2X0YQfsiWBUqCw2A8g33mzSSRJmVQ4zrQG6vQjNhqHjAJWQd3ABpdpT atDihF1wT1l2+5xmFSZOY4WRXpt1Aq/Imq2elJMvMm0nhIlwm/pBsud7LW3AxgUh3cBC UfmHdKFugUXC+KMZFgr0e5YbA088QZwB1fLh4YqkgqWMJbwDmV0pFRwiC5yFO/V56lZZ mqCLhD3mhSBnyzT04LmIlDTXBfgvMmKZFarpdu3iJZktsw/lFUtl9kfeWRI728/XxH6Q koVQ== X-Gm-Message-State: AOAM531Ur4EBpOtTVmf7gHvocXkg4GaF7IYU/rOoXNwNcli3SpOqdoAQ yxhdgSWk2VkjseakVngytwM= X-Google-Smtp-Source: ABdhPJwM0BVyxyZ1HMH6cL2QDvedatAHKAIhZh0x+vdqGNPlBvqzuRt8km1IlGfTr1cfWVpvMjs0rg== X-Received: by 2002:a5d:8446:: with SMTP id w6mr14460191ior.138.1606709135200; Sun, 29 Nov 2020 20:05:35 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id p18sm2119828ile.27.2020.11.29.20.05.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Nov 2020 20:05:34 -0800 (PST) From: Bin Meng To: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Mon, 30 Nov 2020 12:05:23 +0800 Message-Id: <1606709124-80741-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 Received-SPF: pass client-ip=2607:f8b0:4864:20::d41; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/ssi/imx_spi.c | 4 ++-- include/hw/ssi/imx_spi.h | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae..e605049 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f..eeaf49b 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; From patchwork Mon Nov 30 04:05:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 11939683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97563C64E8A for ; Mon, 30 Nov 2020 04:07:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07E8C20657 for ; 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[147.11.124.94]) by smtp.gmail.com with ESMTPSA id p18sm2119828ile.27.2020.11.29.20.05.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Nov 2020 20:05:38 -0800 (PST) From: Bin Meng To: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() Date: Mon, 30 Nov 2020 12:05:24 +0800 Message-Id: <1606709124-80741-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606709124-80741-1-git-send-email-bmeng.cn@gmail.com> References: <1606709124-80741-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::d43; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd43.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xuzhou Cheng , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, during which CS lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes c906a3a01582: ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Acked-by: Alistair Francis --- hw/ssi/imx_spi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049..85c172e 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -231,6 +231,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + int i; DPRINTF("\n"); @@ -243,6 +244,10 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_update_irq(s); + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length = 0; }