From patchwork Mon Nov 30 13:10:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6D22C64E8A for ; Mon, 30 Nov 2020 13:14:50 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5F58620825 for ; Mon, 30 Nov 2020 13:14:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="JOjFUKBY"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="GdTnAdX9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5F58620825 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=nXACTGuP6LJqECrqrVAixV4pdNqFGqCqoJ7DVF6ct6o=; b=JOjFUKBY0WpoM9irlvrqlfxWu Rw+thhGC2dNGfzYsjwH+EH9/eyhQc9NeAB+U0JCpU2sdG8x2xMqm1ZSxM8MZemB0JeJR8lyQlA+LG lNgEs4vXzwD2MAdT5rldel6eadfvrFKif+x5oF0d8OlJuLV3Aekresmg9k6opTbaNWENZfKiF62Nr 0QlBXusWKPLpPzTAxqtbCkbiMZBSOGiGaXTuM83b0IU/YEs/EPIy85NTCcBrhmpQQR9t+4FdFpTyF U7vCA/88ymtTWG8DVhYp1EEWlwtLJo4Yhqta7oVqgNYnKDt2TH7uUHr4hrIVWYZCc51A7QCpzHIYI pnvO3x0Mg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjixS-00057y-VJ; Mon, 30 Nov 2020 13:11:10 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjixI-000550-8j for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2020 13:11:01 +0000 Received: by mail-pl1-x62b.google.com with SMTP id s2so6434752plr.9 for ; Mon, 30 Nov 2020 05:10:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=66bIbZIMyYy2aQ1+PNHmZ6rTWFoZDMO1KzGC89/vZyE=; b=GdTnAdX9F8W8qDdgb8euxuSQVdabwSLXIb5t7PUvLLZrWinfSjCqKxreDd+2Klo9kY buosYpZqM1Ol0MZmzneIS39JMkyfbFz7SzMTzCQjXsi/xQB7YOXTckAVmoGd5WUHFTa4 eJUf2CdeEa5rVAlg3JbjevfrD02CcUskuQg0o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=66bIbZIMyYy2aQ1+PNHmZ6rTWFoZDMO1KzGC89/vZyE=; b=Spz979XTYA+75aHDlSENDViapembvxzBqHKWQp7q7M8j/ceQnhXVZ73E9p7Wf/agk4 Us2c1csyF578OIdjLrL7saisxDpIxMpFMN3voYO2FGLPWlV8W7BbCpgd92WRYLx8Y/oc CAN6sW2fXMi/3mWynquaLKohXs073L9hIY+R4Z22J2jtvhZHyE+mQsr940deYDD5bIX9 01U/AJ9VVpnxqObh8CwUROu4TOSydkr+/s1gZd4OJPBk4Yp+VyB5d/dYM1DYMWmuD3Nh KMZtJbgDGGDibyuJH33l9ETKqpDCXIHTrvYiEKp3/KGi+13yoC6mJ3uZGxW42y7hn2hz Q5zg== X-Gm-Message-State: AOAM531D2GO6O82FqwlaieKTZ/ANYeqYZ1iBhIIlBAyCImN5J27G1lpi 4dLIZsFKzA3kfAoVZr4gYiu8vQ== X-Google-Smtp-Source: ABdhPJy/vEeiJjPZKJDVRM9cViVIu8FP89iPKQ41rcgsVoY6HMn0FcCPUSI9RrJ+vkesBYf4n4MTUw== X-Received: by 2002:a17:90a:7e8e:: with SMTP id j14mr2229217pjl.60.1606741857634; Mon, 30 Nov 2020 05:10:57 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:10:57 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/9] dt-bindings: mstar: Add binding details for mstar, smpctrl Date: Mon, 30 Nov 2020 22:10:39 +0900 Message-Id: <20201130131047.2648960-2-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081100_341095_025B9479 X-CRM114-Status: GOOD ( 16.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds a YAML description of the smpctrl node needed by the platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. Signed-off-by: Daniel Palmer --- .../bindings/arm/mstar/mstar,smpctrl.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml new file mode 100644 index 000000000000..a102287b5c88 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC SMP control registers + +maintainers: + - Daniel Palmer + +description: | + MStar/SigmaStar's Armv7 SoCs that have more than one processor + have a region of registers that allow setting the boot address + and a magic number that allows secondary processors to leave + the loop they are parked in by the boot ROM. + +properties: + compatible: + items: + - const: mstar,smpctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smpctrl@204000 { + compatible = "mstar,smpctrl"; + reg = <0x204000 0x200>; + }; From patchwork Mon Nov 30 13:10:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23029C64E7B for ; Mon, 30 Nov 2020 13:16:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 983ED20708 for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:10:59 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/9] dt-bindings: vendor-prefixes: Add honestar vendor prefix Date: Mon, 30 Nov 2020 22:10:40 +0900 Message-Id: <20201130131047.2648960-3-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081102_492566_6AA4C359 X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add prefix for Honestar Technologies Co., Ltd. Signed-off-by: Daniel Palmer --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..a6cf2cef6f89 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -451,6 +451,8 @@ patternProperties: description: Holt Integrated Circuits, Inc. "^honeywell,.*": description: Honeywell + "^honestar,.*": + description: Honestar Technologies Co., Ltd. "^hoperun,.*": description: Jiangsu HopeRun Software Co., Ltd. "^hp,.*": From patchwork Mon Nov 30 13:10:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8E4AC64E7B for ; Mon, 30 Nov 2020 13:16:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 724522065D for ; Mon, 30 Nov 2020 13:16:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="GTzWA/W/"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="qJhZakmL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 724522065D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Iv2dFpDgOAl3BTUo6ULyserh49twc+9xcpLAcNK/jo4=; b=GTzWA/W/qnjWSRAKr0ny9s89n Xybupb3DKwZ1hlID/eOK216FmZ8w/myu90Ldx010EFz+54uRHA/eLax0aM+kvKeJMXRcrJcaQKzJw RGQoEgKE7LKmmfITqRZ0x3TnENHqb2Uf+fhF/npm+XavXyTdcAcgoYO1jC5pubZjqlr/HYDFI8YkB bAkPabc5OgdeoVhBK3rMZn0ZaSO8B5LBscl4IqjoKW+2mchvHrgAWYX+zZTqFCpewBM9z1Q6SK6M1 /0IBo/7PpkpB41DLbBoIiDbtden7QFLMVMwDRQ30EuOyAHZjzDLGEEJl3qVWu7JsE06s9PJD6e7M1 F/O1nUtOw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjixj-0005Ek-8r; Mon, 30 Nov 2020 13:11:27 +0000 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjixO-00056y-9h for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2020 13:11:07 +0000 Received: by mail-pl1-x644.google.com with SMTP id p6so6458288plr.7 for ; Mon, 30 Nov 2020 05:11:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TdRqXYI9+LXautyFSgQZPVbiKxi/AYNw4/5pXTCk/R4=; b=qJhZakmLX71Ow/Q4navBAsIvIv0yWS8fiCX2fxNBsvczVnYVYxXyvoVV3eTCIDX4QV J9J8nzmhgoffXp1hzkJykZz3J5K+4ovjA0BxL7ZIKhRmifFJ+Vhd0j1k0C/Dk6QZOL0x HHGqADfpDXBcBWjsCM77K/AOOaza45UXAaIPw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TdRqXYI9+LXautyFSgQZPVbiKxi/AYNw4/5pXTCk/R4=; b=dzhGaK7rwJSfi85e+1cqG5zC+/Ijr3FKib4J+BRapdCSelNmLIUNJ3g1cQ+IWSA24I W5UgBOFgTO8iUQuyFfrPHmDpBkSPz0Lclz2PUgvudwoGmPmuggWdMeL7nhzg6KfUYGOi eNnubtXhrftOT6R1QhkC9Xm71TKknnRPVTuqvjNq4eOvkGz6CqL1YR6Oe9Qx3ruSd5O9 wMZID5oq6d1xyTsVhDeKa6spA1D9NuMUUUJaBay1W5BnCxpOfnPavNzv4PAG1wjNvjNf mNzhvb2zyXLDsFAkPTSVm0Wij/ScBMYY1zQ9JKd1ktk8UQ1ZzCUrCncrUtxqAafTFEbE f32A== X-Gm-Message-State: AOAM531hTZvBcg8qeHjYpOLGCKj/iKTqK/ewIBQ2+UGBeBqn7dProH89 8nDED/Vx9brLBy1agjbD+C768A== X-Google-Smtp-Source: ABdhPJwXoKlEzAdbPmg2u4U48+mToekmbmgjgbgdvXRcRwal5v3eSx9A94rxco97SG5qv3e+9ya4QQ== X-Received: by 2002:a17:90a:4093:: with SMTP id l19mr3226303pjg.218.1606741863990; Mon, 30 Nov 2020 05:11:03 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:01 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/9] dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards Date: Mon, 30 Nov 2020 22:10:41 +0900 Message-Id: <20201130131047.2648960-4-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081106_376680_639D62D0 X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Honestar SSD201_HT_V2 is a full size devkit for the SigmaStar SSD201 or SSD202D (they are pin compatible). Currently only the SSD202D version is supported as that's the one I have. Link: https://linux-chenxing.org/infinity2/ssd201_ht_v2/ Signed-off-by: Daniel Palmer --- Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index 7c787405bb2f..61d08c473eb8 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -20,6 +20,12 @@ properties: - thingyjp,breadbee-crust # thingy.jp BreadBee Crust - const: mstar,infinity + - description: infinity2m boards + items: + - enum: + - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit + - const: mstar,infinity2m + - description: infinity3 boards items: - enum: From patchwork Mon Nov 30 13:10:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61A86C64E8A for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:05 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] ARM: mstar: Add infinity2m support Date: Mon, 30 Nov 2020 22:10:42 +0900 Message-Id: <20201130131047.2648960-5-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081110_563354_B4136263 X-CRM114-Status: GOOD ( 18.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The infinity2m series of chips are like the other Mstar/Sigmastar chips in that they have a Cortex A7 system with DDR memory integrated in a single package. The infinity2m chips are intended for recording the incoming streams from IP cameras. So instead of video encoders they have video decoders, instead of a camera interface they have display hardware and so on. Aside from the above points the big difference about these chips is that they include a second Cortex A7 core. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/mstar-v7.dtsi | 2 +- arch/arm/mach-mstar/mstarv7.c | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi new file mode 100644 index 000000000000..02adb9fe9d3c --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 07fc46c7b4d4..2862b32c7f63 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -13,7 +13,7 @@ / { #size-cells = <1>; interrupt-parent = <&gic>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 81a4cbcab206..1aa748fa006e 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -35,6 +35,7 @@ static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { "mstar,infinity", + "mstar,infinity2m", "mstar,infinity3", "mstar,mercury5", NULL, From patchwork Mon Nov 30 13:10:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 665F8C64E90 for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:08 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/9] ARM: mstar: Add common dtsi for SSD201/SSD202D Date: Mon, 30 Nov 2020 22:10:43 +0900 Message-Id: <20201130131047.2648960-6-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081111_665596_40053357 X-CRM114-Status: GOOD ( 15.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SSD201 and SSD202D are basically the same chip with a different DDR die packaged (64MB DDR2 or 128MB DDR3). This patch adds a shared dtsi for the common parts of these chips like gpio, pinctrl etc. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi new file mode 100644 index 000000000000..0811220f0a79 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m.dtsi" From patchwork Mon Nov 30 13:10:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117F7C71156 for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:11 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/9] ARM: mstar: Add chip level dtsi for SSD202D Date: Mon, 30 Nov 2020 22:10:44 +0900 Message-Id: <20201130131047.2648960-7-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081114_288418_9B3CCA47 X-CRM114-Status: GOOD ( 14.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a chip level dtsi for the SigmaStar SSD202D Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi new file mode 100644 index 000000000000..176e10a29896 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m-ssd20xd.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x20000000 0x8000000>; + }; +}; From patchwork Mon Nov 30 13:10:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A687C64E8A for ; Mon, 30 Nov 2020 13:15:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DED232073C for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:13 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 7/9] ARM: mstar: Add dts for Honestar ssd201htv2 Date: Mon, 30 Nov 2020 22:10:45 +0900 Message-Id: <20201130131047.2648960-8-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081117_003406_DA0E2E60 X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a dts for the Honestar ssd201htv2 devkit. This is for the board populated with a SSD202D. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/Makefile | 1 + .../mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..ccbf44b6f32a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1372,6 +1372,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-ssd201htv2.dtb \ mstar-infinity3-msc313e-breadbee.dtb \ mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts new file mode 100644 index 000000000000..5d81641414a2 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "SSD201_HT_V2"; + compatible = "honestar,ssd201htv2", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; From patchwork Mon Nov 30 13:10:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 526ABC64E7B for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:16 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi Date: Mon, 30 Nov 2020 22:10:46 +0900 Message-Id: <20201130131047.2648960-9-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081120_592131_5B348A97 X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the smpctrl registers to the infinity2m dtsi so that the second CPU can be enabled on chips in this family. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 02adb9fe9d3c..85e178368ba4 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -13,3 +13,11 @@ cpu1: cpu@1 { reg = <0x1>; }; }; + +&riu { + smpctrl@204000 { + compatible = "mstar,smpctrl"; + reg = <0x204000 0x200>; + status = "okay"; + }; +}; From patchwork Mon Nov 30 13:10:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11940437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03C24C64E8A for ; Mon, 30 Nov 2020 13:15:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E25720708 for ; Mon, 30 Nov 2020 13:15:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="eGyPCyqm"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="NOERfF7e" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E25720708 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dBmSKMQ7EMtN9+9kqAZfmJeUSVXrQdAG85PEpfhJVFM=; b=eGyPCyqmDttdxbMCYg7oiqypN 6zxFcNh0oVP6o6EQ+o2aHrXhV4PpY76zmQQJu4zS9fJN9wfBOvhwHO8BiNy1pTf+bhLhTe6ppjWjn IA7nzMwfxLslHWpDX4ySS5/kDAe9hW9qgYFxMWrxJgaIUQEqIxbpi6bCWg6AMrIo6HkRiapZp8Las dd4Z2xjGJumrt7IwXykBkM90SAAg49R3IBlbKmm2MqYc4ALJXgvtzx0UgyXoBamtnxNdlymgHnQuy b44q+ZU4lP7QccDGG8i1/iHyY3Q3arToegBy0JWs8VmMMFCNa2Fh8y7Ogldj3QB9l0ZUVwYeqWv6t xGbMuUGXg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjiyK-0005Pz-Vq; Mon, 30 Nov 2020 13:12:05 +0000 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjixe-0005CO-1u for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2020 13:11:24 +0000 Received: by mail-pj1-x1044.google.com with SMTP id r9so1305026pjl.5 for ; Mon, 30 Nov 2020 05:11:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F4b6Mz+meeIOWiwdpvVizNGtENxtsbORSHHjjSCrlas=; b=NOERfF7egowMV6omqbGCYcnTmO++yhypJfIN0zzFCBLOwPjW5dSmvG0jSgPxeAESWL 9acj1SCmIXtpuCB2Z1uvcFa6v6k8VO8nec0r6OsyQX4L1rUrsewKlJ9uuqivdPfvvo5v MCSexCFH5DnPtbgd0TfpUvYMix7Q0BxgQoAjg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4b6Mz+meeIOWiwdpvVizNGtENxtsbORSHHjjSCrlas=; b=F+fp9/ycCoec/T6XTmg6EIcQDcX7Bp3NxyIdhCqHAh/OriWJFK2WcbgvG8zJUq8G9J JLLCuZU9/FRioQ09lJ8k0hlcGwFG8d9QmK4ytGT0weRw5Ic2336QdU/xV4BXYDml9eY6 x4DB5RdyfR/EUApPm8juaukhBbXEfWQSnxNjr1jcnalREeBFuBmnkMH5P5Ly+pEWVnZG xDdY0BS9UE8A55tAzT/VCADqFxBgrwMeOUSyIrX6f5bCmJdnTGv+Ah0GMK6nIpBMSshJ TO8a2Oq+Dc+PD9WBEwkS6dtAAc9B8wNsMVuRBsMl8b4S/KTc3qjPShRuZl9BeuOgvIIA yM1w== X-Gm-Message-State: AOAM5323vNyy++wG5UMOVKPcpEuQeTwGMs6yBN5rp1G3hi/+tWFwbLtu JhoHQccNI5Vcg0TuQnMMqHoNLTYlOCirqQ== X-Google-Smtp-Source: ABdhPJytNtiSFjUBa/8hP6fMqYnvCTlKseq0Z9MVhm7I5h2NQTR5XgRtzFuTCSl6si+IwlkEQh6IOw== X-Received: by 2002:a17:90a:940c:: with SMTP id r12mr25793348pjo.201.1606741879985; Mon, 30 Nov 2020 05:11:19 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:19 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 9/9] ARM: mstar: SMP support Date: Mon, 30 Nov 2020 22:10:47 +0900 Message-Id: <20201130131047.2648960-10-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081122_266315_983AF257 X-CRM114-Status: GOOD ( 21.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds SMP support for MStar/Sigmastar chips that have a second core like those in the infinity2m family. So far only single and dual core chips have been found so this does the bare minimum to boot the second core. From what I can tell not having the "holding pen" code to handle multiple cores is fine if there is only one core the will get booted. This might need to be reconsidered if chips with more cores turn up. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/mstarv7.c | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 1aa748fa006e..23fe47a8f1a5 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -31,6 +31,13 @@ #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) +#ifdef CONFIG_SMP +#define MSTARV7_CPU1_BOOT_ADDR_HIGH 0x4c +#define MSTARV7_CPU1_BOOT_ADDR_LOW 0x50 +#define MSTARV7_CPU1_UNLOCK 0x58 +#define MSTARV7_CPU1_UNLOCK_MAGIC 0xbabe +#endif + static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { @@ -63,6 +70,46 @@ static void mstarv7_mb(void) } } +#ifdef CONFIG_SMP +static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + struct device_node *np; + u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm); + void __iomem *smpctrl = 0; + + /* + * right now we don't know how to boot anything except + * cpu 1. + */ + if (cpu != 1) + return -EINVAL; + + np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl"); + smpctrl = of_iomap(np, 0); + + if (!smpctrl) + return -ENODEV; + + /* set the boot address for the second cpu */ + writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW); + writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH); + + /* unlock the second cpu */ + writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK); + + /* and away we go...*/ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + iounmap(smpctrl); + + return 0; +} + +struct smp_operations __initdata mstarv7_smp_ops = { + .smp_boot_secondary = mstarv7_boot_secondary, +}; +#endif + static void __init mstarv7_init(void) { struct device_node *np; @@ -78,4 +125,7 @@ static void __init mstarv7_init(void) DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") .dt_compat = mstarv7_board_dt_compat, .init_machine = mstarv7_init, +#ifdef CONFIG_SMP + .smp = smp_ops(mstarv7_smp_ops), +#endif MACHINE_END