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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w21sm2036918lff.280.2020.12.04.12.18.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2020 12:18:17 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Subject: [PATCH v3 1/6] dt-bindings: remoteproc: Add binding doc for PRU cores in the PRU-ICSS Date: Fri, 4 Dec 2020 21:18:02 +0100 Message-Id: <20201204201807.14716-2-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> References: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_151821_065312_3B54E977 X-CRM114-Status: GOOD ( 18.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, praneeth@ti.com, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suman Anna The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS or simply PRUSS) on various TI SoCs consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. The K3 AM65x amd J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG IP on AM65x SoCs has two PRU cores, two auxiliary custom PRU cores called Real Time Units (RTUs). The K3 AM65x SR2.0 and J721E SoCs have a revised version of the ICSSG IP, and include two additional custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs). This patch adds the bindings for these PRU cores. The binding covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; Keystone 2 architecture based 66AK2G SoC; and the K3 architecture based SoCs - AM65x and J721E. The Davinci based OMAPL138 SoCs will be covered in a future patch. Co-developed-by: Roger Quadros Signed-off-by: Roger Quadros Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v2->v3: - no changes v1->v2: - fix below yamllint warnings: ./Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml:37:6: [warning] wrong indentation: expected 6 but found 5 (indentation) ./Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml:92:2: [warning] wrong indentation: expected 2 but found 1 (indentation) --- .../bindings/remoteproc/ti,pru-rproc.yaml | 214 ++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml new file mode 100644 index 000000000000..63071eef1632 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Programmable Realtime Unit (PRU) cores + +maintainers: + - Suman Anna + +description: | + Each Programmable Real-Time Unit and Industrial Communication Subsystem + (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called + Programmable Real-Time Units (PRUs), each represented by a node. Each PRU + core has a dedicated Instruction RAM, Control and Debug register sets, and + use the Data RAMs present within the PRU-ICSS for code execution. + + The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary + PRU cores called RTUs with slightly different IP integration. The K3 SoCs + containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two + auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU + or Tx_PRU core can also be used independently like a PRU, or alongside a + corresponding PRU core to provide/implement auxiliary functionality/support. + + Each PRU, RTU or Tx_PRU core node should be defined as a child node of the + corresponding PRU-ICSS node. Each node can optionally be rendered inactive by + using the standard DT string property, "status". + + Please see the overall PRU-ICSS bindings document for additional details + including a complete example, + Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml + +properties: + compatible: + enum: + - ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only) + - ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only) + - ti,am5728-pru # for AM57xx SoC family + - ti,k2g-pru # for 66AK2G SoC family + - ti,am654-pru # for PRUs in K3 AM65x SoC family + - ti,am654-rtu # for RTUs in K3 AM65x SoC family + - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs + - ti,j721e-pru # for PRUs in K3 J721E SoC family + - ti,j721e-rtu # for RTUs in K3 J721E SoC family + - ti,j721e-tx-pru # for Tx_PRUs in K3 J721E SoC family + + reg: + items: + - description: Address and Size of the PRU Instruction RAM + - description: Address and Size of the PRU CTRL sub-module registers + - description: Address and Size of the PRU Debug sub-module registers + + reg-names: + items: + - const: iram + - const: control + - const: debug + + firmware-name: + description: | + Should contain the name of the default firmware image + file located on the firmware search path. + +if: + properties: + compatible: + enum: + - ti,am654-rtu + - ti,j721e-rtu +then: + properties: + $nodename: + pattern: "^rtu@[0-9a-f]+$" +else: + if: + properties: + compatible: + enum: + - ti,am654-tx-pru + - ti,j721e-tx-pru + then: + properties: + $nodename: + pattern: "^txpru@[0-9a-f]+" + else: + properties: + $nodename: + pattern: "^pru@[0-9a-f]+$" + +required: + - compatible + - reg + - reg-names + - firmware-name + +additionalProperties: false + +examples: + - | + /* AM33xx PRU-ICSS */ + pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ + compatible = "ti,sysc-pruss", "ti,sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x300000 0x80000>; + + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pru0: pru@34000 { + compatible = "ti,am3356-pru"; + reg = <0x34000 0x2000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@38000 { + compatible = "ti,am3356-pru"; + reg = <0x38000 0x2000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + }; + }; + + - | + /* AM65x SR2.0 ICSSG */ + #include + + icssg0: icssg@b000000 { + compatible = "ti,am654-icssg"; + reg = <0xb000000 0x80000>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000000 0x80000>; + + icssg0_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pru0_0: pru@34000 { + compatible = "ti,am654-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_0-fw"; + }; + + rtu0_0: rtu@4000 { + compatible = "ti,am654-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_0-fw"; + }; + + tx_pru0_0: txpru@a000 { + compatible = "ti,am654-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_0-fw"; + }; + + pru0_1: pru@38000 { + compatible = "ti,am654-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_1-fw"; + }; + + rtu0_1: rtu@6000 { + compatible = "ti,am654-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_1-fw"; + }; + + tx_pru0_1: txpru@c000 { + compatible = "ti,am654-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_1-fw"; + }; + }; From patchwork Fri Dec 4 20:18:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11952261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84B54C4361B for ; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w21sm2036918lff.280.2020.12.04.12.18.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2020 12:18:18 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Subject: [PATCH v3 2/6] remoteproc: pru: Add a PRU remoteproc driver Date: Fri, 4 Dec 2020 21:18:03 +0100 Message-Id: <20201204201807.14716-3-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> References: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_151820_976744_24884100 X-CRM114-Status: GOOD ( 32.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, praneeth@ti.com, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suman Anna The Programmable Real-Time Unit Subsystem (PRUSS) consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. This patch adds a remoteproc platform driver for managing the individual PRU RISC cores life cycle. The PRUs do not have a unified address space (have an Instruction RAM and a primary Data RAM at both 0x0). The PRU remoteproc driver therefore uses a custom remoteproc core ELF loader ops. The added .da_to_va ops is only used to provide translations for the PRU Data RAMs. This remoteproc driver does not have support for error recovery and system suspend/resume features. Different compatibles are used to allow providing scalability for instance-specific device data if needed. The driver uses a default firmware-name retrieved from device-tree for each PRU core, and the firmwares are expected to be present in the standard Linux firmware search paths. They can also be adjusted by userspace if required through the sysfs interface provided by the remoteproc core. The PRU remoteproc driver uses a client-driven boot methodology: it does _not_ support auto-boot so that the PRU load and boot is dictated by the corresponding client drivers for achieving various usecases. This allows flexibility for the client drivers or applications to set a firmware name (if needed) based on their desired functionality and boot the PRU. The sysfs bind and unbind attributes have also been suppressed so that the PRU devices cannot be unbound and thereby shutdown a PRU from underneath a PRU client driver. The driver currently supports the AM335x, AM437x, AM57xx and 66AK2G SoCs, and support for other TI SoCs will be added in subsequent patches. Co-developed-by: Andrew F. Davis Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v2-v3: Address Mathieu comments: - pru_rproc_load_elf_segments(): use filesz instead of (phdr->p_filesz) and move the check for the !filesz around PT_LOAD check. - pru_rproc_load_elf_segments(): move "skip the memzero.." comment below memcpy. - Add Reviewed-by: tag. v1->v2: - Use PRU_IRAM_ADDR_MASK definition instead of raw 0x3ffff. - Convert 'len' argument from int to size_t type in all *da_to_va. - Return 0 in case of missing .resource_table for pru_rproc_parse_fw() (move the logic from patch #3 where it was corrected). --- drivers/remoteproc/Kconfig | 12 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/pru_rproc.c | 433 +++++++++++++++++++++++++++++++++ 3 files changed, 446 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index d99548fb5dde..3e3865a7cd78 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -125,6 +125,18 @@ config KEYSTONE_REMOTEPROC It's safe to say N here if you're not interested in the Keystone DSPs or just want to use a bare minimum kernel. +config PRU_REMOTEPROC + tristate "TI PRU remoteproc support" + depends on TI_PRUSS + default TI_PRUSS + help + Support for TI PRU remote processors present within a PRU-ICSS + subsystem via the remote processor framework. + + Say Y or M here to support the Programmable Realtime Unit (PRU) + processors on various TI SoCs. It's safe to say N here if you're + not interested in the PRU or if you are unsure. + config QCOM_PIL_INFO tristate diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index da2ace4ec86c..bb26c9e4ef9c 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o +obj-$(CONFIG_PRU_REMOTEPROC) += pru_rproc.o obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c new file mode 100644 index 000000000000..d33392bbd8af --- /dev/null +++ b/drivers/remoteproc/pru_rproc.c @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PRU-ICSS remoteproc driver for various TI SoCs + * + * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author(s): + * Suman Anna + * Andrew F. Davis + * Grzegorz Jaszczyk for Texas Instruments + */ + +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" +#include "remoteproc_elf_helpers.h" + +/* PRU_ICSS_PRU_CTRL registers */ +#define PRU_CTRL_CTRL 0x0000 +#define PRU_CTRL_STS 0x0004 + +/* CTRL register bit-fields */ +#define CTRL_CTRL_SOFT_RST_N BIT(0) +#define CTRL_CTRL_EN BIT(1) +#define CTRL_CTRL_SLEEPING BIT(2) +#define CTRL_CTRL_CTR_EN BIT(3) +#define CTRL_CTRL_SINGLE_STEP BIT(8) +#define CTRL_CTRL_RUNSTATE BIT(15) + +/* PRU Core IRAM address masks */ +#define PRU_IRAM_ADDR_MASK 0x3ffff +#define PRU0_IRAM_ADDR_MASK 0x34000 +#define PRU1_IRAM_ADDR_MASK 0x38000 + +/* PRU device addresses for various type of PRU RAMs */ +#define PRU_IRAM_DA 0 /* Instruction RAM */ +#define PRU_PDRAM_DA 0 /* Primary Data RAM */ +#define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ +#define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ + +/** + * enum pru_iomem - PRU core memory/register range identifiers + * + * @PRU_IOMEM_IRAM: PRU Instruction RAM range + * @PRU_IOMEM_CTRL: PRU Control register range + * @PRU_IOMEM_DEBUG: PRU Debug register range + * @PRU_IOMEM_MAX: just keep this one at the end + */ +enum pru_iomem { + PRU_IOMEM_IRAM = 0, + PRU_IOMEM_CTRL, + PRU_IOMEM_DEBUG, + PRU_IOMEM_MAX, +}; + +/** + * struct pru_rproc - PRU remoteproc structure + * @id: id of the PRU core within the PRUSS + * @dev: PRU core device pointer + * @pruss: back-reference to parent PRUSS structure + * @rproc: remoteproc pointer for this PRU core + * @mem_regions: data for each of the PRU memory regions + * @fw_name: name of firmware image used during loading + */ +struct pru_rproc { + int id; + struct device *dev; + struct pruss *pruss; + struct rproc *rproc; + struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; + const char *fw_name; +}; + +static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) +{ + return readl_relaxed(pru->mem_regions[PRU_IOMEM_CTRL].va + reg); +} + +static inline +void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) +{ + writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); +} + +static int pru_rproc_start(struct rproc *rproc) +{ + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + u32 val; + + dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", + pru->id, (rproc->bootaddr >> 2)); + + val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); + pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + + return 0; +} + +static int pru_rproc_stop(struct rproc *rproc) +{ + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + u32 val; + + dev_dbg(dev, "stopping PRU%d\n", pru->id); + + val = pru_control_read_reg(pru, PRU_CTRL_CTRL); + val &= ~CTRL_CTRL_EN; + pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + + return 0; +} + +/* + * Convert PRU device address (data spaces only) to kernel virtual address. + * + * Each PRU has access to all data memories within the PRUSS, accessible at + * different ranges. So, look through both its primary and secondary Data + * RAMs as well as any shared Data RAM to convert a PRU device address to + * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data + * RAM1 is primary Data RAM for PRU1. + */ +static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len) +{ + struct pruss_mem_region dram0, dram1, shrd_ram; + struct pruss *pruss = pru->pruss; + u32 offset; + void *va = NULL; + + if (len == 0) + return NULL; + + dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0]; + dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1]; + /* PRU1 has its local RAM addresses reversed */ + if (pru->id == 1) + swap(dram0, dram1); + shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2]; + + if (da >= PRU_PDRAM_DA && da + len <= PRU_PDRAM_DA + dram0.size) { + offset = da - PRU_PDRAM_DA; + va = (__force void *)(dram0.va + offset); + } else if (da >= PRU_SDRAM_DA && + da + len <= PRU_SDRAM_DA + dram1.size) { + offset = da - PRU_SDRAM_DA; + va = (__force void *)(dram1.va + offset); + } else if (da >= PRU_SHRDRAM_DA && + da + len <= PRU_SHRDRAM_DA + shrd_ram.size) { + offset = da - PRU_SHRDRAM_DA; + va = (__force void *)(shrd_ram.va + offset); + } + + return va; +} + +/* + * Convert PRU device address (instruction space) to kernel virtual address. + * + * A PRU does not have an unified address space. Each PRU has its very own + * private Instruction RAM, and its device address is identical to that of + * its primary Data RAM device address. + */ +static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len) +{ + u32 offset; + void *va = NULL; + + if (len == 0) + return NULL; + + if (da >= PRU_IRAM_DA && + da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) { + offset = da - PRU_IRAM_DA; + va = (__force void *)(pru->mem_regions[PRU_IOMEM_IRAM].va + + offset); + } + + return va; +} + +/* + * Provide address translations for only PRU Data RAMs through the remoteproc + * core for any PRU client drivers. The PRU Instruction RAM access is restricted + * only to the PRU loader code. + */ +static void *pru_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) +{ + struct pru_rproc *pru = rproc->priv; + + return pru_d_da_to_va(pru, da, len); +} + +/* PRU-specific address translator used by PRU loader. */ +static void *pru_da_to_va(struct rproc *rproc, u64 da, size_t len, bool is_iram) +{ + struct pru_rproc *pru = rproc->priv; + void *va; + + if (is_iram) + va = pru_i_da_to_va(pru, da, len); + else + va = pru_d_da_to_va(pru, da, len); + + return va; +} + +static struct rproc_ops pru_rproc_ops = { + .start = pru_rproc_start, + .stop = pru_rproc_stop, + .da_to_va = pru_rproc_da_to_va, +}; + +static int +pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) +{ + struct device *dev = &rproc->dev; + struct elf32_hdr *ehdr; + struct elf32_phdr *phdr; + int i, ret = 0; + const u8 *elf_data = fw->data; + + ehdr = (struct elf32_hdr *)elf_data; + phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff); + + /* go through the available ELF segments */ + for (i = 0; i < ehdr->e_phnum; i++, phdr++) { + u32 da = phdr->p_paddr; + u32 memsz = phdr->p_memsz; + u32 filesz = phdr->p_filesz; + u32 offset = phdr->p_offset; + bool is_iram; + void *ptr; + + if (phdr->p_type != PT_LOAD || !filesz) + continue; + + dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", + phdr->p_type, da, memsz, filesz); + + if (filesz > memsz) { + dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n", + filesz, memsz); + ret = -EINVAL; + break; + } + + if (offset + filesz > fw->size) { + dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n", + offset + filesz, fw->size); + ret = -EINVAL; + break; + } + + /* grab the kernel address for this device address */ + is_iram = phdr->p_flags & PF_X; + ptr = pru_da_to_va(rproc, da, memsz, is_iram); + if (!ptr) { + dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); + ret = -EINVAL; + break; + } + + memcpy(ptr, elf_data + phdr->p_offset, filesz); + + /* skip the memzero logic performed by remoteproc ELF loader */ + } + + return ret; +} + +/* + * Use a custom parse_fw callback function for dealing with PRU firmware + * specific sections. + */ +static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) +{ + int ret; + + /* load optional rsc table */ + ret = rproc_elf_load_rsc_table(rproc, fw); + if (ret == -EINVAL) + dev_dbg(&rproc->dev, "no resource table found for this fw\n"); + else if (ret) + return ret; + + return 0; +} + +/* + * Compute PRU id based on the IRAM addresses. The PRU IRAMs are + * always at a particular offset within the PRUSS address space. + */ +static int pru_rproc_set_id(struct pru_rproc *pru) +{ + int ret = 0; + + switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { + case PRU0_IRAM_ADDR_MASK: + pru->id = 0; + break; + case PRU1_IRAM_ADDR_MASK: + pru->id = 1; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int pru_rproc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct platform_device *ppdev = to_platform_device(dev->parent); + struct pru_rproc *pru; + const char *fw_name; + struct rproc *rproc = NULL; + struct resource *res; + int i, ret; + const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; + + ret = of_property_read_string(np, "firmware-name", &fw_name); + if (ret) { + dev_err(dev, "unable to retrieve firmware-name %d\n", ret); + return ret; + } + + rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name, + sizeof(*pru)); + if (!rproc) { + dev_err(dev, "rproc_alloc failed\n"); + return -ENOMEM; + } + /* use a custom load function to deal with PRU-specific quirks */ + rproc->ops->load = pru_rproc_load_elf_segments; + + /* use a custom parse function to deal with PRU-specific resources */ + rproc->ops->parse_fw = pru_rproc_parse_fw; + + /* error recovery is not supported for PRUs */ + rproc->recovery_disabled = true; + + /* + * rproc_add will auto-boot the processor normally, but this is not + * desired with PRU client driven boot-flow methodology. A PRU + * application/client driver will boot the corresponding PRU + * remote-processor as part of its state machine either through the + * remoteproc sysfs interface or through the equivalent kernel API. + */ + rproc->auto_boot = false; + + pru = rproc->priv; + pru->dev = dev; + pru->pruss = platform_get_drvdata(ppdev); + pru->rproc = rproc; + pru->fw_name = fw_name; + + for (i = 0; i < ARRAY_SIZE(mem_names); i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + mem_names[i]); + pru->mem_regions[i].va = devm_ioremap_resource(dev, res); + if (IS_ERR(pru->mem_regions[i].va)) { + dev_err(dev, "failed to parse and map memory resource %d %s\n", + i, mem_names[i]); + ret = PTR_ERR(pru->mem_regions[i].va); + return ret; + } + pru->mem_regions[i].pa = res->start; + pru->mem_regions[i].size = resource_size(res); + + dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n", + mem_names[i], &pru->mem_regions[i].pa, + pru->mem_regions[i].size, pru->mem_regions[i].va); + } + + ret = pru_rproc_set_id(pru); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, rproc); + + ret = devm_rproc_add(dev, pru->rproc); + if (ret) { + dev_err(dev, "rproc_add failed: %d\n", ret); + return ret; + } + + dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); + + return 0; +} + +static int pru_rproc_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rproc *rproc = platform_get_drvdata(pdev); + + dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name); + + return 0; +} + +static const struct of_device_id pru_rproc_match[] = { + { .compatible = "ti,am3356-pru", }, + { .compatible = "ti,am4376-pru", }, + { .compatible = "ti,am5728-pru", }, + { .compatible = "ti,k2g-pru", }, + {}, +}; +MODULE_DEVICE_TABLE(of, pru_rproc_match); + +static struct platform_driver pru_rproc_driver = { + .driver = { + .name = "pru-rproc", + .of_match_table = pru_rproc_match, + .suppress_bind_attrs = true, + }, + .probe = pru_rproc_probe, + .remove = pru_rproc_remove, +}; +module_platform_driver(pru_rproc_driver); + +MODULE_AUTHOR("Suman Anna "); +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_AUTHOR("Grzegorz Jaszczyk "); +MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Dec 4 20:18:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11952267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F391DC1B0D9 for ; Fri, 4 Dec 2020 20:20:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7710022B40 for ; Fri, 4 Dec 2020 20:20:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7710022B40 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qUHKc1bACCghy0q/KxdKPOhEILz8phaK+j1L9qQR8kA=; b=OBG1tXqJ7VUvJ6/D9aKEfM9V2 dv5yrw5YZlZd5TwzoceBwiGNRl8ttSWmhAdG030Mqaafo7zs5TC17jjIULPlMAKEgS3LRM7/Ls3XN ivqdY8rvem1sKoxagSrMb/jjTUDlAYBw8zoUJrifDGo7cp/JbtRFpKtwZ5shgE3Oppyq/hGj22Nl8 NL+Fu6o2CvryMitHbCccs3QN8LLu14Exp6I7y8DpNUyjb8sdVHRt40lNHnDpYjNQ+LeDEqQp6QEKA r/i8BuaxUm/AEt2vvw7yYzsnZjIHks4lzaA9twRRYXc32vJXzEaMX9PqQImR0Q78JsQTsVf24Uik5 PqcERMemQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1klHXF-00016G-V5; Fri, 04 Dec 2020 20:18:34 +0000 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1klHX3-00012u-Us for linux-arm-kernel@lists.infradead.org; Fri, 04 Dec 2020 20:18:26 +0000 Received: by mail-lf1-x12d.google.com with SMTP id u19so9382042lfr.7 for ; Fri, 04 Dec 2020 12:18:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Aebq4Z/X+Nr9WpJ3mNo4K1N0OlNLKMXiT5kwsV6RxHU=; b=ZF68vQ4u0T8Ye3WoFbq1snUTda/EUuRSbX3jx/PItOvdMxEim+zkIzSP0oyzWL06ty qdumYxBtYrs/Dekfk4PV9E29UNdPy5gVoCkv1h2XvifGLhAk5owCPDrdrQctVZc69/iK VvZXP2I3ET/e+xPU2gcizbjlKacVQZTEzQPuna+aTfYn+f7BMuzfODbwSdISn90u+Izm ze9Ryfa9iyDf1niKy9Nbp8WJKmM3fpYnj+nZEKqZMDYpgg4gFnfW9u++Uwa84956AyVb +89d++Ucn9z2S+OdGeNeKuhQcoOS2HOMq6oE+wS4rgYLIxp8cYwAYbbCaZ8icdgXo341 Gvpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Aebq4Z/X+Nr9WpJ3mNo4K1N0OlNLKMXiT5kwsV6RxHU=; b=t5gf1SGJrNm9XZDm13+zz0eekdOfEHN49OubqnKiC7mQ2CRtPjEhZbpCoDFexnimIH Vpb30kgISCEXUv7hDFps7qD8GJOoo9Qa4haO/N1FX+UoqzmLHmJ14wpslGwOyK6jkphf GY5WhXHudsdG2lR89t0BvtD2qdsZRIbBCQhUBm5yFs2Bz39xOH24Sd5HKEC6lTVYh2T2 fQYhHRLjZ9UvmN0WO7pFl3Q3DO19AhWHWeS0xkBxIpTXtZQmD5z1PnDiKRSL21bmJwI6 nTm4yzwtXotw1Ht5hNIm/pxiOjFELaN+RQaeYgC67HfgjnGSHyoLZ8DIqCNeDX+GU62V O8IQ== X-Gm-Message-State: AOAM533bgfPUDX0arWR1NZ8kT41NIhksclBkN3U2/XQBfrazsiG5SRfc zBtHPCeK8ERYOeM62LbwU39Fgg== X-Google-Smtp-Source: ABdhPJyBMjWv0xae8uc1WKwxROOr0Bq93BI0hP9fQ4+rFPpLeGAkEz5b5N0H6NQoVO1sjVMpJHRxJA== X-Received: by 2002:a05:6512:3481:: with SMTP id v1mr3763935lfr.113.1607113100409; Fri, 04 Dec 2020 12:18:20 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id w21sm2036918lff.280.2020.12.04.12.18.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2020 12:18:19 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Subject: [PATCH v3 3/6] remoteproc: pru: Add support for PRU specific interrupt configuration Date: Fri, 4 Dec 2020 21:18:04 +0100 Message-Id: <20201204201807.14716-4-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> References: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_151822_067190_BDD4F4CA X-CRM114-Status: GOOD ( 35.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, praneeth@ti.com, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The firmware blob can contain optional ELF sections: .resource_table section and .pru_irq_map one. The second one contains the PRUSS interrupt mapping description, which needs to be setup before powering on the PRU core. To avoid RAM wastage this ELF section is not mapped to any ELF segment (by the firmware linker) and therefore is not loaded to PRU memory. The PRU interrupt configuration is handled within the PRUSS INTC irqchip driver and leverages the system events to interrupt channels and host interrupts mapping configuration. Relevant irq routing information is passed through a special .pru_irq_map ELF section (for interrupts routed to and used by PRU cores) or via the PRU application's device tree node (for interrupts routed to and used by the main CPU). The mappings are currently programmed during the booting/shutdown of the PRU. The interrupt configuration passed through .pru_irq_map ELF section is optional. It varies on specific firmware functionality and therefore have to be unwinded during PRU stop and performed again during PRU start. Co-developed-by: Suman Anna Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v2-v3: Address Mathieu comments: - Because irq_create_fwspec_mapping() returns an unsigned int, convert mapped_irq type to 'unsigned int *'. Due to this change update relevant error path. - Since the num_evts is u8 value and can't be negative drop 'rsc->num_evts < 0' check. Fix checkpatch --strict warning: CHECK: Alignment should match open parenthesis #163: FILE: drivers/remoteproc/pru_rproc.c:165: + dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", + i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); v1->v2: Address Suman comments: - Rework pru_rproc_find_interrupt_map() style: get rid of generic ELF helpers macros usage and stick with elf32_* related structs instead (in order to be consistent with pru_rproc_load_elf_segments() style). - Improve comments and dev_err msgs in pru_rproc_find_interrupt_map(). - Use u8 instead of ssize_t for evt_count. --- drivers/remoteproc/pru_rproc.c | 180 +++++++++++++++++++++++++++++++++ drivers/remoteproc/pru_rproc.h | 46 +++++++++ 2 files changed, 226 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.h diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index d33392bbd8af..4ef59d15d888 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -11,13 +11,16 @@ */ #include +#include #include #include +#include #include #include #include "remoteproc_internal.h" #include "remoteproc_elf_helpers.h" +#include "pru_rproc.h" /* PRU_ICSS_PRU_CTRL registers */ #define PRU_CTRL_CTRL 0x0000 @@ -42,6 +45,8 @@ #define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ #define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ +#define MAX_PRU_SYS_EVENTS 160 + /** * enum pru_iomem - PRU core memory/register range identifiers * @@ -65,6 +70,10 @@ enum pru_iomem { * @rproc: remoteproc pointer for this PRU core * @mem_regions: data for each of the PRU memory regions * @fw_name: name of firmware image used during loading + * @mapped_irq: virtual interrupt numbers of created fw specific mapping + * @pru_interrupt_map: pointer to interrupt mapping description (firmware) + * @pru_interrupt_map_sz: pru_interrupt_map size + * @evt_count: number of mapped events */ struct pru_rproc { int id; @@ -73,6 +82,10 @@ struct pru_rproc { struct rproc *rproc; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; const char *fw_name; + unsigned int *mapped_irq; + struct pru_irq_rsc *pru_interrupt_map; + size_t pru_interrupt_map_sz; + u8 evt_count; }; static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) @@ -86,15 +99,107 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static void pru_dispose_irq_mapping(struct pru_rproc *pru) +{ + while (pru->evt_count--) { + if (pru->mapped_irq[pru->evt_count] > 0) + irq_dispose_mapping(pru->mapped_irq[pru->evt_count]); + } + + kfree(pru->mapped_irq); +} + +/* + * Parse the custom PRU interrupt map resource and configure the INTC + * appropriately. + */ +static int pru_handle_intrmap(struct rproc *rproc) +{ + struct device *dev = rproc->dev.parent; + struct pru_rproc *pru = rproc->priv; + struct pru_irq_rsc *rsc = pru->pru_interrupt_map; + struct irq_fwspec fwspec; + struct device_node *irq_parent; + int i, ret = 0; + + /* not having pru_interrupt_map is not an error */ + if (!rsc) + return 0; + + /* currently supporting only type 0 */ + if (rsc->type != 0) { + dev_err(dev, "unsupported rsc type: %d\n", rsc->type); + return -EINVAL; + } + + if (rsc->num_evts > MAX_PRU_SYS_EVENTS) + return -EINVAL; + + if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) != + pru->pru_interrupt_map_sz) + return -EINVAL; + + pru->evt_count = rsc->num_evts; + pru->mapped_irq = kcalloc(pru->evt_count, sizeof(int), GFP_KERNEL); + if (!pru->mapped_irq) + return -ENOMEM; + + /* + * parse and fill in system event to interrupt channel and + * channel-to-host mapping + */ + irq_parent = of_irq_find_parent(pru->dev->of_node); + if (!irq_parent) { + kfree(pru->mapped_irq); + return -ENODEV; + } + + fwspec.fwnode = of_node_to_fwnode(irq_parent); + fwspec.param_count = 3; + for (i = 0; i < pru->evt_count; i++) { + fwspec.param[0] = rsc->pru_intc_map[i].event; + fwspec.param[1] = rsc->pru_intc_map[i].chnl; + fwspec.param[2] = rsc->pru_intc_map[i].host; + + dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", + i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); + + pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec); + if (!pru->mapped_irq[i]) { + dev_err(dev, "failed to get virq\n"); + ret = pru->mapped_irq[i]; + goto map_fail; + } + } + + return ret; + +map_fail: + pru_dispose_irq_mapping(pru); + + return ret; +} + static int pru_rproc_start(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; u32 val; + int ret; dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", pru->id, (rproc->bootaddr >> 2)); + ret = pru_handle_intrmap(rproc); + /* + * reset references to pru interrupt map - they will stop being valid + * after rproc_start returns + */ + pru->pru_interrupt_map = NULL; + pru->pru_interrupt_map_sz = 0; + if (ret) + return ret; + val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); pru_control_write_reg(pru, PRU_CTRL_CTRL, val); @@ -113,6 +218,10 @@ static int pru_rproc_stop(struct rproc *rproc) val &= ~CTRL_CTRL_EN; pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + /* dispose irq mapping - new firmware can provide new mapping */ + if (pru->mapped_irq) + pru_dispose_irq_mapping(pru); + return 0; } @@ -273,12 +382,70 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) return ret; } +static const void * +pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw) +{ + struct elf32_shdr *shdr, *name_table_shdr; + const char *name_table; + const u8 *elf_data = fw->data; + struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data; + u16 shnum = ehdr->e_shnum; + u16 shstrndx = ehdr->e_shstrndx; + int i; + + /* first, get the section header */ + shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff); + /* compute name table section header entry in shdr array */ + name_table_shdr = shdr + shstrndx; + /* finally, compute the name table section address in elf */ + name_table = elf_data + name_table_shdr->sh_offset; + + for (i = 0; i < shnum; i++, shdr++) { + u32 size = shdr->sh_size; + u32 offset = shdr->sh_offset; + u32 name = shdr->sh_name; + + if (strcmp(name_table + name, ".pru_irq_map")) + continue; + + /* make sure we have the entire irq map */ + if (offset + size > fw->size || offset + size < size) { + dev_err(dev, ".pru_irq_map section truncated\n"); + return ERR_PTR(-EINVAL); + } + + /* make sure irq map has at least the header */ + if (sizeof(struct pru_irq_rsc) > size) { + dev_err(dev, "header-less .pru_irq_map section\n"); + return ERR_PTR(-EINVAL); + } + + return shdr; + } + + dev_dbg(dev, "no .pru_irq_map section found for this fw\n"); + + return NULL; +} + /* * Use a custom parse_fw callback function for dealing with PRU firmware * specific sections. + * + * The firmware blob can contain optional ELF sections: .resource_table section + * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping + * description, which needs to be setup before powering on the PRU core. To + * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the + * firmware linker) and therefore is not loaded to PRU memory. */ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) { + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + const u8 *elf_data = fw->data; + const void *shdr; + u8 class = fw_elf_get_class(fw); + u64 sh_offset; int ret; /* load optional rsc table */ @@ -288,6 +455,19 @@ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) else if (ret) return ret; + /* find .pru_interrupt_map section, not having it is not an error */ + shdr = pru_rproc_find_interrupt_map(dev, fw); + if (IS_ERR(shdr)) + return PTR_ERR(shdr); + + if (!shdr) + return 0; + + /* preserve pointer to PRU interrupt map together with it size */ + sh_offset = elf_shdr_get_sh_offset(class, shdr); + pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset); + pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr); + return 0; } diff --git a/drivers/remoteproc/pru_rproc.h b/drivers/remoteproc/pru_rproc.h new file mode 100644 index 000000000000..8ee9c3171610 --- /dev/null +++ b/drivers/remoteproc/pru_rproc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * PRUSS Remote Processor specific types + * + * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#ifndef _PRU_RPROC_H_ +#define _PRU_RPROC_H_ + +/** + * struct pruss_int_map - PRU system events _to_ channel and host mapping + * @event: number of the system event + * @chnl: channel number assigned to a given @event + * @host: host number assigned to a given @chnl + * + * PRU system events are mapped to channels, and these channels are mapped + * to host interrupts. Events can be mapped to channels in a one-to-one or + * many-to-one ratio (multiple events per channel), and channels can be + * mapped to host interrupts in a one-to-one or many-to-one ratio (multiple + * channels per interrupt). + */ +struct pruss_int_map { + u8 event; + u8 chnl; + u8 host; +}; + +/** + * struct pru_irq_rsc - PRU firmware section header for IRQ data + * @type: resource type + * @num_evts: number of described events + * @pru_intc_map: PRU interrupt routing description + * + * The PRU firmware blob can contain optional .pru_irq_map ELF section, which + * provides the PRUSS interrupt mapping description. The pru_irq_rsc struct + * describes resource entry format. + */ +struct pru_irq_rsc { + u8 type; + u8 num_evts; + struct pruss_int_map pru_intc_map[]; +} __packed; + +#endif /* _PRU_RPROC_H_ */ From patchwork Fri Dec 4 20:18:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11952265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D8D3C4167B for ; Fri, 4 Dec 2020 20:20:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 266DF22B40 for ; Fri, 4 Dec 2020 20:20:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 266DF22B40 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3RT3+6epmGUlxT7c/f3yWbFbD11hyF/EsRrrREeU0kA=; b=hsYR9EQvkaVh4gnPC7oHGpPuq 3/QSFwDnGZVNB+O0GyZd+x6U8E49bUN2DMEZat7Z7AFR/pgC+tkfOeWJZnwLuH2aJQfLctYBImPFD hJdXWNc+azNi/acB8a6u1zE6UqtXO8imvsiw0ilij6bd1GPVCOCtvq9ulrAKLT7Du7tjHUgPdGWlb rJqZZPsbUWWJzzSQCY0ZDGa9alBUd8nNCFHwTukz9fPhNptd6JtDuY+FLu7hUwCce5sEgvIcjs/y8 bZ096aixcA3Md+gE9mcdMS9Who5hoX6TL4V1caWhJVbwpfIG5U1XBvFTX128GdmW61rZb6a1ZjWq4 goHvzYUXQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1klHXK-000174-2Z; Fri, 04 Dec 2020 20:18:38 +0000 Received: from mail-lf1-x143.google.com ([2a00:1450:4864:20::143]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1klHX5-00013f-0r for linux-arm-kernel@lists.infradead.org; Fri, 04 Dec 2020 20:18:26 +0000 Received: by mail-lf1-x143.google.com with SMTP id d20so9350767lfe.11 for ; Fri, 04 Dec 2020 12:18:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xt8QuWXk/g6askbWi99LuVBrM97JNGcNTAl0D+UbaYI=; b=rKfCVJUwnd66MPqnMbOC508RPjgxrmg4EUxCnqngmcl/AnBfBf5eQFoQlK1so9JKc3 ousXxG8hArnns/n+jOrvMbNouOh/wK51EZqkJjpLiGJUdyacqJ3dbC7zXXPj8WafTdrl 4U+Mzf19EfB5F7I2R2q9L3UTRd3SQUcC43jb2+PEi610jqTycoHdOmDxfAxLi5Jj9KDe SU2DX81y4K5/5wg077xEMWvlwnMZzt5hyJlVZjJAyRz8KeqxnNiCgOPlr73Lg1sWjPHB JYUoyqa3t7hn7tN5+vuN8jHsnOPLukfl5mmVAa2b7982jUP334Hr81u44KGuX1+EIjdw itsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xt8QuWXk/g6askbWi99LuVBrM97JNGcNTAl0D+UbaYI=; b=tSXSG57arN0byjDONwAolpZDmTKtBjjm1jtuBJJd7xy8qm3OKEk+Js4R0hJP5YG3uY dzCXYd5sf/siePQjY4vZee7rRbf1RSy8rpoIs0jGH7g+ZN6jQXgKZW3U/eToPrmsHhgj T4L/G1MbORCEqE4kD8+qu4o4qs4/4MLlKr/6RlBgSUh/SsU6N0vn1BteTs37EvVEgKej sp8vMdROkwZ+7maSzO56zdPDWux6nPi4AvdU8/hmXdWuSNDs1GmmvJRoohdDUGFKJW/+ 3vBDrALFKMMLR5QQOhZVe6iWxwq1BPDEKJUvym+OEZhzTnzHTfUcKzJovEBz1YxmIXTl 2H7w== X-Gm-Message-State: AOAM531wGX8X4ojJ8hlA1nLz6KyxWRTE6XLzGpKAAbVc0V4pdA5YsXye d4tt57FdGemea1wh3Ph9l+gAww== X-Google-Smtp-Source: ABdhPJz7ITP46bNgVVcIhlX2UDpR0V2gXIhU5e4UTfVXSAbV6WJqncAsO/D+QNg9QBaFS3xUyVl5Tw== X-Received: by 2002:a19:6144:: with SMTP id m4mr3959929lfk.546.1607113101740; Fri, 04 Dec 2020 12:18:21 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id w21sm2036918lff.280.2020.12.04.12.18.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2020 12:18:21 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Subject: [PATCH v3 4/6] remoteproc: pru: Add pru-specific debugfs support Date: Fri, 4 Dec 2020 21:18:05 +0100 Message-Id: <20201204201807.14716-5-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> References: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_151823_220456_B7517DAA X-CRM114-Status: GOOD ( 23.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, praneeth@ti.com, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suman Anna The remoteproc core creates certain standard debugfs entries, that does not give a whole lot of useful information for the PRUs. The PRU remoteproc driver is enhanced to add additional debugfs entries for PRU. These will be auto-cleaned up when the parent rproc debug directory is removed. The enhanced debugfs support adds two new entries: 'regs' and 'single_step'. The 'regs' dumps out the useful CTRL sub-module registers as well as each of the 32 GPREGs and CT_REGs registers. The GPREGs and CT_REGs though are printed only when the PRU is halted and accessible as per the IP design. The 'single_step' utilizes the single-step execution of the PRU cores. Writing a non-zero value performs a single step, and a zero value restores the PRU to execute in the same mode as the mode before the first single step. (note: if the PRU is halted because of a halt instruction, then no change occurs). Logic for setting the PC and jumping over a halt instruction shall be added in the future. Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v2->v3: Address Mathieu comments: - Remove extra line before DEFINE_SHOW_ATTRIBUTE(). - Add Reviewed-by: tag. --- drivers/remoteproc/pru_rproc.c | 136 +++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 4ef59d15d888..b22c4903299e 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -25,6 +26,13 @@ /* PRU_ICSS_PRU_CTRL registers */ #define PRU_CTRL_CTRL 0x0000 #define PRU_CTRL_STS 0x0004 +#define PRU_CTRL_WAKEUP_EN 0x0008 +#define PRU_CTRL_CYCLE 0x000C +#define PRU_CTRL_STALL 0x0010 +#define PRU_CTRL_CTBIR0 0x0020 +#define PRU_CTRL_CTBIR1 0x0024 +#define PRU_CTRL_CTPPR0 0x0028 +#define PRU_CTRL_CTPPR1 0x002C /* CTRL register bit-fields */ #define CTRL_CTRL_SOFT_RST_N BIT(0) @@ -34,6 +42,10 @@ #define CTRL_CTRL_SINGLE_STEP BIT(8) #define CTRL_CTRL_RUNSTATE BIT(15) +/* PRU_ICSS_PRU_DEBUG registers */ +#define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) +#define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) + /* PRU Core IRAM address masks */ #define PRU_IRAM_ADDR_MASK 0x3ffff #define PRU0_IRAM_ADDR_MASK 0x34000 @@ -73,6 +85,8 @@ enum pru_iomem { * @mapped_irq: virtual interrupt numbers of created fw specific mapping * @pru_interrupt_map: pointer to interrupt mapping description (firmware) * @pru_interrupt_map_sz: pru_interrupt_map size + * @dbg_single_step: debug state variable to set PRU into single step mode + * @dbg_continuous: debug state variable to restore PRU execution mode * @evt_count: number of mapped events */ struct pru_rproc { @@ -85,6 +99,8 @@ struct pru_rproc { unsigned int *mapped_irq; struct pru_irq_rsc *pru_interrupt_map; size_t pru_interrupt_map_sz; + u32 dbg_single_step; + u32 dbg_continuous; u8 evt_count; }; @@ -99,6 +115,124 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg) +{ + return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg); +} + +static int regs_show(struct seq_file *s, void *data) +{ + struct rproc *rproc = s->private; + struct pru_rproc *pru = rproc->priv; + int i, nregs = 32; + u32 pru_sts; + int pru_is_running; + + seq_puts(s, "============== Control Registers ==============\n"); + seq_printf(s, "CTRL := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTRL)); + pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS); + seq_printf(s, "STS (PC) := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2); + seq_printf(s, "WAKEUP_EN := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN)); + seq_printf(s, "CYCLE := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CYCLE)); + seq_printf(s, "STALL := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_STALL)); + seq_printf(s, "CTBIR0 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTBIR0)); + seq_printf(s, "CTBIR1 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTBIR1)); + seq_printf(s, "CTPPR0 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTPPR0)); + seq_printf(s, "CTPPR1 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTPPR1)); + + seq_puts(s, "=============== Debug Registers ===============\n"); + pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) & + CTRL_CTRL_RUNSTATE; + if (pru_is_running) { + seq_puts(s, "PRU is executing, cannot print/access debug registers.\n"); + return 0; + } + + for (i = 0; i < nregs; i++) { + seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n", + i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)), + i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i))); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(regs); + +/* + * Control PRU single-step mode + * + * This is a debug helper function used for controlling the single-step + * mode of the PRU. The PRU Debug registers are not accessible when the + * PRU is in RUNNING state. + * + * Writing a non-zero value sets the PRU into single-step mode irrespective + * of its previous state. The PRU mode is saved only on the first set into + * a single-step mode. Writing a zero value will restore the PRU into its + * original mode. + */ +static int pru_rproc_debug_ss_set(void *data, u64 val) +{ + struct rproc *rproc = data; + struct pru_rproc *pru = rproc->priv; + u32 reg_val; + + val = val ? 1 : 0; + if (!val && !pru->dbg_single_step) + return 0; + + reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL); + + if (val && !pru->dbg_single_step) + pru->dbg_continuous = reg_val; + + if (val) + reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN; + else + reg_val = pru->dbg_continuous; + + pru->dbg_single_step = val; + pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val); + + return 0; +} + +static int pru_rproc_debug_ss_get(void *data, u64 *val) +{ + struct rproc *rproc = data; + struct pru_rproc *pru = rproc->priv; + + *val = pru->dbg_single_step; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get, + pru_rproc_debug_ss_set, "%llu\n"); + +/* + * Create PRU-specific debugfs entries + * + * The entries are created only if the parent remoteproc debugfs directory + * exists, and will be cleaned up by the remoteproc core. + */ +static void pru_rproc_create_debug_entries(struct rproc *rproc) +{ + if (!rproc->dbg_dir) + return; + + debugfs_create_file("regs", 0400, rproc->dbg_dir, + rproc, ®s_fops); + debugfs_create_file("single_step", 0600, rproc->dbg_dir, + rproc, &pru_rproc_debug_ss_fops); +} + static void pru_dispose_irq_mapping(struct pru_rproc *pru) { while (pru->evt_count--) { @@ -571,6 +705,8 @@ static int pru_rproc_probe(struct platform_device *pdev) return ret; } + pru_rproc_create_debug_entries(rproc); + dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); return 0; From patchwork Fri Dec 4 20:18:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11952269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B886AC19437 for ; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w21sm2036918lff.280.2020.12.04.12.18.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2020 12:18:23 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Subject: [PATCH v3 5/6] remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCs Date: Fri, 4 Dec 2020 21:18:06 +0100 Message-Id: <20201204201807.14716-6-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> References: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_151825_436614_66F81E3B X-CRM114-Status: GOOD ( 31.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, praneeth@ti.com, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suman Anna The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. Enhance the existing PRU remoteproc driver to support these new PRU, RTU and Tx PRU cores by using specific compatibles. The initial names for the firmware images for each PRU core are retrieved from DT nodes, and can be adjusted through sysfs if required. The PRU remoteproc driver has to be specifically modified to use a custom memcpy function within its ELF loader implementation for these new cores in order to overcome a limitation with copying data into each of the core's IRAM memories. These memory ports support only 4-byte writes, and any sub-word order byte writes clear out the remaining bytes other than the bytes being written within the containing word. The default ARM64 memcpy also cannot be used as it throws an exception when the preferred 8-byte copy operation is attempted. This choice is made by using a state flag that is set only on K3 SoCs. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v2->v3: Address Mathieu comments: - Change type of some local variable in pru_rproc_memcpy from 'int *' to 'u32 *'. At the occasion use size_t for 'size' inside mentioned function. - Add Reviewed-by: tag. v1->v2: - Update documentation of pru_rproc_memcpy() according to Suman comments. - Update documentation of is_k3 flag. --- drivers/remoteproc/pru_rproc.c | 140 ++++++++++++++++++++++++++++++--- 1 file changed, 131 insertions(+), 9 deletions(-) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index b22c4903299e..f76423792acb 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -46,10 +46,14 @@ #define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) #define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) -/* PRU Core IRAM address masks */ +/* PRU/RTU/Tx_PRU Core IRAM address masks */ #define PRU_IRAM_ADDR_MASK 0x3ffff #define PRU0_IRAM_ADDR_MASK 0x34000 #define PRU1_IRAM_ADDR_MASK 0x38000 +#define RTU0_IRAM_ADDR_MASK 0x4000 +#define RTU1_IRAM_ADDR_MASK 0x6000 +#define TX_PRU0_IRAM_ADDR_MASK 0xa000 +#define TX_PRU1_IRAM_ADDR_MASK 0xc000 /* PRU device addresses for various type of PRU RAMs */ #define PRU_IRAM_DA 0 /* Instruction RAM */ @@ -74,12 +78,38 @@ enum pru_iomem { PRU_IOMEM_MAX, }; +/** + * enum pru_type - PRU core type identifier + * + * @PRU_TYPE_PRU: Programmable Real-time Unit + * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit + * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit + * @PRU_TYPE_MAX: just keep this one at the end + */ +enum pru_type { + PRU_TYPE_PRU = 0, + PRU_TYPE_RTU, + PRU_TYPE_TX_PRU, + PRU_TYPE_MAX, +}; + +/** + * struct pru_private_data - device data for a PRU core + * @type: type of the PRU core (PRU, RTU, Tx_PRU) + * @is_k3: flag used to identify the need for special load handling + */ +struct pru_private_data { + enum pru_type type; + unsigned int is_k3 : 1; +}; + /** * struct pru_rproc - PRU remoteproc structure * @id: id of the PRU core within the PRUSS * @dev: PRU core device pointer * @pruss: back-reference to parent PRUSS structure * @rproc: remoteproc pointer for this PRU core + * @data: PRU core specific data * @mem_regions: data for each of the PRU memory regions * @fw_name: name of firmware image used during loading * @mapped_irq: virtual interrupt numbers of created fw specific mapping @@ -94,6 +124,7 @@ struct pru_rproc { struct device *dev; struct pruss *pruss; struct rproc *rproc; + const struct pru_private_data *data; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; const char *fw_name; unsigned int *mapped_irq; @@ -318,11 +349,12 @@ static int pru_rproc_start(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; u32 val; int ret; - dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", - pru->id, (rproc->bootaddr >> 2)); + dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n", + names[pru->data->type], pru->id, (rproc->bootaddr >> 2)); ret = pru_handle_intrmap(rproc); /* @@ -344,9 +376,10 @@ static int pru_rproc_stop(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; u32 val; - dev_dbg(dev, "stopping PRU%d\n", pru->id); + dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id); val = pru_control_read_reg(pru, PRU_CTRL_CTRL); val &= ~CTRL_CTRL_EN; @@ -458,9 +491,52 @@ static struct rproc_ops pru_rproc_ops = { .da_to_va = pru_rproc_da_to_va, }; +/* + * Custom memory copy implementation for ICSSG PRU/RTU/Tx_PRU Cores + * + * The ICSSG PRU/RTU/Tx_PRU cores have a memory copying issue with IRAM + * memories, that is not seen on previous generation SoCs. The data is reflected + * properly in the IRAM memories only for integer (4-byte) copies. Any unaligned + * copies result in all the other pre-existing bytes zeroed out within that + * 4-byte boundary, thereby resulting in wrong text/code in the IRAMs. Also, the + * IRAM memory port interface does not allow any 8-byte copies (as commonly used + * by ARM64 memcpy implementation) and throws an exception. The DRAM memory + * ports do not show this behavior. + */ +static int pru_rproc_memcpy(void *dest, const void *src, size_t count) +{ + const u32 *s = src; + u32 *d = dest; + size_t size = count / 4; + u32 *tmp_src = NULL; + + /* + * TODO: relax limitation of 4-byte aligned dest addresses and copy + * sizes + */ + if ((long)dest % 4 || count % 4) + return -EINVAL; + + /* src offsets in ELF firmware image can be non-aligned */ + if ((long)src % 4) { + tmp_src = kmemdup(src, count, GFP_KERNEL); + if (!tmp_src) + return -ENOMEM; + s = tmp_src; + } + + while (size--) + *d++ = *s++; + + kfree(tmp_src); + + return 0; +} + static int pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) { + struct pru_rproc *pru = rproc->priv; struct device *dev = &rproc->dev; struct elf32_hdr *ehdr; struct elf32_phdr *phdr; @@ -508,7 +584,17 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) break; } - memcpy(ptr, elf_data + phdr->p_offset, filesz); + if (pru->data->is_k3 && is_iram) { + ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset, + filesz); + if (ret) { + dev_err(dev, "PRU memory copy failed for da 0x%x memsz 0x%x\n", + da, memsz); + break; + } + } else { + memcpy(ptr, elf_data + phdr->p_offset, filesz); + } /* skip the memzero logic performed by remoteproc ELF loader */ } @@ -614,9 +700,17 @@ static int pru_rproc_set_id(struct pru_rproc *pru) int ret = 0; switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { + case TX_PRU0_IRAM_ADDR_MASK: + fallthrough; + case RTU0_IRAM_ADDR_MASK: + fallthrough; case PRU0_IRAM_ADDR_MASK: pru->id = 0; break; + case TX_PRU1_IRAM_ADDR_MASK: + fallthrough; + case RTU1_IRAM_ADDR_MASK: + fallthrough; case PRU1_IRAM_ADDR_MASK: pru->id = 1; break; @@ -637,8 +731,13 @@ static int pru_rproc_probe(struct platform_device *pdev) struct rproc *rproc = NULL; struct resource *res; int i, ret; + const struct pru_private_data *data; const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; + data = of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + ret = of_property_read_string(np, "firmware-name", &fw_name); if (ret) { dev_err(dev, "unable to retrieve firmware-name %d\n", ret); @@ -671,6 +770,7 @@ static int pru_rproc_probe(struct platform_device *pdev) pru = rproc->priv; pru->dev = dev; + pru->data = data; pru->pruss = platform_get_drvdata(ppdev); pru->rproc = rproc; pru->fw_name = fw_name; @@ -722,11 +822,33 @@ static int pru_rproc_remove(struct platform_device *pdev) return 0; } +static const struct pru_private_data pru_data = { + .type = PRU_TYPE_PRU, +}; + +static const struct pru_private_data k3_pru_data = { + .type = PRU_TYPE_PRU, + .is_k3 = 1, +}; + +static const struct pru_private_data k3_rtu_data = { + .type = PRU_TYPE_RTU, + .is_k3 = 1, +}; + +static const struct pru_private_data k3_tx_pru_data = { + .type = PRU_TYPE_TX_PRU, + .is_k3 = 1, +}; + static const struct of_device_id pru_rproc_match[] = { - { .compatible = "ti,am3356-pru", }, - { .compatible = "ti,am4376-pru", }, - { .compatible = "ti,am5728-pru", }, - { .compatible = "ti,k2g-pru", }, + { .compatible = "ti,am3356-pru", .data = &pru_data }, + { .compatible = "ti,am4376-pru", .data = &pru_data }, + { .compatible = "ti,am5728-pru", .data = &pru_data }, + { .compatible = "ti,k2g-pru", .data = &pru_data }, + { .compatible = "ti,am654-pru", .data = &k3_pru_data }, + { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, + { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, {}, }; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w21sm2036918lff.280.2020.12.04.12.18.23 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2020 12:18:24 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Subject: [PATCH v3 6/6] remoteproc: pru: Add support for various PRU cores on K3 J721E SoCs Date: Fri, 4 Dec 2020 21:18:07 +0100 Message-Id: <20201204201807.14716-7-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> References: <20201204201807.14716-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_151826_142498_FEFD5BD1 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, praneeth@ti.com, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, rogerq@ti.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suman Anna The K3 J721E family of SoCs have a revised version of the AM65x ICSSG IP and contains two instances of this newer ICSSG IP. Each ICSSG processor subsystem contains 2 primary PRU cores, 2 auxiliary PRU cores called RTUs, and 2 new auxiliary cores called Transmit PRUs (Tx_PRUs). Enhance the existing PRU remoteproc driver to support these new PRU and RTU cores by using specific compatibles. The cores have the same memory copying limitations as on AM65x, so reuses the custom memcpy function within the driver's ELF loader implementation. The initial names for the firmware images for each PRU core are retrieved from DT nodes, and can be adjusted through sysfs if required. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v2->v3: - Add Reviewed-by: tag --- drivers/remoteproc/pru_rproc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index f76423792acb..e32123c099de 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -849,6 +849,9 @@ static const struct of_device_id pru_rproc_match[] = { { .compatible = "ti,am654-pru", .data = &k3_pru_data }, { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, + { .compatible = "ti,j721e-pru", .data = &k3_pru_data }, + { .compatible = "ti,j721e-rtu", .data = &k3_rtu_data }, + { .compatible = "ti,j721e-tx-pru", .data = &k3_tx_pru_data }, {}, }; MODULE_DEVICE_TABLE(of, pru_rproc_match);