From patchwork Sat Dec 5 01:08:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7549EC433FE for ; Sat, 5 Dec 2020 01:09:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2A62322D6F for ; Sat, 5 Dec 2020 01:09:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2A62322D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61EAE6E22C; Sat, 5 Dec 2020 01:09:02 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 903746E222 for ; Sat, 5 Dec 2020 01:09:00 +0000 (UTC) IronPort-SDR: qR7/5T9F6b+8lqN7MYu+e01+Ysz/UrCAI6cC8qFzs2pJSH7ROJBWXYkKJDqmfKngina1wLzTfi BZe7uKMfDlTw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173570978" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570978" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:54 -0800 IronPort-SDR: VWl4n392I8ABICkgSWnd6mtFqsHEtwONNqDTkY4nzh4HbgIMPcSyrZFc7ApxmXAYXzHqUcx0zo B3fJVwAGQddw== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062849" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:54 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:23 -0800 Message-Id: <20201205010844.361880-2-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/22] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Fix TGL REVID macros to fetch correct display/gt stepping based on SOC rev id from INTEL_REVID() macro. Previously, we were just returning the first element of the revid array instead of using the correct index based on SOC rev id. Fixes: ("drm/i915/tgl: Fix stepping WA matching") Cc: José Roberto de Souza Cc: Matt Roper Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_drv.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fc1090c6889c..2e2149c9a2f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1580,9 +1580,9 @@ static inline const struct i915_rev_steppings * tgl_revids_get(struct drm_i915_private *dev_priv) { if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) - return tgl_uy_revids; + return &tgl_uy_revids[INTEL_REVID(dev_priv)]; else - return tgl_revids; + return &tgl_revids[INTEL_REVID(dev_priv)]; } #define IS_TGL_DISP_REVID(p, since, until) \ @@ -1592,14 +1592,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv) #define IS_TGL_UY_GT_REVID(p, since, until) \ ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ - tgl_uy_revids->gt_stepping >= (since) && \ - tgl_uy_revids->gt_stepping <= (until)) + tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \ + tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until)) #define IS_TGL_GT_REVID(p, since, until) \ (IS_TIGERLAKE(p) && \ !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ - tgl_revids->gt_stepping >= (since) && \ - tgl_revids->gt_stepping <= (until)) + tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \ + tgl_revids[INTEL_REVID(p)].gt_stepping <= (until)) #define RKL_REVID_A0 0x0 #define RKL_REVID_B0 0x1 From patchwork Sat Dec 5 01:08:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0477EC4361A for ; Sat, 5 Dec 2020 01:09:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF6B222D6F for ; Sat, 5 Dec 2020 01:09:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF6B222D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A40406E22F; Sat, 5 Dec 2020 01:09:01 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C2886E220 for ; Sat, 5 Dec 2020 01:09:00 +0000 (UTC) IronPort-SDR: scrFz5J4sYE/lkRiIfAsIRKoiB1KGlYqqETuqDrmXyNkLCUh7gbmGsc+Mre6Abj4GghIAlx1aZ 3zEW+pDi6vCg== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173570981" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570981" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:55 -0800 IronPort-SDR: yeVafwRhSjvAFXKJAQjfoBk3u+OAqDkoqMU2O5ea61AHMYoaaiUyeRoojRwWdDTLzOpIR5/l+W gL/NpdizsELQ== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062857" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:55 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:24 -0800 Message-Id: <20201205010844.361880-3-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/22] drm/i915/tgl: Add bound checks and simplify TGL REVID macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add bound checks for TGL REV ID array. Since, there might be a possibility of using older kernels on latest platform revisions, resulting in out of bounds access for rev ID array. In this scenario, use the latest rev ID available and apply those WAs. Also, simplify GT macros for TGL rev ID to reuse tgl_revids_get(). Cc: José Roberto de Souza Cc: Matt Roper Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/i915_drv.h | 34 +++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2e2149c9a2f4..37c2df19ce52 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1573,16 +1573,30 @@ enum { TGL_REVID_D0, }; -extern const struct i915_rev_steppings tgl_uy_revids[]; -extern const struct i915_rev_steppings tgl_revids[]; +#define TGL_UY_REVIDS_SIZE 4 +#define TGL_REVIDS_SIZE 2 + +extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE]; +extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE]; static inline const struct i915_rev_steppings * tgl_revids_get(struct drm_i915_private *dev_priv) { - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) - return &tgl_uy_revids[INTEL_REVID(dev_priv)]; - else - return &tgl_revids[INTEL_REVID(dev_priv)]; + u8 revid = INTEL_REVID(dev_priv); + u8 size; + const struct i915_rev_steppings *tgl_revid_tbl; + + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { + tgl_revid_tbl = tgl_uy_revids; + size = ARRAY_SIZE(tgl_uy_revids); + } else { + tgl_revid_tbl = tgl_revids; + size = ARRAY_SIZE(tgl_revids); + } + + revid = min_t(u8, revid, size - 1); + + return &tgl_revid_tbl[revid]; } #define IS_TGL_DISP_REVID(p, since, until) \ @@ -1592,14 +1606,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv) #define IS_TGL_UY_GT_REVID(p, since, until) \ ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ - tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \ - tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until)) + tgl_revids_get(p)->gt_stepping >= (since) && \ + tgl_revids_get(p)->gt_stepping <= (until)) #define IS_TGL_GT_REVID(p, since, until) \ (IS_TIGERLAKE(p) && \ !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ - tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \ - tgl_revids[INTEL_REVID(p)].gt_stepping <= (until)) + tgl_revids_get(p)->gt_stepping >= (since) && \ + tgl_revids_get(p)->gt_stepping <= (until)) #define RKL_REVID_A0 0x0 #define RKL_REVID_B0 0x1 From patchwork Sat Dec 5 01:08:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09073C4361A for ; Sat, 5 Dec 2020 01:09:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A206322D6F for ; Sat, 5 Dec 2020 01:09:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A206322D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 756076E221; Sat, 5 Dec 2020 01:09:00 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 680806E221 for ; Sat, 5 Dec 2020 01:08:59 +0000 (UTC) IronPort-SDR: +vJ7yp1O7dR/qOBCWNpF2+n4qARiLOMGyQd2/9hjweSPba7h1FQnWjHpM00Uw09zWGnK2r6Pt7 ulm3bmaHV7Zg== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173570985" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570985" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:57 -0800 IronPort-SDR: 52uU8/JPR9Iqq2ErVN5VXc4KHOQgNZtW9D/6hRiXBMVTc7q+zeVtXDNmpjg9suhrpkatfAzBUE CmjV9ahCSU6A== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062862" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:56 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:25 -0800 Message-Id: <20201205010844.361880-4-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama - Add the initial platform information for Alderlake-S. - Specify ppgtt_size value - Add dma_mask_size - Add ADLS REVIDs - HW tracking(Selective Update Tracking Enable) has been removed from ADLS. Disable PSR2 till we enable software/ manual tracking. v2: - Add support for different ADLS SOC steppings to select correct GT/DISP stepping based on Bspec 53655 based on feedback from Matt Roper.(aswarup) v3: - Make display/gt steppings info generic for reuse with TGL and ADLS. - Modify the macros to reuse tgl_revids_get() - Add HTI support to adls device info.(mdroper) Bspec: 53597 Bspec: 53648 Bspec: 53655 Bspec: 48028 Bspec: 53650 BSpec: 50422 Cc: José Roberto de Souza Cc: Matt Roper Cc: Lucas De Marchi Cc: Anusha Srivatsa Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Signed-off-by: Caz Yokoyama Signed-off-by: Aditya Swarup --- .../drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 +++++++----- drivers/gpu/drm/i915/i915_drv.h | 45 ++++++++++++++----- drivers/gpu/drm/i915/i915_pci.c | 13 ++++++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- include/drm/i915_pciids.h | 13 ++++++ 10 files changed, 86 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index fe2d90bba536..06c036e2092c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) int config, i; if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0)) /* Wa_1409767108:tgl,dg1 */ table = wa_1409767108_buddy_page_masks; else diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d9a395c486d3..1771f5000a45 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (dev_priv->psr.psr2_sel_fetch_enabled) { /* WA 1408330847 */ - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) || IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) /* WA 1408330847 */ if (dev_priv->psr.psr2_sel_fetch_enabled && - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || + (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) || IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index b7e208816074..e19d4f873b94 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -3032,7 +3032,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, { /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 7c6b21ced56f..3db57b577a79 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -71,16 +71,24 @@ const struct i915_rev_steppings kbl_revids[] = { }; const struct i915_rev_steppings tgl_uy_revids[] = { - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 }, - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 }, - [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 }, - [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 }, + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 }, + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 }, + [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 }, + [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 }, }; /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ const struct i915_rev_steppings tgl_revids[] = { - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 }, - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 }, + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 }, + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 }, +}; + +const struct i915_rev_steppings adls_revids[] = { + [ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 }, + [ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 }, + [ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 }, + [ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 }, + [ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 }, }; static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) @@ -1250,13 +1258,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) + if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS); /* Wa_1607087056:tgl also know as BUG:1409180338 */ - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) + if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); @@ -1734,7 +1742,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) struct drm_i915_private *i915 = engine->i915; if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || - IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { + IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) { /* * Wa_1607138336:tgl[a0],dg1[a0] * Wa_1607063988:tgl[a0],dg1[a0] @@ -1744,7 +1752,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); } - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { + if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) { /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c2df19ce52..91bd262dd871 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) #define IS_BDW_ULT(dev_priv) \ @@ -1566,37 +1567,43 @@ extern const struct i915_rev_steppings kbl_revids[]; (IS_JSL_EHL(p) && IS_REVID(p, since, until)) enum { - TGL_REVID_A0, - TGL_REVID_B0, - TGL_REVID_B1, - TGL_REVID_C0, - TGL_REVID_D0, + REVID_A0, + REVID_A2, + REVID_B0, + REVID_B1, + REVID_C0, + REVID_D0, }; #define TGL_UY_REVIDS_SIZE 4 #define TGL_REVIDS_SIZE 2 +#define ADLS_REVIDS_SIZE 13 extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE]; extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE]; +extern const struct i915_rev_steppings adls_revids[ADLS_REVIDS_SIZE]; static inline const struct i915_rev_steppings * tgl_revids_get(struct drm_i915_private *dev_priv) { u8 revid = INTEL_REVID(dev_priv); u8 size; - const struct i915_rev_steppings *tgl_revid_tbl; + const struct i915_rev_steppings *revid_tbl; - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { - tgl_revid_tbl = tgl_uy_revids; + if (IS_ALDERLAKE_S(dev_priv)) { + revid_tbl = adls_revids; + size = ARRAY_SIZE(adls_revids); + } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { + revid_tbl = tgl_uy_revids; size = ARRAY_SIZE(tgl_uy_revids); } else { - tgl_revid_tbl = tgl_revids; + revid_tbl = tgl_revids; size = ARRAY_SIZE(tgl_revids); } revid = min_t(u8, revid, size - 1); - return &tgl_revid_tbl[revid]; + return &revid_tbl[revid]; } #define IS_TGL_DISP_REVID(p, since, until) \ @@ -1628,6 +1635,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv) #define IS_DG1_REVID(p, since, until) \ (IS_DG1(p) && IS_REVID(p, since, until)) +#define ADLS_REVID_A0 0x0 +#define ADLS_REVID_A2 0x1 +#define ADLS_REVID_B0 0x4 +#define ADLS_REVID_G0 0x8 +#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/ + +extern const struct i915_rev_steppings adls_revids[]; + +#define IS_ADLS_DISP_REVID(p, since, until) \ + (IS_ALDERLAKE_S(p) && \ + tgl_revids_get(p)->disp_stepping >= (since) && \ + tgl_revids_get(p)->disp_stepping <= (until)) + +#define IS_ADLS_GT_REVID(p, since, until) \ + (IS_ALDERLAKE_S(p) && \ + tgl_revids_get(p)->gt_stepping >= (since) && \ + tgl_revids_get(p)->gt_stepping <= (until)) + #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 11fe790b1969..26e4bf8bb4ef 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info __maybe_unused = { .ppgtt_size = 47, }; +static const struct intel_device_info adl_s_info = { + GEN12_FEATURES, + PLATFORM(INTEL_ALDERLAKE_S), + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), + .require_force_probe = 1, + .display.has_hti = 1, + .display.has_psr_hw_tracking = 0, + .platform_engine_mask = + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), + .dma_mask_size = 46, +}; + #undef GEN #undef PLATFORM @@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_JSL_IDS(&jsl_info), INTEL_TGL_12_IDS(&tgl_info), INTEL_RKL_IDS(&rkl_info), + INTEL_ADLS_IDS(&adl_s_info), {0, 0, 0} }; MODULE_DEVICE_TABLE(pci, pciidlist); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ef767f04c37c..ce8c69c17b8e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -66,6 +66,7 @@ static const char * const platform_names[] = { PLATFORM_NAME(TIGERLAKE), PLATFORM_NAME(ROCKETLAKE), PLATFORM_NAME(DG1), + PLATFORM_NAME(ALDERLAKE_S), }; #undef PLATFORM_NAME diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index d92fa041c700..360f3f1835f5 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -84,6 +84,7 @@ enum intel_platform { INTEL_TIGERLAKE, INTEL_ROCKETLAKE, INTEL_DG1, + INTEL_ALDERLAKE_S, INTEL_MAX_PLATFORMS }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bbc73df7f753..d92616581819 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); /* Wa_1409825376:tgl (pre-prod)*/ - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1)) + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1)) intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 931e46191047..ae53ff8462ae 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -634,4 +634,17 @@ INTEL_VGA_DEVICE(0x4907, info), \ INTEL_VGA_DEVICE(0x4908, info) +/* ADL-S */ +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info), \ + INTEL_VGA_DEVICE(0x4698, info), \ + INTEL_VGA_DEVICE(0x4699, info) + #endif /* _I915_PCIIDS_H */ From patchwork Sat Dec 5 01:08:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31557C4361A for ; Sat, 5 Dec 2020 01:09:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E37A822D6F for ; Sat, 5 Dec 2020 01:09:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E37A822D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A45016E223; Sat, 5 Dec 2020 01:09:00 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B07B6E220 for ; Sat, 5 Dec 2020 01:08:59 +0000 (UTC) IronPort-SDR: dE/W0immGprcUuNMMrotGoEqR2KRaZQ5jbOneFYGHkQj7U60y4B8XcW2GX6bp4gJHoazWuo4sx 2NP/Qw7OIy5A== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173570994" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570994" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:58 -0800 IronPort-SDR: GAKvfBOyRr2YvnwdNDmaz5Im1+jocKBV7vFfcgHKDRQVzzEJqv8UIagloXOBcEJHvJhrH002K6 AQRP6QcrRFIw== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062880" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:57 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:26 -0800 Message-Id: <20201205010844.361880-5-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/22] x86/gpu: add ADL_S stolen memory support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , x86@kernel.org, Lucas De Marchi , Ingo Molnar , Thomas Gleixner , Borislav Petkov Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama ADL_S re-uses the same stolen memory registers as TGL and ICL. This patch has a dependency on: ("drm/i915/adl_s: Add ADL-S platform info and PCI ids") Bspec: 52055 Bspec: 49589 Bspec: 49636 Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: x86@kernel.org Cc: Ingo Molnar , Cc: Thomas Gleixner , Cc: Borislav Petkov Signed-off-by: Caz Yokoyama Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index a4b5af03dcc1..6edd1e2ee8af 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_EHL_IDS(&gen11_early_ops), INTEL_TGL_12_IDS(&gen11_early_ops), INTEL_RKL_IDS(&gen11_early_ops), + INTEL_ADLS_IDS(&gen11_early_ops), }; struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); From patchwork Sat Dec 5 01:08:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B21BCC433FE for ; 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a="173570997" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570997" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:59 -0800 IronPort-SDR: 3WRUHHvltfEfYQsW4/AgZy6waWhGghAeHw6P9mMAdRb97swG2XHFA6gY4x9t/YFOtNNd6h56dM DGr8QFkrZgug== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062887" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:58 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:27 -0800 Message-Id: <20201205010844.361880-6-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/22] drm/i915/adl_s: Add PCH support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Add support for Alderpoint(ADP) PCH used with Alderlake-S. v2: - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup) Cc: Matt Roper Cc: Lucas De Marchi Cc: Caz Yokoyama Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Signed-off-by: Anusha Srivatsa Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/intel_pch.c | 8 +++++++- drivers/gpu/drm/i915/intel_pch.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index f31c0dabd0cc..2a6d70f247e8 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n"); drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv)); return PCH_JSP; + case INTEL_PCH_ADP_DEVICE_ID_TYPE: + drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n"); + drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv)); + return PCH_ADP; default: return PCH_NONE; } @@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + id = INTEL_PCH_ADP_DEVICE_ID_TYPE; + else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) id = INTEL_PCH_TGP_DEVICE_ID_TYPE; else if (IS_JSL_EHL(dev_priv)) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h index 06d2cd50af0b..7318377503b0 100644 --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h @@ -26,6 +26,7 @@ enum intel_pch { PCH_JSP, /* Jasper Lake PCH */ PCH_MCC, /* Mule Creek Canyon PCH */ PCH_TGP, /* Tiger Lake PCH */ + PCH_ADP, /* Alder Lake PCH */ /* Fake PCHs, functionality handled on the same PCI dev */ PCH_DG1 = 1024, @@ -53,12 +54,14 @@ enum intel_pch { #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880 +#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) From patchwork Sat Dec 5 01:08:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35B40C4167B for ; Sat, 5 Dec 2020 01:09:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F202022D6F for ; Sat, 5 Dec 2020 01:09:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F202022D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7A636E235; Sat, 5 Dec 2020 01:09:05 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE0116E220 for ; Sat, 5 Dec 2020 01:09:00 +0000 (UTC) IronPort-SDR: 3TKpOKclzGw0OypJS89hxnWdkJLBeE1hO6H3TnwDa4qXty/wHFdIZAKsIPV6u2OR92xkYGgIz4 f7j3I5LGtaGg== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173570998" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570998" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:00 -0800 IronPort-SDR: T4NEWikvYgdPVMMLktmRRo1KpO7CCNrviOL2ehSM44fdbht1GuUJIBmUlwemt6tEFszKxosDIX yp80S/WN0TeA== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062896" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:08:59 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:28 -0800 Message-Id: <20201205010844.361880-7-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/22] drm/i915/adl_s: Add Interrupt Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa ADLS follows ICP/TGP like interrupts. v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Signed-off-by: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_irq.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b245109f73e3..d1b4893d6c92 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -191,8 +191,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (HAS_PCH_DG1(dev_priv)) hpd->pch_hpd = hpd_sde_dg1; - else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || - HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) hpd->pch_hpd = hpd_icp; else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) hpd->pch_hpd = hpd_spt; From patchwork Sat Dec 5 01:08:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B67ADC4361B for ; Sat, 5 Dec 2020 01:09:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6B09322D6F for ; Sat, 5 Dec 2020 01:09:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6B09322D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FA506E237; Sat, 5 Dec 2020 01:09:04 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id A07056E222 for ; Sat, 5 Dec 2020 01:09:01 +0000 (UTC) IronPort-SDR: fS+21cKqvRGVvR9GwIM20KIZoGh/75nFLzDu7tcYj1y4PqreWxTwZ25FyzG6u3bBrJ7/t4nDR5 EeyH/Djz1XNg== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173570999" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173570999" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:01 -0800 IronPort-SDR: BqzIITS0wJ5Bl2obonsVJY9nhl8extNeBJPggufLpzV3J3E2hAtVgjHgg/O/lfgch5Mejisaps 2JiR6spMOKiw== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062904" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:00 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:29 -0800 Message-Id: <20201205010844.361880-8-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Alderlake-S has 5 combo phys, add reg definitions for combo phys and update the port to phy helper for ADL-S. v2: - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc() and return false for platforms RKL,DG1 and ADLS.(mdroper) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Signed-off-by: Anusha Srivatsa Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++---- drivers/gpu/drm/i915/i915_reg.h | 5 ++++- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9187a20a8aca..2d1c5bfe4032 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7397,6 +7397,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) return false; + else if (IS_ALDERLAKE_S(dev_priv)) + return phy <= PHY_E; else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return phy <= PHY_D; else if (IS_JSL_EHL(dev_priv)) @@ -7409,9 +7411,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) - return false; - else if (INTEL_GEN(dev_priv) >= 12) + if (IS_TIGERLAKE(dev_priv)) return phy >= PHY_D && phy <= PHY_I; else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv)) return phy >= PHY_C && phy <= PHY_F; @@ -7421,7 +7421,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { - if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) + if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) + return PHY_B + port - PORT_TC1; + else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) return PHY_C + port - PORT_TC1; else if (IS_JSL_EHL(i915) && port == PORT_D) return PHY_A; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cdc67f583a9c..60a0d4c35cae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _ICL_COMBOPHY_B 0x6C000 #define _EHL_COMBOPHY_C 0x160000 #define _RKL_COMBOPHY_D 0x161000 +#define _ADL_COMBOPHY_E 0x16B000 + #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ _ICL_COMBOPHY_B, \ _EHL_COMBOPHY_C, \ - _RKL_COMBOPHY_D) + _RKL_COMBOPHY_D, \ + _ADL_COMBOPHY_E) /* CNL/ICL Port CL_DW registers */ #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ From patchwork Sat Dec 5 01:08:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF001C4361A for ; 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a="173571002" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571002" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:02 -0800 IronPort-SDR: hSYU/hiAFktZ8IYUszhPhFzYxPjSj+qOjWzRmY4gkxnitUm8MFE3q/e0Kz3GxPDpc68Z6XkFQE c4jiOHqRH3gg== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062915" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:01 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:30 -0800 Message-Id: <20201205010844.361880-9-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add changes for configuring DPLL for ADL-S - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S - Extend CNL macro to choose DPLL_ENABLE for ADL-S. - Select CFGCR0 and CFGCR1 for ADL-S plls. On BSpec: 53720 PLL arrangement dig for adls: DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1) DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1) v2 (Lucas): add missing update_ref_clks Bspec: 50288 Bspec: 50289 Bspec: 49443 v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield for DPLL3_USED.(mdroper) Bspec: 53707 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 21 +++++++++- 2 files changed, 53 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index f6ad257a260e..529b1d569af2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + dpll_mask = + BIT(DPLL_ID_DG1_DPLL3) | + BIT(DPLL_ID_DG1_DPLL2) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else if (IS_DG1(dev_priv)) { if (port == PORT_D || port == PORT_E) { dpll_mask = BIT(DPLL_ID_DG1_DPLL2) | @@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!(val & PLL_ENABLE)) goto out; - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id)); + } else if (IS_DG1(dev_priv)) { hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); } else if (IS_ROCKETLAKE(dev_priv)) { @@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg; - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + cfgcr0_reg = ADLS_DPLL_CFGCR0(id); + cfgcr1_reg = ADLS_DPLL_CFGCR1(id); + } else if (IS_DG1(dev_priv)) { cfgcr0_reg = DG1_DPLL_CFGCR0(id); cfgcr1_reg = DG1_DPLL_CFGCR1(id); } else if (IS_ROCKETLAKE(dev_priv)) { @@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info adls_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, + { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, + { }, +}; + +static const struct intel_dpll_mgr adls_pll_mgr = { + .dpll_info = adls_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (IS_DG1(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + dpll_mgr = &adls_pll_mgr; + else if (IS_DG1(dev_priv)) dpll_mgr = &dg1_pll_mgr; else if (IS_ROCKETLAKE(dev_priv)) dpll_mgr = &rkl_pll_mgr; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 60a0d4c35cae..999b4eb422db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) #define HDPORT_STATE _MMIO(0x45050) -#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) #define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) #define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) #define HDPORT_ENABLED REG_BIT(0) @@ -10345,11 +10345,14 @@ enum skl_power_gate { /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 +#define _ADLS_DPLL2_ENABLE 0x46018 +#define _ADLS_DPLL3_ENABLE 0x46030 #define PLL_ENABLE (1 << 31) #define PLL_LOCK (1 << 30) #define PLL_POWER_ENABLE (1 << 27) #define PLL_POWER_STATE (1 << 26) -#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) +#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ + _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -10595,6 +10598,20 @@ enum skl_power_gate { _DG1_DPLL2_CFGCR1, \ _DG1_DPLL3_CFGCR1) +#define _ADLS_DPLL3_CFGCR0 0x1642C0 +#define _ADLS_DPLL4_CFGCR0 0x164294 +#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ + _TGL_DPLL1_CFGCR0, \ + _ADLS_DPLL3_CFGCR0, \ + _ADLS_DPLL4_CFGCR0) + +#define _ADLS_DPLL3_CFGCR1 0x1642C4 +#define _ADLS_DPLL4_CFGCR1 0x164298 +#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ + _TGL_DPLL1_CFGCR1, \ + _ADLS_DPLL3_CFGCR1, \ + _ADLS_DPLL4_CFGCR1) + #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 #define _DKL_PHY3_BASE 0x16A000 From patchwork Sat Dec 5 01:08:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ACA2C433FE for ; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEB0122D6F for ; Sat, 5 Dec 2020 01:09:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CEB0122D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D39446E239; Sat, 5 Dec 2020 01:09:07 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id C61CE6E222 for ; Sat, 5 Dec 2020 01:09:03 +0000 (UTC) IronPort-SDR: u2yHgUhRaDs9aa90jb1NgVHc8ThYWcSSLRKrR1PUTmN/BGNhZp+3EfWdWHT11WYirucKq534qu ycSFNF2nb0iA== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571006" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571006" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:03 -0800 IronPort-SDR: 86iZODcy2mEPKt6BGk45QTKuBKqs1j/+6sjoV9FXu/qoyF6Y2gadJjPszikZNblZ0ll2fvc6L9 poDKUNuIQx9A== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062925" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:03 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:31 -0800 Message-Id: <20201205010844.361880-10-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add changes to configure port clock registers for ADL-S. Combo phy port clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers. The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S translates to DDI A -> DDIA DDI B -> USBC1 DDI I -> USBC2 For DPCLKA_CFGCR1 DDI J -> USBC3 DDI K -> USBC4 Bspec: 50287 Bspec: 53812 Bspec: 53723 v2: Replace I915_READ() with intel_de_read().(Jani) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++++++++++++------- drivers/gpu/drm/i915/display/intel_display.c | 18 +++++- drivers/gpu/drm/i915/i915_reg.h | 23 ++++++- 3 files changed, 82 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 76e975b4765b..fdf692be2bc3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3088,25 +3088,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 val; + u32 val, mask, sel; + i915_reg_t reg; + + if (IS_ALDERLAKE_S(dev_priv)) { + reg = ADLS_DPCLKA_CFGCR(phy); + mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); + sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); + } else if (IS_ROCKETLAKE(dev_priv)) { + reg = ICL_DPCLKA_CFGCR0; + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + reg = ICL_DPCLKA_CFGCR0; + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, reg); drm_WARN_ON(&dev_priv->drm, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { - u32 mask, sel; - - if (IS_ROCKETLAKE(dev_priv)) { - mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } else { - mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } - /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -3119,12 +3124,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, */ val &= ~mask; val |= sel; - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); - intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); } val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, reg, val); mutex_unlock(&dev_priv->dpll.lock); } @@ -3150,9 +3155,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + if (IS_ALDERLAKE_S(dev_priv)) + val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy)); + else + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + + if (IS_ALDERLAKE_S(dev_priv)) + intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val); + else + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); mutex_unlock(&dev_priv->dpll.lock); } @@ -3192,13 +3205,19 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, u32 port_mask, bool ddi_clk_needed) { enum port port; + bool ddi_clk_off; u32 val; - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); for_each_port_masked(port, port_mask) { enum phy phy = intel_port_to_phy(dev_priv, port); - bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, - phy); + + if (IS_ALDERLAKE_S(dev_priv)) + val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy)); + else + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + + ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, + phy); if (ddi_clk_needed == !ddi_clk_off) continue; @@ -3214,7 +3233,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", phy_name(phy)); val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + if (IS_ALDERLAKE_S(dev_priv)) + intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val); + else + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); } } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2d1c5bfe4032..0ff0eeabab8c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11028,6 +11028,20 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc, return 0; } +static void adls_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, + struct intel_crtc_state *pipe_config) +{ + enum phy phy = intel_port_to_phy(dev_priv, port); + enum intel_dpll_id id; + u32 val; + + val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy)); + val &= ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); + id = val >> ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy); + + pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); +} + static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) { @@ -11401,7 +11415,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); } - if (IS_DG1(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + adls_get_ddi_pll(dev_priv, port, pipe_config); + else if (IS_DG1(dev_priv)) dg1_get_ddi_pll(dev_priv, port, pipe_config); else if (INTEL_GEN(dev_priv) >= 11) icl_get_ddi_pll(dev_priv, port, pipe_config); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 999b4eb422db..ce4ef7fa4000 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10307,7 +10307,7 @@ enum skl_power_gate { /* ICL Clocks */ #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ (tc_port) + 12 : \ @@ -10342,6 +10342,27 @@ enum skl_power_gate { #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \ (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy)) +/* ADLS Clocks */ +#define _ADLS_DPCLKA_CFGCR0 0x164280 +#define _ADLS_DPCLKA_CFGCR1 0x1642BC +#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ + _ADLS_DPCLKA_CFGCR0, \ + _ADLS_DPCLKA_CFGCR1) +#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) +/* ADLS DPCLKA_CFGCR0 DDI mask */ +#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) +#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) +#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) +/* ADLS DPCLKA_CFGCR1 DDI mask */ +#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) +#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) +#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ + ADLS_DPCLKA_DDIA_SEL_MASK, \ + ADLS_DPCLKA_DDIB_SEL_MASK, \ + ADLS_DPCLKA_DDII_SEL_MASK, \ + ADLS_DPCLKA_DDIJ_SEL_MASK, \ + ADLS_DPCLKA_DDIK_SEL_MASK) + /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 From patchwork Sat Dec 5 01:08:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1A26C4361A for ; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D28522D6F for ; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8D28522D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E727C6E2B6; Sat, 5 Dec 2020 01:09:08 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 144326E235 for ; Sat, 5 Dec 2020 01:09:05 +0000 (UTC) IronPort-SDR: k5u0NZRl3RerIBonUQn4TIVI6Qfaw/BjhyZumeDm1pgcku4IbVrzxeZpvw2fkVWQS9Ingiv265 IJQ9uBbCERQQ== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571009" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571009" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:04 -0800 IronPort-SDR: zz06BUWpWNy+/HHIT5Wb5p2zOLpu1W1hUy69FOip1Wu607i+TBBPugazGqAlt5RQnZ02Rk4Ey5 jSCeyT0Gj2AA== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062930" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:04 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:32 -0800 Message-Id: <20201205010844.361880-11-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Initialize display outputs for ADL-S. ADL-S has 5 display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs. Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0ff0eeabab8c..19ed51e6c647 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -17627,7 +17627,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + intel_ddi_init(dev_priv, PORT_A); + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + intel_ddi_init(dev_priv, PORT_F); /* DDI TC3 */ + intel_ddi_init(dev_priv, PORT_G); /* DDI TC4 */ + } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_TC1); From patchwork Sat Dec 5 01:08:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB2BEC4361B for ; Sat, 5 Dec 2020 01:09:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E12722D6F for ; Sat, 5 Dec 2020 01:09:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4E12722D6F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B28046E2B8; Sat, 5 Dec 2020 01:09:09 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2AA576E255 for ; Sat, 5 Dec 2020 01:09:06 +0000 (UTC) IronPort-SDR: qQHl6PVWIb1S+9gOVTtdgA6ID4Hh4vfZuyAkpQcdw0yai6PqnPw9b3DaTA/cNw1RpWMfCEnInv szYtPzvcnXQg== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571010" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571010" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:05 -0800 IronPort-SDR: 7Pg6YpgKaTpIAr6kJE+lZoQzioYJLpe62X0+DjZKruPOlif/EshEyrvfeyNghuY75DB4rPqRN0 WFO62wZ/uihg== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062940" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:05 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:33 -0800 Message-Id: <20201205010844.361880-12-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E. Combo PHY A still uses the old ddc pin mapping. From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI B->ddc_pin=2 should translate to PORT_D->0x9 DDI C->ddc_pin=3 should translate to PORT_E->0xa DDI D->ddc_pin=4 should translate to PORT_F->0xb DDI E->ddc_pin=5 should translate to PORT_G->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI B and DDI C info. Bspec:20124 v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing depends on the PCH being used rather than the platform.(mdroper) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4cc949b228f2..9dc67c03ffc0 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = { [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, }; +static const u8 adls_ddc_pin_map[] = { + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { const u8 *ddc_pin_map; int n_entries; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { + if (HAS_PCH_ADP(dev_priv)) { + ddc_pin_map = adls_ddc_pin_map; + n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { return vbt_pin; } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { ddc_pin_map = icp_ddc_pin_map; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index e10fdb369daa..060a13b63aa9 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return intel_port_to_phy(dev_priv, port) + 1; } +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + enum phy phy = intel_port_to_phy(dev_priv, port); + + WARN_ON(port == PORT_B || port == PORT_C); + + /* + * Pin mapping for ADL-S requires TC pins for all combo phy outputs + * except first combo output. + */ + if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B) + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; + + return GMBUS_PIN_1_BXT + phy; +} + static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { @@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + if (IS_ALDERLAKE_S(dev_priv)) + ddc_pin = adls_port_to_ddc_pin(dev_priv, port); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 49b4b5fca941..32d1b4f05760 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -325,6 +325,10 @@ enum vbt_gmbus_ddi { ICL_DDC_BUS_PORT_4, TGL_DDC_BUS_PORT_5, TGL_DDC_BUS_PORT_6, + ADLS_DDC_BUS_PORT_TC1 = 0x2, + ADLS_DDC_BUS_PORT_TC2, + ADLS_DDC_BUS_PORT_TC3, + ADLS_DDC_BUS_PORT_TC4 }; #define DP_AUX_A 0x40 From patchwork Sat Dec 5 01:08:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17AA4C433FE for ; Sat, 5 Dec 2020 01:09:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C1D8322D71 for ; Sat, 5 Dec 2020 01:09:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C1D8322D71 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 15DE36E2BC; Sat, 5 Dec 2020 01:09:10 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 792EE6E239 for ; Sat, 5 Dec 2020 01:09:07 +0000 (UTC) IronPort-SDR: 1JHOGMDb3i4VX2/ShFD6ScFkKf6p1nBU9qjtgwzyA5MVMKxgGtXgvqa17tXLIT0WylCQlFBV2U UEXn+iIbQ+iA== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571011" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571011" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:07 -0800 IronPort-SDR: HldRSO6kxiihh1u3SOdKw5FZyWzDxBYUAb2Og6Xlk3C45mWQ5unT11NROkNb0BTye1LNPMskVx jlUJ6g9O1V0g== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062948" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:06 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:34 -0800 Message-Id: <20201205010844.361880-13-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E. - Add ADLS specific port mappings for vbt port dvo settings. - Select appropriate AUX CH specific to ADLS based on port mapping. Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++----- 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 9dc67c03ffc0..8f166f49b6cc 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, }; + /* + * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E, + * PORT_F and PORT_G, we need to map that to correct VBT sections. + */ + static const int adls_port_mapping[][3] = { + [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, + [PORT_B] = { -1 }, + [PORT_C] = { -1 }, + [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, + [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, + [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, + [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, + }; - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping), + ARRAY_SIZE(adls_port_mapping[0]), + adls_port_mapping, + dvo_port); + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), ARRAY_SIZE(rkl_port_mapping[0]), rkl_port_mapping, @@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, return aux_ch; } + /* + * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D + * map to DDI A,B,TC1,TC2 respectively. + * + * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E + * map to DDI A,TC1,TC2,TC3,TC4 respectively. + */ switch (info->alternate_aux_channel) { case DP_AUX_A: aux_ch = AUX_CH_A; break; case DP_AUX_B: - aux_ch = AUX_CH_B; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC1; + else + aux_ch = AUX_CH_B; break; case DP_AUX_C: - /* - * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D - * map to DDI A,B,TC1,TC2 respectively. - */ - aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? - AUX_CH_USBC1 : AUX_CH_C; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC2; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + aux_ch = AUX_CH_USBC1; + else + aux_ch = AUX_CH_C; break; case DP_AUX_D: - aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? - AUX_CH_USBC2 : AUX_CH_D; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC3; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + aux_ch = AUX_CH_USBC2; + else + aux_ch = AUX_CH_D; break; case DP_AUX_E: - aux_ch = AUX_CH_E; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC4; + else + aux_ch = AUX_CH_E; break; case DP_AUX_F: aux_ch = AUX_CH_F; From patchwork Sat Dec 5 01:08:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73CEBC4167B for ; Sat, 5 Dec 2020 01:09:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C36622D71 for ; Sat, 5 Dec 2020 01:09:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C36622D71 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 549FE6E2C0; Sat, 5 Dec 2020 01:09:10 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B57596E255 for ; Sat, 5 Dec 2020 01:09:08 +0000 (UTC) IronPort-SDR: 37mwY8d+jwjck+cm5M7AVDDoWNj678Bj4HlQk8Gkz0Pcs3FAV6+CkadDeadHtGa+MuCWamt4zs vdwe4wFfnzzw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571017" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571017" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:08 -0800 IronPort-SDR: gaV7VyMQsRO1EQ4E7gKuEYRiJcy0UEuB6a9wXA1zDp/9VgAhVzx398luKtSbxhVnGBgPWc66d1 32iDnZ74RXfQ== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062968" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:08 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:35 -0800 Message-Id: <20201205010844.361880-14-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/22] drm/i915/adl_s: Update combo PHY master/slave relationships X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 996ae0608a62..dd45cbafcf42 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) * RKL,DG1: * A(master) -> B(slave) * C(master) -> D(slave) + * ADL-S: + * A(master) -> B(slave), C(slave) + * D(master) -> E(slave) * * We must set the IREFGEN bit for any PHY acting as a master * to another PHY. */ - if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C) + if (phy == PHY_A) return true; + else if (IS_ALDERLAKE_S(dev_priv)) + return phy == PHY_D; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + return phy == PHY_C; - return phy == PHY_A; + return false; } static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, From patchwork Sat Dec 5 01:08:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51AF1C4167B for ; Sat, 5 Dec 2020 01:09:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1AE9322D70 for ; Sat, 5 Dec 2020 01:09:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1AE9322D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B67D96E2D1; Sat, 5 Dec 2020 01:09:18 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03CFE6E255 for ; Sat, 5 Dec 2020 01:09:09 +0000 (UTC) IronPort-SDR: C8LIn3y+jXXtmF4r0rKgT0ODgdfiVieqnGAm00VBRgt8wGuStqvrcTE8N0bPjuowBE8uCiuUNt eLWa4vMSwbNg== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571021" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571021" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:09 -0800 IronPort-SDR: gdnyMRjGiyVettvOi3DbzKsVrUEfjKmNFZpP2GlYSLoNN583fi5vcgN2j7+5M1dHY3ULTBLb5L 5ZNBhnNqYkfA== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062976" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:09 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:36 -0800 Message-Id: <20201205010844.361880-15-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 14/22] drm/i915/adl_s: Update PHY_MISC programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index dd45cbafcf42..c55813c6194a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * Some platforms only expect PHY_MISC to be programmed for PHY-A and * PHY-B and may not even have instances of the register for the * other combo PHY's. + * + * ADL-S technically has three instances of PHY_MISC, but only requires + * that we program it for PHY A. */ - if (IS_JSL_EHL(i915) || - IS_ROCKETLAKE(i915) || - IS_DG1(i915)) + + if (IS_ALDERLAKE_S(i915)) + return phy == PHY_A; + else if (IS_JSL_EHL(i915) || + IS_ROCKETLAKE(i915) || + IS_DG1(i915)) return phy < PHY_C; return true; From patchwork Sat Dec 5 01:08:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53CD0C0018C for ; Sat, 5 Dec 2020 01:09:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C71722D70 for ; Sat, 5 Dec 2020 01:09:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C71722D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6341A6E2C7; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFA316E2C8 for ; Sat, 5 Dec 2020 01:09:10 +0000 (UTC) IronPort-SDR: dB/zATaUKqm7jooQ02nubIwoWz3tu2MlyXorKqRlNYhAgUBzQfMjFLeRkE2xDS09rQ3yCZ8qOv NmKJRJSUdRDA== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571025" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571025" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:10 -0800 IronPort-SDR: zg3sCKIjm+DpkLHQbxL/8D0jT5mMRiSxt3OBXp4XwoP1Zg/siMmd3x5wtekZlgu8FGh1REbvPa 6gPy4tsf4deA== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062981" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:10 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:37 -0800 Message-Id: <20201205010844.361880-16-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 15/22] drm/i915/adl_s: Add display WAs for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" - Extend permanent driver WA Wa_1409767108, Wa_14010685332 and Wa_14011294188 to adl-s. - Extend permanent driver WA Wa_1606054188 to adl-s. - Add Wa_14011765242 for adl-s A0 stepping. Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_display_power.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++-- drivers/gpu/drm/i915/intel_device_info.c | 6 +++++- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 06c036e2092c..8b163d804a41 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask; int config, i; - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || + if (IS_ALDERLAKE_S(dev_priv) || + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0)) - /* Wa_1409767108:tgl,dg1 */ + /* Wa_1409767108:tgl,dg1,adl-s */ table = wa_1409767108_buddy_page_masks; else table = tgl_buddy_page_masks; @@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - /* Wa_14011294188:ehl,jsl,tgl,rkl */ + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1) intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e19d4f873b94..2d820ff2b236 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2371,8 +2371,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, return -EINVAL; } - /* Wa_1606054188:tgl */ - if (IS_TIGERLAKE(dev_priv) && + /* Wa_1606054188:tgl,adl-s */ + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && intel_format_is_p01x(fb->format->format)) { drm_dbg_kms(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ce8c69c17b8e..da651ef10014 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); enum pipe pipe; - if (INTEL_GEN(dev_priv) >= 10) { + /* Wa_14011765242: adl-s A0 */ + if (IS_ADLS_DISP_REVID(dev_priv, REVID_A0, REVID_A0)) + for_each_pipe(dev_priv, pipe) + runtime->num_scalers[pipe] = 0; + else if (INTEL_GEN(dev_priv) >= 10) { for_each_pipe(dev_priv, pipe) runtime->num_scalers[pipe] = 2; } else if (IS_GEN(dev_priv, 9)) { From patchwork Sat Dec 5 01:08:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5C6BC4361A for ; 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a="173571027" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571027" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:11 -0800 IronPort-SDR: 3a0Tt69MA89ulOKCWHj/pDrJUIkLxt39Yrsj+WyMwOzZed4A1NRZnpYrUgMTVKsB6wHJKyj1c0 5iOQ17RBRRlw== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062990" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:11 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:38 -0800 Message-Id: <20201205010844.361880-17-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/22] drm/i915/adl_s: Add GT and CTX WAs for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" - Add placeholders for gt and ctx WAs for ADL-S - Extend Wa_1606931601 and Wa_1409804808 to ADL-S. - Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha) - Extend Wa_22010271021 to ADLS (cyokoyam) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++------- 1 file changed, 61 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3db57b577a79..1a1958d3e617 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { gen12_ctx_workarounds_init(engine, wal); - - /* - * Wa_1604555607:tgl,rkl - * - * Note that the implementation of this workaround is further modified - * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. - * FF_MODE2 register will return the wrong value when read. The default - * value for this register is zero for all fields and there are no bit - * masks. So instead of doing a RMW we should just write the GS Timer - * and TDS timer values for Wa_1604555607 and Wa_16011163337. - */ - wa_add(wal, - FF_MODE2, - FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, - 0); } static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -696,6 +680,12 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); } +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); +} + static void __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, struct i915_wa_list *wal, @@ -708,7 +698,31 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_DG1(i915)) + if (INTEL_GEN(i915) >= 12) { + /* + * This setting isn't actually a workaround, but is a general + * tuning setting that needs to be programmed on all platforms + * gen12+. Although some platforms also refer to this setting + * as Wa_1604555607, we need to program it even on platforms that + * don't explicitly list that workaround. + * + * Note that the implementation is further modified according + * to the FF_MODE2 guidance given by Wa_1608008084:gen12. + * FF_MODE2 register will return the wrong value when read. + * The default value for this register is zero for all fields + * and there are no bit masks. So instead of doing a RMW, we + * should just write the value directly. + */ + wa_add(wal, + FF_MODE2, + FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_TDS_TIMER_128, + 0); + } + + if (IS_ALDERLAKE_S(i915)) + adls_ctx_workarounds_init(engine, wal); + else if (IS_DG1(i915)) dg1_ctx_workarounds_init(engine, wal); else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); @@ -1294,10 +1308,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } +static void +adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); +} + static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_DG1(i915)) + if (IS_ALDERLAKE_S(i915)) + adls_gt_workarounds_init(i915, wal); + else if (IS_DG1(i915)) dg1_gt_workarounds_init(i915, wal); else if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); @@ -1678,6 +1700,11 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_ACCESS_RD); } +static void adls_whitelist_build(struct intel_engine_cs *engine) +{ + tgl_whitelist_build(engine); +} + void intel_engine_init_whitelist(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; @@ -1685,7 +1712,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) wa_init_start(w, "whitelist", engine->name); - if (IS_DG1(i915)) + if (IS_ALDERLAKE_S(i915)) + adls_whitelist_build(engine); + else if (IS_DG1(i915)) dg1_whitelist_build(engine); else if (IS_GEN(i915, 12)) tgl_whitelist_build(engine); @@ -1766,22 +1795,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl,rkl,dg1 */ + if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) || + IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl,dg1,adl-s */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); /* * Wa_1407928979:tgl A* * Wa_18011464164:tgl[B0+],dg1[B0+] * Wa_22010931296:tgl[B0+],dg1[B0+] - * Wa_14010919138:rkl, dg1 + * Wa_14010919138:rkl,dg1,adl-s */ wa_write_or(wal, GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE); /* * Wa_1606700617:tgl,dg1 - * Wa_22010271021:tgl,rkl,dg1 + * Wa_22010271021:tgl,rkl,dg1, adl-s */ wa_masked_en(wal, GEN9_CS_DEBUG_MODE1, @@ -1793,15 +1823,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) ENABLE_SMALLPL); } - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || + if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1409804808:tgl,rkl,dg1[a0] */ + /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); /* * Wa_1409085225:tgl - * Wa_14010229206:tgl,rkl,dg1[a0] + * Wa_14010229206:tgl,rkl,dg1[a0],adl-s */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); @@ -1815,10 +1845,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * it applies to all steppings so we trust the "all steppings." * For DG1 this only applies to A0. */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); + if (!IS_ALDERLAKE_S(i915)) + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); } if (IS_GEN(i915, 11)) { From patchwork Sat Dec 5 01:08:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0123AC4361B for ; Sat, 5 Dec 2020 01:09:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C00C122D70 for ; Sat, 5 Dec 2020 01:09:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C00C122D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9AE606E2D8; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 051AA6E2C7 for ; Sat, 5 Dec 2020 01:09:12 +0000 (UTC) IronPort-SDR: USn9M6kUXVprClUQPpUy1RuoZOUbdW+7qorwDE0TuFh8wyGHYxe4M0qqjvwW2c9B5beiUK5Mji Ovgj0ongvLYw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571031" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571031" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:12 -0800 IronPort-SDR: PqbP0DKzYV8Ns2463+PcwLwGnpAP2ffrBpT9Il4OjV+R62ogUIrmo2D+wulE2EfYgxgaQYaeqx x+PsNGIR5ckg== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062997" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:12 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:39 -0800 Message-Id: <20201205010844.361880-18-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama The crwebview indicates on ADL-S that some of our MCHBAR registers have moved from their traditional 0x50XX offsets to new locations. The meaning and bit layout of the registers remain same. v2: Simplify logic to a single if else chain and fix indents.(Lucas) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Signed-off-by: Caz Yokoyama Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_dram.c | 23 +++++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce4ef7fa4000..55e186293fbb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10865,6 +10865,8 @@ enum skl_power_gate { #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048) + #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) #define SKL_DRAM_S_SHIFT 16 @@ -10892,6 +10894,9 @@ enum skl_power_gate { #define CNL_DRAM_RANK_3 (0x2 << 9) #define CNL_DRAM_RANK_4 (0x3 << 9) +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054) +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058) + /* * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using intel_uncore_write. diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 4754296a250e..fc9942139ccc 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915) { struct dram_info *dram_info = &i915->dram_info; struct dram_channel_info ch0 = {}, ch1 = {}; + i915_reg_t ch0_reg, ch1_reg; u32 val; int ret; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); + if (IS_ALDERLAKE_S(i915)) { + ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR; + ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR; + } else { + ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR; + ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR; + } + + val = intel_uncore_read(&i915->uncore, ch0_reg); ret = skl_dram_get_channel_info(i915, &ch0, 0, val); if (ret == 0) dram_info->num_channels++; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); + val = intel_uncore_read(&i915->uncore, ch1_reg); ret = skl_dram_get_channel_info(i915, &ch1, 1, val); if (ret == 0) dram_info->num_channels++; @@ -231,8 +238,12 @@ skl_get_dram_type(struct drm_i915_private *i915) { u32 val; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); + if (IS_ALDERLAKE_S(i915)) + val = intel_uncore_read(&i915->uncore, + ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR); + else + val = intel_uncore_read(&i915->uncore, + SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); switch (val & SKL_DRAM_DDR_TYPE_MASK) { case SKL_DRAM_DDR_TYPE_DDR3: From patchwork Sat Dec 5 01:08:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08E9EC4361A for ; Sat, 5 Dec 2020 01:09:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBFC122D70 for ; Sat, 5 Dec 2020 01:09:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CBFC122D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 252786E2DE; Sat, 5 Dec 2020 01:09:19 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id A2B9F6E2C7 for ; Sat, 5 Dec 2020 01:09:13 +0000 (UTC) IronPort-SDR: 3/2+WZjDqZiLzzG/eQBu0+VIi05AOCVOCoJquxYwRWwblPrYdadUyLS+hSsajNPP4DFgh0TNtG hqcZqhgatVCw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571038" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571038" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:13 -0800 IronPort-SDR: e8fAwq8bv/1sc/6A4aKPmnmayn3pSars3qTvTkywwdFlFG6R8BQkqTGXX59wrfm6WmMrYUIvvO luEy94nYwkew== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369063007" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:13 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:40 -0800 Message-Id: <20201205010844.361880-19-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 18/22] drm/i915/adl_s: Add power wells X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Lucas De Marchi TGL power wells can be re-used for ADL-S with the exception of the fake power well for TC_COLD, just like DG-1. Bspec: 53597 Cc: Imre Deak Cc: Matt Roper Cc: Aditya Swarup Signed-off-by: Lucas De Marchi Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 8b163d804a41..152cf4a6826d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4632,7 +4632,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) { From patchwork Sat Dec 5 01:08:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A05B6C433FE for ; Sat, 5 Dec 2020 01:09:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67EB522D70 for ; Sat, 5 Dec 2020 01:09:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 67EB522D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6690F6E2DC; Sat, 5 Dec 2020 01:09:16 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94A836E2D5 for ; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) IronPort-SDR: gpzBnPd39zjWG430qCrfpP5KC5bg2NZDOf/AkLdoZlUvd3XjINxi+0QURFFXRuUcuLMJCAiHlB 7YAxQY6zWC+g== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571040" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571040" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:14 -0800 IronPort-SDR: JoS1pnJ4LKkBSYUXwyS8St6CsIwl+jQH1oTS8jrLSjmiJTKs4/1dPbp+ljDch0C6yfiZ6Vl5Gq 7fPNXEJwXSiA== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369063012" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:13 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:41 -0800 Message-Id: <20201205010844.361880-20-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 19/22] drm/i915/adl_s: Re-use TGL GuC/HuC firmware X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as TGL did, making them all firmware-compatible. Let's re-use TGL's firmware for ADL-S. Bspec: 50668 Cc: John Harrison Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 180c23e2e25e..2d123158df0d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * List of required GuC and HuC binaries per-platform. * Must be ordered based on platform + revid, from newer to older. * - * Note that RKL uses the same firmware as TGL. + * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same + * firmware as TGL. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(JASPERLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl, 9, 0, 0)) \ From patchwork Sat Dec 5 01:08:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1009C0018C for ; Sat, 5 Dec 2020 01:09:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AD4EE22D70 for ; Sat, 5 Dec 2020 01:09:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AD4EE22D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 186DE6E2E1; Sat, 5 Dec 2020 01:09:20 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 992B76E2D1 for ; Sat, 5 Dec 2020 01:09:15 +0000 (UTC) IronPort-SDR: ns6mtb1mIGcwbdaG0YGwUOgx2RK13BraAtslNcqc2ZSjDCDPS/1FFaxD1UvaV3M3Q6jc3brgLz UQt23/GEDA6Q== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571042" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571042" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:15 -0800 IronPort-SDR: rQA456zC5lgfpLwoMY9ZqtrDIAww+xGfE8cMyFAdeQYlxUfou7OWv2Pk7aFLf0PYhId0vwa2iR YB9dGnGibfYQ== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369063045" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:14 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:42 -0800 Message-Id: <20201205010844.361880-21-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 20/22] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza - As RKL and ADL-S only have 5 planes, primary and 4 sprites and the cursor plane, let's group the handling together under HAS_D12_PLANE_MINIMIZATION. - Also use macro to select pipe irq fault error mask. BSpec: 49251 Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 2d820ff2b236..10176b174e50 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -366,7 +366,7 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) { - if (IS_ROCKETLAKE(i915)) + if (HAS_D12_PLANE_MINIMIZATION(i915)) return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); else return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 91bd262dd871..1d710d9d8dee 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1796,6 +1796,9 @@ extern const struct i915_rev_steppings adls_revids[]; #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) +#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ + IS_ALDERLAKE_S(dev_priv)) + static inline bool intel_vtd_active(void) { #ifdef CONFIG_INTEL_IOMMU diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d1b4893d6c92..bcb0f7c96c65 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) { - if (IS_ROCKETLAKE(dev_priv)) + if (HAS_D12_PLANE_MINIMIZATION(dev_priv)) return RKL_DE_PIPE_IRQ_FAULT_ERRORS; else if (INTEL_GEN(dev_priv) >= 11) return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index da651ef10014..c94a52642f32 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); - if (IS_ROCKETLAKE(dev_priv)) + if (HAS_D12_PLANE_MINIMIZATION(dev_priv)) for_each_pipe(dev_priv, pipe) runtime->num_sprites[pipe] = 4; else if (INTEL_GEN(dev_priv) >= 11) From patchwork Sat Dec 5 01:08:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61A22C4361B for ; Sat, 5 Dec 2020 01:09:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C6DF22D70 for ; Sat, 5 Dec 2020 01:09:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C6DF22D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE0096E2DF; Sat, 5 Dec 2020 01:09:19 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id D023D6E2D5 for ; Sat, 5 Dec 2020 01:09:17 +0000 (UTC) IronPort-SDR: wW2O8UBm0H9+XfIUGM2BKZ2VftVl9C5kbD7PMQwOlo/zRyvNpB9ry/Oh0kv+kaY58g68YHs8Tv YdZU1TdMB/sw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571050" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571050" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:17 -0800 IronPort-SDR: Ttq9PDwcgljxi1WRUVn7qrRFQSVfx4nBRWanv+F34a//ZJMtk9z8w+tmzL1rm9ukt7G8Vvg221 oAuUIWELNzFw== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369063088" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:17 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:43 -0800 Message-Id: <20201205010844.361880-22-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 21/22] drm/i915/adl_s: Load DMC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Load DMC on ADL_S v2.01. This is the first offcial release of DMC for ADL_S. Cc: Jani Nikula Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Cc: Aditya Swarup Signed-off-by: Anusha Srivatsa Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_csr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 67dc64df78a5..db9f219c4b5a 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -40,6 +40,10 @@ #define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define ADLS_CSR_PATH "i915/adls_dmc_ver2_01.bin" +#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) +MODULE_FIRMWARE(ADLS_CSR_PATH); + #define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin" #define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) MODULE_FIRMWARE(DG1_CSR_PATH); @@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) */ intel_csr_runtime_pm_get(dev_priv); - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + csr->fw_path = ADLS_CSR_PATH; + csr->required_version = ADLS_CSR_VERSION_REQUIRED; + csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + } else if (IS_DG1(dev_priv)) { csr->fw_path = DG1_CSR_PATH; csr->required_version = DG1_CSR_VERSION_REQUIRED; csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; From patchwork Sat Dec 5 01:08:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA1D9C433FE for ; Sat, 5 Dec 2020 01:09:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3D6322D70 for ; Sat, 5 Dec 2020 01:09:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B3D6322D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3282F6E2E6; Sat, 5 Dec 2020 01:09:23 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBE2C6E2D5 for ; Sat, 5 Dec 2020 01:09:18 +0000 (UTC) IronPort-SDR: h5K480U9CIY4ReHJQ3oh7AjZllEbSjaagWANvZV2w1zgg/zhimaC30qmYu+McFBZH8i6dCP9XJ P6STHx10lFdw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571053" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571053" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:18 -0800 IronPort-SDR: DlLx+zu4lBlFNi1wTyg+BJwAWZxK3zQPuroZgZa9k0VSwp9zsiuVfaNLKaeO6f/aHHgQkotZX0 SSSNhv487wKg== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369063103" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:18 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:44 -0800 Message-Id: <20201205010844.361880-23-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 22/22] drm/i915/adl_s: Update memory bandwidth parameters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tejas Upadhyay Just like RKL, the ADL_S platform also has different memory characteristics from past platforms. Update the values used by our memory bandwidth calculations accordingly. Bspec: 64631 Cc: Matt Roper Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Signed-off-by: Tejas Upadhyay Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index bd060404d249..32522ec1ffb9 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = { .displayrtids = 128, }; +static const struct intel_sa_info adls_sa_info = { + .deburst = 16, + .deprogbwlimit = 38, /* GB/s */ + .displayrtids = 256, +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (IS_ROCKETLAKE(dev_priv)) icl_get_bw_info(dev_priv, &rkl_sa_info); + else if (IS_ALDERLAKE_S(dev_priv)) + icl_get_bw_info(dev_priv, &adls_sa_info); else if (IS_GEN(dev_priv, 12)) icl_get_bw_info(dev_priv, &tgl_sa_info); else if (IS_GEN(dev_priv, 11))