From patchwork Mon Dec 7 09:17:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuosheng Huang X-Patchwork-Id: 11955171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0046C433FE for ; Mon, 7 Dec 2020 09:19:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 993E723437 for ; Mon, 7 Dec 2020 09:19:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 993E723437 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=allwinnertech.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Ua+EzkI/FV+8J4yB+aVjX2h77wL8SxhaoZF89X0Vw70=; b=WnCUzL392zmeRVpuPBe0EpBa3a 7aHrETpJ9DT2kxjtnDJ/WVj3iOt+xh3VxqFMnHLRO93twR9jEffnFxHlCujLXPD5X1NOSQUZYRu28 7oR4Qhqoe7EmQIrpUBl6tVDPC9xByDndneIbVXtxWeUo7SuBwQhevwJEXZkZja/h8GBdEGvAhNOdY anKlqQTy/SEvpPJ08A0jeDvopAkJOIKFlYLhzZ9H12NAf2VkI3Wa/K6TaJqeLQ+WHFTQMD9zI/Gfi Dh1vbl8gvKTnvXgM+yIQt141a8HBL8B0PBVbeHofR+7q70Lo5ddyk0337L9CKls4YBFzIXHL8p2ok FoI0YAcw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmCeK-0001Iu-Pw; Mon, 07 Dec 2020 09:17:40 +0000 Received: from smtp2207-205.mail.aliyun.com ([121.197.207.205]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmCeD-0001Dg-GQ for linux-arm-kernel@lists.infradead.org; Mon, 07 Dec 2020 09:17:36 +0000 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07437193|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0217741-0.00249463-0.975731; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=huangshuosheng@allwinnertech.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.J42KvvE_1607332641; Received: from allwinnertech.com(mailfrom:huangshuosheng@allwinnertech.com fp:SMTPD_---.J42KvvE_1607332641) by smtp.aliyun-inc.com(10.147.43.230); Mon, 07 Dec 2020 17:17:25 +0800 From: Shuosheng Huang To: tiny.windzz@gmail.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, mripard@kernel.org, wens@csie.org, jernej.skrabec@siol.net Subject: [PATCH V2 1/3] cpufreq: sun50i: add efuse_xlate to get efuse version. Date: Mon, 7 Dec 2020 17:17:16 +0800 Message-Id: <20201207091716.17492-1-huangshuosheng@allwinnertech.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_041733_814480_DA4B8476 X-CRM114-Status: GOOD ( 16.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shuosheng Huang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It's better to use efuse_xlate to extract the differentiated part regarding different SoC. Signed-off-by: Shuosheng Huang --- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 72 +++++++++++++++++--------- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c index 9907a165135b..da23d581a4b4 100644 --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c @@ -22,21 +22,52 @@ #define NVMEM_MASK 0x7 #define NVMEM_SHIFT 5 +#define SUN50I_H6_NVMEM_MASK 0x7 +#define SUN50I_H6_NVMEM_SHIFT 5 + +struct sunxi_cpufreq_soc_data { + u32 (*efuse_xlate)(void *efuse); +}; + static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev; +static u32 sun50i_h6_efuse_xlate(struct nvmem_cell *speedbin_nvmem) +{ + size_t len; + u32 *speedbin; + u32 efuse_value; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + efuse_value = (*(u32 *)speedbin >> SUN50I_H6_NVMEM_SHIFT) & + SUN50I_H6_NVMEM_MASK; + kfree(speedbin); + /* + * We treat unexpected efuse values as if the SoC was from + * the slowest bin. Expected efuse values are 1-3, slowest + * to fastest. + */ + if (efuse_value >= 1 && efuse_value <= 3) + return efuse_value - 1; + else + return 0; +} + /** * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value + * @soc_data: pointer to sunxi_cpufreq_soc_data context * @versions: Set to the value parsed from efuse * * Returns 0 if success. */ -static int sun50i_cpufreq_get_efuse(u32 *versions) +static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data, + u32 *versions) { struct nvmem_cell *speedbin_nvmem; struct device_node *np; struct device *cpu_dev; - u32 *speedbin, efuse_value; - size_t len; int ret; cpu_dev = get_cpu_device(0); @@ -63,41 +94,31 @@ static int sun50i_cpufreq_get_efuse(u32 *versions) return PTR_ERR(speedbin_nvmem); } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); + *versions = soc_data->efuse_xlate(speedbin_nvmem); nvmem_cell_put(speedbin_nvmem); - if (IS_ERR(speedbin)) - return PTR_ERR(speedbin); - - efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK; - - /* - * We treat unexpected efuse values as if the SoC was from - * the slowest bin. Expected efuse values are 1-3, slowest - * to fastest. - */ - if (efuse_value >= 1 && efuse_value <= 3) - *versions = efuse_value - 1; - else - *versions = 0; - kfree(speedbin); return 0; }; static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct opp_table **opp_tables; char name[MAX_NAME_LEN]; unsigned int cpu; u32 speed = 0; int ret; + match = dev_get_platdata(&pdev->dev); + if (!match) + return -EINVAL; + opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); if (!opp_tables) return -ENOMEM; - ret = sun50i_cpufreq_get_efuse(&speed); + ret = sun50i_cpufreq_get_efuse(match->data, &speed); if (ret) return ret; @@ -163,8 +184,12 @@ static struct platform_driver sun50i_cpufreq_driver = { }, }; +static const struct sunxi_cpufreq_soc_data sun50i_h6_data = { + .efuse_xlate = sun50i_h6_efuse_xlate, +}; + static const struct of_device_id sun50i_cpufreq_match_list[] = { - { .compatible = "allwinner,sun50i-h6" }, + { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data }, {} }; @@ -198,9 +223,8 @@ static int __init sun50i_cpufreq_init(void) if (unlikely(ret < 0)) return ret; - sun50i_cpufreq_pdev = - platform_device_register_simple("sun50i-cpufreq-nvmem", - -1, NULL, 0); + sun50i_cpufreq_pdev = platform_device_register_data(NULL, + "sun50i-cpufreq-nvmem", -1, match, sizeof(*match)); ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev); if (ret == 0) return 0; From patchwork Mon Dec 7 09:18:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuosheng Huang X-Patchwork-Id: 11955173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB99EC433FE for ; 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NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.J415HFU_1607332709; Received: from allwinnertech.com(mailfrom:huangshuosheng@allwinnertech.com fp:SMTPD_---.J415HFU_1607332709) by smtp.aliyun-inc.com(10.147.44.145); Mon, 07 Dec 2020 17:18:33 +0800 From: Shuosheng Huang To: tiny.windzz@gmail.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, mripard@kernel.org, wens@csie.org, jernej.skrabec@siol.net Subject: [PATCH V2 2/3] cpufreq: sun50i: add a100 cpufreq support Date: Mon, 7 Dec 2020 17:18:27 +0800 Message-Id: <20201207091827.31529-1-huangshuosheng@allwinnertech.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_041842_453972_4C4D4BDC X-CRM114-Status: GOOD ( 13.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shuosheng Huang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cpufreq nvmem based for allwinner a100 SoC, it's similar to h6. Signed-off-by: Shuosheng Huang --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/sun50i-cpufreq-nvmem.c | 32 ++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 3776d960f405..2ebf5d9cb616 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -102,6 +102,7 @@ static const struct of_device_id whitelist[] __initconst = { */ static const struct of_device_id blacklist[] __initconst = { { .compatible = "allwinner,sun50i-h6", }, + { .compatible = "allwinner,sun50i-a100", }, { .compatible = "calxeda,highbank", }, { .compatible = "calxeda,ecx-2000", }, diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c index da23d581a4b4..def4a19abe16 100644 --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c @@ -25,6 +25,9 @@ #define SUN50I_H6_NVMEM_MASK 0x7 #define SUN50I_H6_NVMEM_SHIFT 5 +#define SUN50I_A100_NVMEM_MASK 0xf +#define SUN50I_A100_NVMEM_SHIFT 12 + struct sunxi_cpufreq_soc_data { u32 (*efuse_xlate)(void *efuse); }; @@ -55,6 +58,30 @@ static u32 sun50i_h6_efuse_xlate(struct nvmem_cell *speedbin_nvmem) return 0; } +static u32 sun50i_a100_efuse_xlate(struct nvmem_cell *speedbin_nvmem) +{ + size_t len; + u32 *speedbin; + u32 efuse_value; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) & + SUN50I_A100_NVMEM_MASK; + kfree(speedbin); + + switch (efuse_value) { + case 0b100: + return 2; + case 0b010: + return 1; + default: + return 0; + } +} + /** * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value * @soc_data: pointer to sunxi_cpufreq_soc_data context @@ -188,8 +215,13 @@ static const struct sunxi_cpufreq_soc_data sun50i_h6_data = { .efuse_xlate = sun50i_h6_efuse_xlate, }; +static const struct sunxi_cpufreq_soc_data sun50i_a100_data = { + .efuse_xlate = sun50i_a100_efuse_xlate, +}; + static const struct of_device_id sun50i_cpufreq_match_list[] = { { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data }, + { .compatible = "allwinner,sun50i-a100", .data = &sun50i_a100_data }, {} }; From patchwork Mon Dec 7 09:19:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuosheng Huang X-Patchwork-Id: 11955179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFBD9C4167B for ; Mon, 7 Dec 2020 09:21:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6FCC9236F9 for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmCgh-00027s-RN; Mon, 07 Dec 2020 09:20:07 +0000 Received: from smtp2207-205.mail.aliyun.com ([121.197.207.205]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmCgd-00025V-Uj for linux-arm-kernel@lists.infradead.org; Mon, 07 Dec 2020 09:20:05 +0000 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07449924|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.600806-0.00119886-0.397995; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047207; MF=huangshuosheng@allwinnertech.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.J42Kx0o_1607332795; Received: from allwinnertech.com(mailfrom:huangshuosheng@allwinnertech.com fp:SMTPD_---.J42Kx0o_1607332795) by smtp.aliyun-inc.com(10.147.43.230); Mon, 07 Dec 2020 17:19:57 +0800 From: Shuosheng Huang To: robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, jernej.skrabec@siol.net, tiny.windzz@gmail.com Subject: [PATCH V2 3/3] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table Date: Mon, 7 Dec 2020 17:19:53 +0800 Message-Id: <20201207091953.15451-1-huangshuosheng@allwinnertech.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_042004_371045_AE2D37D0 X-CRM114-Status: GOOD ( 13.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Shuosheng Huang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the A100. Signed-off-by: Shuosheng Huang --- .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++ .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++ .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts index d34c2bb1079f..7c579923f973 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" /{ model = "Allwinner A100 Perf1"; @@ -20,6 +21,10 @@ chosen { }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &pio { vcc-pb-supply = <®_dcdc1>; vcc-pc-supply = <®_eldo1>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi new file mode 100644 index 000000000000..e245823d70e8 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Yangtao Li +// Copyright (c) 2020 ShuoSheng Huang + +/ { + cpu_opp_table: cpu-opp-table { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp@408000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <408000000>; + + opp-microvolt-speed0 = <900000 900000 1200000>; + opp-microvolt-speed1 = <900000 900000 1200000>; + opp-microvolt-speed2 = <900000 900000 1200000>; + }; + + opp@600000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <600000000>; + + opp-microvolt-speed0 = <900000 900000 1200000>; + opp-microvolt-speed1 = <900000 900000 1200000>; + opp-microvolt-speed2 = <900000 900000 1200000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <940000 940000 1200000>; + opp-microvolt-speed1 = <900000 900000 1200000>; + opp-microvolt-speed2 = <900000 900000 1200000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1020000 1020000 1200000>; + opp-microvolt-speed1 = <980000 980000 1200000>; + opp-microvolt-speed2 = <950000 950000 1200000>; + }; + + opp@1200000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1200000000>; + + opp-microvolt-speed0 = <1100000 1100000 1200000>; + opp-microvolt-speed1 = <1020000 1020000 1200000>; + opp-microvolt-speed2 = <1000000 1000000 1200000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1160000 1160000 1200000>; + opp-microvolt-speed1 = <1060000 1060000 1200000>; + opp-microvolt-speed2 = <1030000 1030000 1200000>; + }; + + opp@1464000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1464000000>; + + opp-microvolt-speed0 = <1180000 1180000 1200000>; + opp-microvolt-speed1 = <1180000 1180000 1200000>; + opp-microvolt-speed2 = <1130000 1130000 1200000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index cc321c04f121..8f370a175ce6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -23,6 +23,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu@1 { @@ -30,6 +31,7 @@ cpu@1 { device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu@2 { @@ -37,6 +39,7 @@ cpu@2 { device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu@3 { @@ -44,6 +47,7 @@ cpu@3 { device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; }; @@ -121,6 +125,10 @@ efuse@3006000 { ths_calibration: calib@14 { reg = <0x14 8>; }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x2>; + }; }; pio: pinctrl@300b000 {