From patchwork Mon Dec 7 16:42:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jae Hyun Yoo X-Patchwork-Id: 11956385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6059C2BBD4 for ; Mon, 7 Dec 2020 16:35:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B64A4238E7 for ; Mon, 7 Dec 2020 16:35:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727833AbgLGQeo (ORCPT ); Mon, 7 Dec 2020 11:34:44 -0500 Received: from mga12.intel.com ([192.55.52.136]:51459 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727794AbgLGQeo (ORCPT ); Mon, 7 Dec 2020 11:34:44 -0500 IronPort-SDR: ei9Oyq3gbTZS8xmaxnSrHwshuohi64F0sqkYqVUKITdsx4jFP2Vw38m+bXvy1xBWiZA9PBn187 whXgpuP3/cCw== X-IronPort-AV: E=McAfee;i="6000,8403,9827"; a="152970139" X-IronPort-AV: E=Sophos;i="5.78,400,1599548400"; d="scan'208";a="152970139" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2020 08:32:58 -0800 IronPort-SDR: Wd59LJBOxhnFNEMnSB4YiYGljaOcvTaL6kMR1eLzOYIANqgyRTptzL6swotMqeIoPVIKTtLtPq aBj1cmiJ0cFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,400,1599548400"; d="scan'208";a="317246226" Received: from maru.jf.intel.com ([10.54.51.77]) by fmsmga008.fm.intel.com with ESMTP; 07 Dec 2020 08:32:58 -0800 From: Jae Hyun Yoo To: Joel Stanley , Andrew Jeffery , Eddie James , Stephen Boyd , Michael Turquette , Mauro Carvalho Chehab , Hans Verkuil Cc: linux-clk@vger.kernel.org, linux-media@vger.kernel.org, openbmc@lists.ozlabs.org, linux-aspeed@lists.ozlabs.org, Jae Hyun Yoo Subject: [PATCH 1/2] clk: ast2600: fix reset settings for eclk and vclk Date: Mon, 7 Dec 2020 08:42:39 -0800 Message-Id: <20201207164240.15436-2-jae.hyun.yoo@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201207164240.15436-1-jae.hyun.yoo@linux.intel.com> References: <20201207164240.15436-1-jae.hyun.yoo@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Video engine reset setting should be coupled with eclk to match it with the setting for previous Aspeed SoCs which is defined in clk-aspeed.c since all Aspeed SoCs are sharing a single video engine driver. Also, reset bit 6 is defined as 'Video Engine' reset in datasheet so it should be de-asserted when eclk is enabled. This commit fixes the setting. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley --- drivers/clk/clk-ast2600.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index 177368cac6dd..882da16575d4 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -60,10 +60,10 @@ static void __iomem *scu_g6_base; static const struct aspeed_gate_data aspeed_g6_gates[] = { /* clk rst name parent flags */ [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ - [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ + [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */ [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ /* vclk parent - dclk/d1clk/hclk/mclk */ - [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ + [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */ [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ /* From dpll */ [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ From patchwork Mon Dec 7 16:42:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jae Hyun Yoo X-Patchwork-Id: 11956387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51AE3C3526E for ; Mon, 7 Dec 2020 16:35:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3679D238E5 for ; Mon, 7 Dec 2020 16:35:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727798AbgLGQer (ORCPT ); Mon, 7 Dec 2020 11:34:47 -0500 Received: from mga12.intel.com ([192.55.52.136]:51470 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727417AbgLGQeq (ORCPT ); Mon, 7 Dec 2020 11:34:46 -0500 IronPort-SDR: 6tm9sXeUHgtzd9B46a/chN+EcVDFoIXjjdMlK2cMOXPMM7eU0ljkE6Hjjwwlzmv6MKdFDDfGiY Qnl8UB0o0xEA== X-IronPort-AV: E=McAfee;i="6000,8403,9827"; a="152970149" X-IronPort-AV: E=Sophos;i="5.78,400,1599548400"; d="scan'208";a="152970149" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2020 08:33:00 -0800 IronPort-SDR: WlQxwyB0V1M4V9527ULq+RvgRgQS09YAl43Vzzkj6FL61An2RmNcjDfqJCsjw3KJnXK0qrs5MW vWCLkKGF53Hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,400,1599548400"; d="scan'208";a="317246242" Received: from maru.jf.intel.com ([10.54.51.77]) by fmsmga008.fm.intel.com with ESMTP; 07 Dec 2020 08:33:00 -0800 From: Jae Hyun Yoo To: Joel Stanley , Andrew Jeffery , Eddie James , Stephen Boyd , Michael Turquette , Mauro Carvalho Chehab , Hans Verkuil Cc: linux-clk@vger.kernel.org, linux-media@vger.kernel.org, openbmc@lists.ozlabs.org, linux-aspeed@lists.ozlabs.org, Jae Hyun Yoo Subject: [PATCH 2/2] media: aspeed: fix clock handling logic Date: Mon, 7 Dec 2020 08:42:40 -0800 Message-Id: <20201207164240.15436-3-jae.hyun.yoo@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201207164240.15436-1-jae.hyun.yoo@linux.intel.com> References: <20201207164240.15436-1-jae.hyun.yoo@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Video engine uses eclk and vclk for its clock sources and its reset control is coupled with eclk so the current clock enabling sequence works like below. Enable eclk De-assert Video Engine reset 10ms delay Enable vclk It introduces improper reset on the Video Engine hardware and eventually the hardware generates unexpected DMA memory transfers that can corrupt memory region in random and sporadic patterns. This issue is observed very rarely on some specific AST2500 SoCs but it causes a critical kernel panic with making a various shape of signature so it's extremely hard to debug. Moreover, the issue is observed even when the video engine is not actively used because udevd turns on the video engine hardware for a short time to make a query in every boot. To fix this issue, this commit changes the clock handling logic to make the reset de-assertion triggered after enabling both eclk and vclk. Also, it adds clk_unprepare call for a case when probe fails. Fixes: d2b4387f3bdf ("media: platform: Add Aspeed Video Engine driver") Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Eddie James --- drivers/media/platform/aspeed-video.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c index c46a79eace98..db072ff2df70 100644 --- a/drivers/media/platform/aspeed-video.c +++ b/drivers/media/platform/aspeed-video.c @@ -514,8 +514,8 @@ static void aspeed_video_off(struct aspeed_video *video) aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); /* Turn off the relevant clocks */ - clk_disable(video->vclk); clk_disable(video->eclk); + clk_disable(video->vclk); clear_bit(VIDEO_CLOCKS_ON, &video->flags); } @@ -526,8 +526,8 @@ static void aspeed_video_on(struct aspeed_video *video) return; /* Turn on the relevant clocks */ - clk_enable(video->eclk); clk_enable(video->vclk); + clk_enable(video->eclk); set_bit(VIDEO_CLOCKS_ON, &video->flags); } @@ -1719,8 +1719,11 @@ static int aspeed_video_probe(struct platform_device *pdev) return rc; rc = aspeed_video_setup_video(video); - if (rc) + if (rc) { + clk_unprepare(video->vclk); + clk_unprepare(video->eclk); return rc; + } return 0; }