From patchwork Tue Dec 8 12:28:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95ED1C4361B for ; Tue, 8 Dec 2020 12:31:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C05523ABA for ; Tue, 8 Dec 2020 12:31:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728868AbgLHMbm (ORCPT ); Tue, 8 Dec 2020 07:31:42 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44956 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728773AbgLHMbm (ORCPT ); Tue, 8 Dec 2020 07:31:42 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTigB066606; Tue, 8 Dec 2020 06:29:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430584; bh=yUn5N7xuRZ7wh1GGz0Cy7uuTOcliNJXdPx5b/4Ti4II=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hpRrSaZLkr2mNJErroeGJuq9452GH8euaMHP9z5ajv1Osnuse6Me5nfhwqRXEWuG6 2cqO50Uhu2zrEkv817nhlGmbs90FuwFCnYETNRBuALA3SEVmOECI+2Gp12nhnqkb6N idz2mIrtEI2j+KDYe0fXXbtGgTTzxGjBRLnZuLQI= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTiKh086297 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:44 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:43 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:43 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjF095068; Tue, 8 Dec 2020 06:29:41 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 01/29] drm/panel: panel-dsi-cm: cleanup tear enable Date: Tue, 8 Dec 2020 14:28:27 +0200 Message-ID: <20201208122855.254819-2-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Simplify the code by moving code from _dsicm_enable_te() into dsicm_power_on(). Signed-off-by: Tomi Valkeinen Reviewed-by: Sam Ravnborg Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/panel/panel-dsi-cm.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-dsi-cm.c b/drivers/gpu/drm/panel/panel-dsi-cm.c index 729b42b4dabd..38f79dca1fd0 100644 --- a/drivers/gpu/drm/panel/panel-dsi-cm.c +++ b/drivers/gpu/drm/panel/panel-dsi-cm.c @@ -68,8 +68,6 @@ static inline struct panel_drv_data *panel_to_ddata(struct drm_panel *panel) return container_of(panel, struct panel_drv_data, panel); } -static int _dsicm_enable_te(struct panel_drv_data *ddata, bool enable); - static void dsicm_bl_power(struct panel_drv_data *ddata, bool enable) { struct backlight_device *backlight; @@ -313,10 +311,13 @@ static int dsicm_power_on(struct panel_drv_data *ddata) if (r) goto err; - r = _dsicm_enable_te(ddata, true); + r = mipi_dsi_dcs_set_tear_on(ddata->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); if (r) goto err; + /* possible panel bug */ + msleep(100); + ddata->enabled = true; if (!ddata->intro_printed) { @@ -417,22 +418,6 @@ static int dsicm_disable(struct drm_panel *panel) return r; } -static int _dsicm_enable_te(struct panel_drv_data *ddata, bool enable) -{ - struct mipi_dsi_device *dsi = ddata->dsi; - int r; - - if (enable) - r = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - else - r = mipi_dsi_dcs_set_tear_off(dsi); - - /* possible panel bug */ - msleep(100); - - return r; -} - static int dsicm_get_modes(struct drm_panel *panel, struct drm_connector *connector) { From patchwork Tue Dec 8 12:28:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0546C433FE for ; Tue, 8 Dec 2020 12:30:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADFB123AA7 for ; Tue, 8 Dec 2020 12:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727463AbgLHMa6 (ORCPT ); Tue, 8 Dec 2020 07:30:58 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44994 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727992AbgLHMa6 (ORCPT ); Tue, 8 Dec 2020 07:30:58 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTkT8066616; Tue, 8 Dec 2020 06:29:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430586; bh=wbXNMafqm+H4Ot7y4k9lHFPPoLIUKb4M6mQEddffijU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ak7mdCelO5e6xV9bPWmkvz8TkAV4/P1H3cAFrYMLrT+YHwHNccKpdgCz1R81Mm80X BNkNFU4iw/eP96lu8pwHfEYl2lVwNqZ0caDdCR6tUI+7LCs6Op704fAEwzOgh9mTYA kWHucRc1uRs6cK9wP3UEFImL+0XF1FiPDLkYs3XI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTkWK086314 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:46 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:46 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:46 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjG095068; Tue, 8 Dec 2020 06:29:44 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 02/29] ARM: dts: omap5: add address-cells & size-cells to dsi Date: Tue, 8 Dec 2020 14:28:28 +0200 Message-ID: <20201208122855.254819-3-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add address-cells & size-cells to DSI nodes so that board files do not need to define them. Signed-off-by: Tomi Valkeinen Cc: Tony Lindgren Acked-by: Tony Lindgren Reviewed-by: Sebastian Reichel --- arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2bf2e5839a7f..e6f6947965ef 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -517,6 +517,9 @@ dsi1: encoder@0 { clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; @@ -549,6 +552,9 @@ dsi2: encoder@0 { clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; From patchwork Tue Dec 8 12:28:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39073C4361B for ; Tue, 8 Dec 2020 12:30:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E453F23A9D for ; Tue, 8 Dec 2020 12:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728192AbgLHMa5 (ORCPT ); Tue, 8 Dec 2020 07:30:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33282 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727463AbgLHMa5 (ORCPT ); Tue, 8 Dec 2020 07:30:57 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTnfi064008; Tue, 8 Dec 2020 06:29:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430589; bh=s1EWE/SXUVeER6hkk0HRG9tRuUdyEyQIlfDmCa0tmQM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zWrShTYuAjhM8Vy/qqK0zmAqP7YKOCmAzzr6MU/v4JIP7cUb5gpy07kdNLfh2f+e2 VHt2+wg0VUdek0GNSAG5BA+AnKvf0uG5Qbk7x+Pv6a8l6R/aUozcL76HvGblZiq2pp lLUuSCQtdz8kMoNVfOROWFbwZBpQKH2nvx9C09aA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTn9X103274 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:49 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:48 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:48 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjH095068; Tue, 8 Dec 2020 06:29:46 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 03/29] drm/omap: pll: fix iteration loop check Date: Tue, 8 Dec 2020 14:28:29 +0200 Message-ID: <20201208122855.254819-4-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org If the PLL calc function is given bad parameters, n_start/m_start may be higher than n_stop/m_stop, which leads to the loops iterating through the whole u32 number space. Fix this by failing early on such cases. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/pll.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c index 1212f3cc52d1..12926218c436 100644 --- a/drivers/gpu/drm/omapdrm/dss/pll.c +++ b/drivers/gpu/drm/omapdrm/dss/pll.c @@ -222,6 +222,9 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); n_inc = 1; + if (n_start > n_stop) + return false; + if (hw->errata_i886) { swap(n_start, n_stop); n_inc = -1; @@ -239,6 +242,9 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, hw->m_max); m_inc = 1; + if (m_start > m_stop) + continue; + if (hw->errata_i886) { swap(m_start, m_stop); m_inc = -1; From patchwork Tue Dec 8 12:28:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A5D6C4361B for ; Tue, 8 Dec 2020 12:31:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E7C923AC2 for ; Tue, 8 Dec 2020 12:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727998AbgLHMbl (ORCPT ); Tue, 8 Dec 2020 07:31:41 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33220 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728773AbgLHMbl (ORCPT ); Tue, 8 Dec 2020 07:31:41 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTpoQ064018; Tue, 8 Dec 2020 06:29:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430591; bh=A2yh5uoIc5rpq5mohJlKCQRU71EKsWsAa9cuN6BcACw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pbQDHckAcpPOIPpP/odtmfPsKIMhM+jDIFaaAa9pj5z+Jje0DvsLp4Zev11TjOO12 vNDJlZXU47ruyKsFkdXmnyD7TMlKOTsIgYKZEAZfjuTLv8BrVU55+4YMAkk5CASY6/ HDq5fcdGbfWpLeUIJQGwDT0GOmyHpWSrmkel1yHc= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTp6T103300 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:51 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:51 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:51 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjI095068; Tue, 8 Dec 2020 06:29:49 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 04/29] drm/omap: dsi: set trans_mode according to client mode_flags Date: Tue, 8 Dec 2020 14:28:30 +0200 Message-ID: <20201208122855.254819-5-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The DSI host driver currently ignores the video mode flags in client->mode_flags. Add the code to take the transfer mode from client's mode_flags. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index c3592c6db977..7fee9cf8782d 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -5140,6 +5140,13 @@ static int omap_dsi_host_attach(struct mipi_dsi_host *host, dsi->config.lp_clk_min = 7000000; // TODO: get from client? dsi->config.lp_clk_max = client->lp_rate; + if (client->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + dsi->config.trans_mode = OMAP_DSS_DSI_BURST_MODE; + else if (client->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + dsi->config.trans_mode = OMAP_DSS_DSI_PULSE_MODE; + else + dsi->config.trans_mode = OMAP_DSS_DSI_EVENT_MODE; + dsi->ulps_auto_idle = false; return 0; From patchwork Tue Dec 8 12:28:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E18FC4361B for ; Tue, 8 Dec 2020 12:31:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0BF9723AA7 for ; Tue, 8 Dec 2020 12:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728495AbgLHMa7 (ORCPT ); Tue, 8 Dec 2020 07:30:59 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33404 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727992AbgLHMa7 (ORCPT ); Tue, 8 Dec 2020 07:30:59 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTsRQ064024; Tue, 8 Dec 2020 06:29:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430594; bh=JpHA/w1FiegOmLYTvyhahyGj8gRh7jLTeSQfmEeloCI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JNezfKgmxr6xNeSNkJG5a7lzqq7eWzJR9KbGIaZ0bHeMujU6kIkq01JuSoCvKOOmS eByFph3s/eT8uP4ENhfEJXr7OVijLdPbZM3jSf+TC50n2kVU0ebk7Zbbkha2AdMuIo bMGm2rUJh3zR30KYevjTFbtaPg0NJ2F56Ga+vm5M= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTsUM103314 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:54 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:54 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:53 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjJ095068; Tue, 8 Dec 2020 06:29:51 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 05/29] drm/panel: panel-dsi-cm: set column & page at setup Date: Tue, 8 Dec 2020 14:28:31 +0200 Message-ID: <20201208122855.254819-6-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Set the column & page address once during setup, instead of relying the DSI host driver to set those. Signed-off-by: Tomi Valkeinen Reviewed-by: Sam Ravnborg Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/panel/panel-dsi-cm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-dsi-cm.c b/drivers/gpu/drm/panel/panel-dsi-cm.c index 38f79dca1fd0..556f9a2c5c0c 100644 --- a/drivers/gpu/drm/panel/panel-dsi-cm.c +++ b/drivers/gpu/drm/panel/panel-dsi-cm.c @@ -170,6 +170,22 @@ static int dsicm_get_id(struct panel_drv_data *ddata, u8 *id1, u8 *id2, u8 *id3) return 0; } +static int dsicm_set_update_window(struct panel_drv_data *ddata) +{ + struct mipi_dsi_device *dsi = ddata->dsi; + int r; + + r = mipi_dsi_dcs_set_column_address(dsi, 0, ddata->mode.hdisplay - 1); + if (r < 0) + return r; + + r = mipi_dsi_dcs_set_page_address(dsi, 0, ddata->mode.vdisplay - 1); + if (r < 0) + return r; + + return 0; +} + static int dsicm_bl_update_status(struct backlight_device *dev) { struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev); @@ -307,6 +323,10 @@ static int dsicm_power_on(struct panel_drv_data *ddata) if (r) goto err; + r = dsicm_set_update_window(ddata); + if (r) + goto err; + r = mipi_dsi_dcs_set_display_on(ddata->dsi); if (r) goto err; From patchwork Tue Dec 8 12:28:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AB1FC4167B for ; Tue, 8 Dec 2020 12:31:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36AA923AC0 for ; Tue, 8 Dec 2020 12:31:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726278AbgLHMbB (ORCPT ); Tue, 8 Dec 2020 07:31:01 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45170 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727992AbgLHMbB (ORCPT ); Tue, 8 Dec 2020 07:31:01 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTvvD066640; Tue, 8 Dec 2020 06:29:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430597; bh=XD/sefueOKoXyqgCh9BxBBpoHqtt4qwCxN2yjeUoZK4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RnZgNyPinWYkfuZjDZMZm8tgYth+cDBHPr7zePICNhiuUfeNe4F+NW17D9jlQ5WTR sdOGbpWAOOgPFIUptiO5rjGsZ4+rTCEo9XGV3yI9XS9Zr27murYwRHHqcuuttWfxGh K9k07GZYyAJR82vK7baJyA5FDeDL/TixkVo96clA= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTue4086386 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:57 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:56 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:56 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjK095068; Tue, 8 Dec 2020 06:29:54 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 06/29] drm/omap: dsi: send nop instead of page & column Date: Tue, 8 Dec 2020 14:28:32 +0200 Message-ID: <20201208122855.254819-7-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The OMAP DSI command mode panel driver used to send page & column address before each frame update, and this code was moved into the DSI host driver when converting it to the DRM bridge model. However, it's not really required to send the page & column address before each frame. It's also something that doesn't really belong to the DSI host driver, so we should drop the code. That said, frame updates break if we don't send _something_ between the frames. A NOP command does the trick. It is not clear if this behavior is as expected from a DSI command mode frame transfer, or is it a feature/issue with OMAP DSI driver, or a feature/issue in the command mode panel used. Most likely this is related to the following from the DSI spec: "To enable PHY synchronization the host processor should periodically end HS transmission and drive the Data Lanes to the LP state. This transition should take place at least once per frame." Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 46 ++++++++++++------------------- 1 file changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 7fee9cf8782d..c6e044f8bece 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -3884,35 +3884,19 @@ static int _dsi_update(struct dsi_data *dsi) return 0; } -static int _dsi_update_window(struct dsi_data *dsi, int channel, - int x, int y, int w, int h) -{ - int x1 = x, x2 = (x + w - 1); - int y1 = y, y2 = (y + h - 1); - u8 payloadX[5] = { MIPI_DCS_SET_COLUMN_ADDRESS, - x1 >> 8, x1 & 0xff, x2 >> 8, x2 & 0xff }; - u8 payloadY[5] = { MIPI_DCS_SET_PAGE_ADDRESS, - y1 >> 8, y1 & 0xff, y2 >> 8, y2 & 0xff }; - struct mipi_dsi_msg msgX = { 0 }, msgY = { 0 }; - int ret; +static int _dsi_send_nop(struct dsi_data *dsi, int channel) +{ + const u8 payload[] = { MIPI_DCS_NOP }; + const struct mipi_dsi_msg msg = { + .channel = channel, + .type = MIPI_DSI_DCS_SHORT_WRITE, + .tx_len = 1, + .tx_buf = payload, + }; WARN_ON(!dsi_bus_is_locked(dsi)); - msgX.type = MIPI_DSI_DCS_LONG_WRITE; - msgX.channel = channel; - msgX.tx_buf = payloadX; - msgX.tx_len = sizeof(payloadX); - - msgY.type = MIPI_DSI_DCS_LONG_WRITE; - msgY.channel = channel; - msgY.tx_buf = payloadY; - msgY.tx_len = sizeof(payloadY); - - ret = _omap_dsi_host_transfer(dsi, &msgX); - if (ret != 0) - return ret; - - return _omap_dsi_host_transfer(dsi, &msgY); + return _omap_dsi_host_transfer(dsi, &msg); } static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) @@ -3944,10 +3928,14 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) dsi_set_ulps_auto(dsi, false); - r = _dsi_update_window(dsi, channel, 0, 0, dsi->vm.hactive, - dsi->vm.vactive); + /* + * Send NOP between the frames. If we don't send something here, the + * updates stop working. This is probably related to DSI spec stating + * that the DSI host should transition to LP at least once per frame. + */ + r = _dsi_send_nop(dsi, channel); if (r < 0) { - DSSWARN("window update error: %d\n", r); + DSSWARN("failed to send nop between frames: %d\n", r); goto err; } From patchwork Tue Dec 8 12:28:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0F55C433FE for ; Tue, 8 Dec 2020 12:31:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BFCDC23ABA for ; Tue, 8 Dec 2020 12:31:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728893AbgLHMbs (ORCPT ); Tue, 8 Dec 2020 07:31:48 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33526 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727798AbgLHMbs (ORCPT ); Tue, 8 Dec 2020 07:31:48 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTxUX064051; Tue, 8 Dec 2020 06:29:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430599; bh=l7cm1XwrM/F/UqJofWy5I/fNSYSt1m1cM8ZbnQnJm90=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=C6HSMmyJ6LT9LXKI4DGCkhg/BYXgVhUjzySPoNVPiWahs3+QOY73EoJfliwvctJt6 BJfOrpzW80+fznsnD9P3uQtFEkRuZZ2BS0H3PZdIOAunqaXDd9ADiL9ocOl8VNukc3 Ffn4ZTiiplnQi0bN5XH82AkiRpDhtObu9wNJvuP4= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CTx8D037277 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:29:59 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:29:58 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:29:59 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjL095068; Tue, 8 Dec 2020 06:29:56 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 07/29] drm/omap: dsi: simplify VC handling Date: Tue, 8 Dec 2020 14:28:33 +0200 Message-ID: <20201208122855.254819-8-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The VC handling has gotten quite tangled up. As the first step to clean it up, lets define that we only support a single DSI peripheral (which was really already the case), and we always use VC0 (define VC_DEFAULT 0) register block to send data to the peripheral. We can thus have a single mipi_dsi_device pointer and remove the for-loops which made passes over all the four VCs (just the first one was ever used). Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 49 ++++++++----------------------- 1 file changed, 13 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index c6e044f8bece..5e13478010db 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -360,9 +360,10 @@ struct dsi_data { bool vdds_dsi_enabled; struct regulator *vdds_dsi_reg; + struct mipi_dsi_device *dsidev; + struct { enum dsi_vc_source source; - struct mipi_dsi_device *dest; enum fifo_size tx_fifo_size; enum fifo_size rx_fifo_size; } vc[4]; @@ -452,6 +453,8 @@ static bool dsi_perf; module_param(dsi_perf, bool, 0644); #endif +#define VC_DEFAULT 0 + #define drm_bridge_to_dsi(bridge) \ container_of(bridge, struct dsi_data, bridge) @@ -3716,16 +3719,11 @@ static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel static void dsi_disable_video_outputs(struct omap_dss_device *dssdev) { struct dsi_data *dsi = to_dsi_data(dssdev); - unsigned int i; dsi_bus_lock(dsi); dsi->video_enabled = false; - for (i = 0; i < 4; i++) { - if (!dsi->vc[i].dest) - continue; - dsi_disable_video_output(dssdev, i); - } + dsi_disable_video_output(dssdev, VC_DEFAULT); dsi_display_disable(dssdev); @@ -3914,11 +3912,6 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) goto err; } - if (!dsi->vc[channel].dest) { - r = -ENODEV; - goto err; - } - if (dsi->vm.hactive == 0 || dsi->vm.vactive == 0) { r = -EINVAL; goto err; @@ -3959,16 +3952,7 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) static int dsi_update_all(struct omap_dss_device *dssdev) { - unsigned int i; - int r; - - for (i = 0; i < 4; i++) { - r = dsi_update_channel(dssdev, i); - if (r && r != -ENODEV) - return r; - } - - return r; + return dsi_update_channel(dssdev, VC_DEFAULT); } /* Display funcs */ @@ -4196,17 +4180,12 @@ static void dsi_display_enable(struct omap_dss_device *dssdev) static void dsi_enable_video_outputs(struct omap_dss_device *dssdev) { struct dsi_data *dsi = to_dsi_data(dssdev); - unsigned int i; dsi_bus_lock(dsi); dsi_display_enable(dssdev); - for (i = 0; i < 4; i++) { - if (!dsi->vc[i].dest) - continue; - dsi_enable_video_output(dssdev, i); - } + dsi_enable_video_output(dssdev, VC_DEFAULT); dsi->video_enabled = true; @@ -5095,8 +5074,8 @@ static int omap_dsi_host_attach(struct mipi_dsi_host *host, if (channel > 3) return -EINVAL; - if (dsi->vc[channel].dest) { - DSSERR("cannot get VC for display %s", dev_name(&client->dev)); + if (dsi->dsidev) { + DSSERR("dsi client already attached\n"); return -EBUSY; } @@ -5117,7 +5096,7 @@ static int omap_dsi_host_attach(struct mipi_dsi_host *host, dsi->mode = OMAP_DSS_DSI_CMD_MODE; } - dsi->vc[channel].dest = client; + dsi->dsidev = client; dsi->pix_fmt = client->format; INIT_DEFERRABLE_WORK(&dsi->ulps_work, @@ -5149,11 +5128,11 @@ static int omap_dsi_host_detach(struct mipi_dsi_host *host, if (channel > 3) return -EINVAL; - if (dsi->vc[channel].dest != client) + if (WARN_ON(dsi->dsidev != client)) return -EINVAL; omap_dsi_unregister_te_irq(dsi); - dsi->vc[channel].dest = NULL; + dsi->dsidev = NULL; return 0; } @@ -5685,10 +5664,8 @@ static int dsi_probe(struct platform_device *pdev) } /* DSI VCs initialization */ - for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { + for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) dsi->vc[i].source = DSI_VC_SOURCE_L4; - dsi->vc[i].dest = NULL; - } r = dsi_get_clocks(dsi); if (r) From patchwork Tue Dec 8 12:28:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C400C4361B for ; Tue, 8 Dec 2020 12:31:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6E1123ABA for ; Tue, 8 Dec 2020 12:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727452AbgLHMbt (ORCPT ); Tue, 8 Dec 2020 07:31:49 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33536 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727798AbgLHMbt (ORCPT ); Tue, 8 Dec 2020 07:31:49 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CU2uF064098; Tue, 8 Dec 2020 06:30:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430602; bh=wdap3DjOYmxXlAFEu1U0+KG+ezB+xoP2+U85DXN3G/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v5/QsdC18suXRt6+2v9Q13abdLEhX+zg/udCx/oTG+uxu5v+0/SAgdbbTMblkocfg kX1ayjfOr4SgXy6TqegRAWQfeEwNZcamv7zokU4ekQEy8jV6MdD2HetjczzLsnZLGP tjUVE3Oua9UOA5qOo6lpxG6yA/Ca2/++aSz/UPCg= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CU1bS086526 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:02 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:01 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:01 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjM095068; Tue, 8 Dec 2020 06:29:59 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 08/29] drm/omap: dsi: drop useless channel checks Date: Tue, 8 Dec 2020 14:28:34 +0200 Message-ID: <20201208122855.254819-9-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org A DSI peripheral can have virtual channel ID of 0-3. This should be always the case, and there's no need in the driver to validate the channel. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 5e13478010db..c78ae99c8742 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -3902,9 +3902,6 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) struct dsi_data *dsi = to_dsi_data(dssdev); int r; - if (channel > 3) - return -EINVAL; - dsi_bus_lock(dsi); if (!dsi->video_enabled) { @@ -5068,12 +5065,8 @@ static int omap_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *client) { struct dsi_data *dsi = host_to_omap(host); - unsigned int channel = client->channel; int r; - if (channel > 3) - return -EINVAL; - if (dsi->dsidev) { DSSERR("dsi client already attached\n"); return -EBUSY; @@ -5123,10 +5116,6 @@ static int omap_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *client) { struct dsi_data *dsi = host_to_omap(host); - unsigned int channel = client->channel; - - if (channel > 3) - return -EINVAL; if (WARN_ON(dsi->dsidev != client)) return -EINVAL; From patchwork Tue Dec 8 12:28:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E94ADC433FE for ; Tue, 8 Dec 2020 12:31:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BEEDD23ABA for ; Tue, 8 Dec 2020 12:31:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727798AbgLHMbv (ORCPT ); Tue, 8 Dec 2020 07:31:51 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45236 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726138AbgLHMbv (ORCPT ); Tue, 8 Dec 2020 07:31:51 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CU5sK066729; Tue, 8 Dec 2020 06:30:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430605; bh=0Q2Dczc2K7+6NpQJz8vc9eUj7Sb0lPEvV6qfEomzRro=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=e2+peX3IW24lVdJEHDP2ARPp0mrM7tS11OsFHBITmQq2iLDCXpG02Y4yxtMuAvi6j pjORcs589uINr4T6I0VBGhhjQ4QQsuwER9vC9eY3bsX6wHYIAir/S4SSX+jqWs69zq pDMm3rVKSmr/mjY9GiR4jiTn6E8Abr9NoNerD9Xg= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CU47W104333 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:04 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:04 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:04 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjN095068; Tue, 8 Dec 2020 06:30:02 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 09/29] drm/omap: dsi: cleanup dispc channel usage Date: Tue, 8 Dec 2020 14:28:35 +0200 Message-ID: <20201208122855.254819-10-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The "channel" usage in omap dsi driver is confusing. As the first step, change "channel" to "dispc_channel" when dealing with the dispc channel. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index c78ae99c8742..cf0dc4872d14 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -3978,10 +3978,10 @@ static int dsi_configure_dispc_clocks(struct dsi_data *dsi) static int dsi_display_init_dispc(struct dsi_data *dsi) { - enum omap_channel channel = dsi->output.dispc_channel; + enum omap_channel dispc_channel = dsi->output.dispc_channel; int r; - dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ? + dss_select_lcd_clk_source(dsi->dss, dispc_channel, dsi->module_id == 0 ? DSS_CLK_SRC_PLL1_1 : DSS_CLK_SRC_PLL2_1); @@ -4017,19 +4017,19 @@ static int dsi_display_init_dispc(struct dsi_data *dsi) dss_mgr_unregister_framedone_handler(&dsi->output, dsi_framedone_irq_callback, dsi); err: - dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); + dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); return r; } static void dsi_display_uninit_dispc(struct dsi_data *dsi) { - enum omap_channel channel = dsi->output.dispc_channel; + enum omap_channel dispc_channel = dsi->output.dispc_channel; if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) dss_mgr_unregister_framedone_handler(&dsi->output, dsi_framedone_irq_callback, dsi); - dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); + dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); } static int dsi_configure_dsi_clocks(struct dsi_data *dsi) @@ -4846,12 +4846,12 @@ static int dsi_set_config(struct omap_dss_device *dssdev, } /* - * Return a hardcoded channel for the DSI output. This should work for + * Return a hardcoded dispc channel for the DSI output. This should work for * current use cases, but this can be later expanded to either resolve * the channel in some more dynamic manner, or get the channel as a user * parameter. */ -static enum omap_channel dsi_get_channel(struct dsi_data *dsi) +static enum omap_channel dsi_get_dispc_channel(struct dsi_data *dsi) { switch (dsi->data->model) { case DSI_MODEL_OMAP3: @@ -5403,7 +5403,7 @@ static int dsi_init_output(struct dsi_data *dsi) out->type = OMAP_DISPLAY_TYPE_DSI; out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; - out->dispc_channel = dsi_get_channel(dsi); + out->dispc_channel = dsi_get_dispc_channel(dsi); out->dsi_ops = &dsi_ops; out->of_port = 0; out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE From patchwork Tue Dec 8 12:28:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAA22C4361B for ; Tue, 8 Dec 2020 12:31:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B5F3323AAA for ; Tue, 8 Dec 2020 12:31:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728894AbgLHMbx (ORCPT ); Tue, 8 Dec 2020 07:31:53 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45246 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726138AbgLHMbx (ORCPT ); Tue, 8 Dec 2020 07:31:53 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CU8aF066882; Tue, 8 Dec 2020 06:30:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430608; bh=MnToD2DG0K+OpBqGtUIr/d0MqVLRirI1Mmr75ceUdSs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=POSY42cCQPzKkRdJobwBTEyhwP1rwi5JwrbJ7yiFkt4lgvWvoa+GgsQay5CANXtl7 Jq/qN2Qy/5HZSa8dmwlgCINzmUR11FRDvsHrCGeHNoDP9NQmV/8eRlmRYgrZ+THcxV +QNRSZdEvey+SZZ2b3yrqAIEycvp/cMcOsD4O3j8= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CU7CV087439 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:07 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:07 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:06 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjO095068; Tue, 8 Dec 2020 06:30:04 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 10/29] drm/omap: dsi: rename 'channel' to 'vc' Date: Tue, 8 Dec 2020 14:28:36 +0200 Message-ID: <20201208122855.254819-11-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The "channel" usage in omap dsi driver is confusing. We have three different "channels": 1) DSI virtual channel ID. This is a number from 0 to 3, included in the packet payload. 2) VC. This is a register block in the DSI IP. There are four of those blocks. A VC is a DSI "pipeline", with defined fifo settings, data source (cpu or dispc), and some other settings. It has no relation to the 1). 3) dispc channel. It's the "pipeline" number dispc uses to send pixel data. The previous patch handled the third case. To start fixing 1) and 2), we first rename all uses of 'channel' to 'vc', as in most of the cases that is the correct thing to use. However, in some places 1) and 2) have gotten mixed up (i.e. the code uses msg->channel when it should use vc), which will be fixed in the following patch. Note that mixing 1) and 2) currently is "fine", as at the moment we only support DSI peripherals with DSI virtual channel 0, and we always use VC0 to send data. So both 1) and 2) are always 0. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 220 +++++++++++++++--------------- 1 file changed, 110 insertions(+), 110 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index cf0dc4872d14..273159e8f992 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -214,7 +214,7 @@ static void dsi_set_ulps_auto(struct dsi_data *dsi, bool enable); static int dsi_display_init_dispc(struct dsi_data *dsi); static void dsi_display_uninit_dispc(struct dsi_data *dsi); -static int dsi_vc_send_null(struct dsi_data *dsi, int channel); +static int dsi_vc_send_null(struct dsi_data *dsi, int vc); static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, const struct mipi_dsi_msg *msg); @@ -376,7 +376,7 @@ struct dsi_data { /* space for a copy used by the interrupt handler */ struct dsi_isr_tables isr_tables_copy; - int update_channel; + int update_vc; #ifdef DSI_PERF_MEASURE unsigned int update_bytes; #endif @@ -639,7 +639,7 @@ static void print_irq_status(u32 status) #undef PIS } -static void print_irq_status_vc(int channel, u32 status) +static void print_irq_status_vc(int vc, u32 status) { if (status == 0) return; @@ -650,7 +650,7 @@ static void print_irq_status_vc(int channel, u32 status) #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", - channel, + vc, status, PIS(CS), PIS(ECC_CORR), @@ -1031,7 +1031,7 @@ static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, return r; } -static int dsi_register_isr_vc(struct dsi_data *dsi, int channel, +static int dsi_register_isr_vc(struct dsi_data *dsi, int vc, omap_dsi_isr_t isr, void *arg, u32 mask) { unsigned long flags; @@ -1040,18 +1040,18 @@ static int dsi_register_isr_vc(struct dsi_data *dsi, int channel, spin_lock_irqsave(&dsi->irq_lock, flags); r = _dsi_register_isr(isr, arg, mask, - dsi->isr_tables.isr_table_vc[channel], - ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); + dsi->isr_tables.isr_table_vc[vc], + ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); if (r == 0) - _omap_dsi_set_irqs_vc(dsi, channel); + _omap_dsi_set_irqs_vc(dsi, vc); spin_unlock_irqrestore(&dsi->irq_lock, flags); return r; } -static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel, +static int dsi_unregister_isr_vc(struct dsi_data *dsi, int vc, omap_dsi_isr_t isr, void *arg, u32 mask) { unsigned long flags; @@ -1060,11 +1060,11 @@ static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel, spin_lock_irqsave(&dsi->irq_lock, flags); r = _dsi_unregister_isr(isr, arg, mask, - dsi->isr_tables.isr_table_vc[channel], - ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); + dsi->isr_tables.isr_table_vc[vc], + ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); if (r == 0) - _omap_dsi_set_irqs_vc(dsi, channel); + _omap_dsi_set_irqs_vc(dsi, vc); spin_unlock_irqrestore(&dsi->irq_lock, flags); @@ -2232,9 +2232,9 @@ static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi) return 0; } -static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel) +static bool dsi_vc_is_enabled(struct dsi_data *dsi, int vc) { - return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0); + return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0); } static void dsi_packet_sent_handler_vp(void *data, u32 mask) @@ -2242,14 +2242,14 @@ static void dsi_packet_sent_handler_vp(void *data, u32 mask) struct dsi_packet_sent_handler_data *vp_data = (struct dsi_packet_sent_handler_data *) data; struct dsi_data *dsi = vp_data->dsi; - const int channel = dsi->update_channel; + const int vc = dsi->update_vc; u8 bit = dsi->te_enabled ? 30 : 31; - if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0) + if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0) complete(vp_data->completion); } -static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel) +static int dsi_sync_vc_vp(struct dsi_data *dsi, int vc) { DECLARE_COMPLETION_ONSTACK(completion); struct dsi_packet_sent_handler_data vp_data = { @@ -2261,13 +2261,13 @@ static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel) bit = dsi->te_enabled ? 30 : 31; - r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, + r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, &vp_data, DSI_VC_IRQ_PACKET_SENT); if (r) goto err0; /* Wait for completion only if TE_EN/TE_START is still set */ - if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) { + if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) { if (wait_for_completion_timeout(&completion, msecs_to_jiffies(10)) == 0) { DSSERR("Failed to complete previous frame transfer\n"); @@ -2276,12 +2276,12 @@ static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel) } } - dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, + dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, &vp_data, DSI_VC_IRQ_PACKET_SENT); return 0; err1: - dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, + dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, &vp_data, DSI_VC_IRQ_PACKET_SENT); err0: return r; @@ -2292,13 +2292,13 @@ static void dsi_packet_sent_handler_l4(void *data, u32 mask) struct dsi_packet_sent_handler_data *l4_data = (struct dsi_packet_sent_handler_data *) data; struct dsi_data *dsi = l4_data->dsi; - const int channel = dsi->update_channel; + const int vc = dsi->update_vc; - if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0) + if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0) complete(l4_data->completion); } -static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel) +static int dsi_sync_vc_l4(struct dsi_data *dsi, int vc) { DECLARE_COMPLETION_ONSTACK(completion); struct dsi_packet_sent_handler_data l4_data = { @@ -2307,13 +2307,13 @@ static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel) }; int r = 0; - r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, + r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, &l4_data, DSI_VC_IRQ_PACKET_SENT); if (r) goto err0; /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ - if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) { + if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) { if (wait_for_completion_timeout(&completion, msecs_to_jiffies(10)) == 0) { DSSERR("Failed to complete previous l4 transfer\n"); @@ -2322,47 +2322,47 @@ static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel) } } - dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, + dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, &l4_data, DSI_VC_IRQ_PACKET_SENT); return 0; err1: - dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, + dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, &l4_data, DSI_VC_IRQ_PACKET_SENT); err0: return r; } -static int dsi_sync_vc(struct dsi_data *dsi, int channel) +static int dsi_sync_vc(struct dsi_data *dsi, int vc) { WARN_ON(!dsi_bus_is_locked(dsi)); WARN_ON(in_interrupt()); - if (!dsi_vc_is_enabled(dsi, channel)) + if (!dsi_vc_is_enabled(dsi, vc)) return 0; - switch (dsi->vc[channel].source) { + switch (dsi->vc[vc].source) { case DSI_VC_SOURCE_VP: - return dsi_sync_vc_vp(dsi, channel); + return dsi_sync_vc_vp(dsi, vc); case DSI_VC_SOURCE_L4: - return dsi_sync_vc_l4(dsi, channel); + return dsi_sync_vc_l4(dsi, vc); default: BUG(); return -EINVAL; } } -static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable) +static int dsi_vc_enable(struct dsi_data *dsi, int vc, bool enable) { - DSSDBG("dsi_vc_enable channel %d, enable %d\n", - channel, enable); + DSSDBG("dsi_vc_enable vc %d, enable %d\n", + vc, enable); enable = enable ? 1 : 0; - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0); + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0); - if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) { + if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 0, enable)) { DSSERR("Failed to set dsi_vc_enable to %d\n", enable); return -EIO; } @@ -2370,17 +2370,17 @@ static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable) return 0; } -static void dsi_vc_initial_config(struct dsi_data *dsi, int channel) +static void dsi_vc_initial_config(struct dsi_data *dsi, int vc) { u32 r; - DSSDBG("Initial config of virtual channel %d", channel); + DSSDBG("Initial config of VC %d", vc); - r = dsi_read_reg(dsi, DSI_VC_CTRL(channel)); + r = dsi_read_reg(dsi, DSI_VC_CTRL(vc)); if (FLD_GET(r, 15, 15)) /* VC_BUSY */ DSSERR("VC(%d) busy when trying to configure it!\n", - channel); + vc); r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ @@ -2395,76 +2395,76 @@ static void dsi_vc_initial_config(struct dsi_data *dsi, int channel) r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ - dsi_write_reg(dsi, DSI_VC_CTRL(channel), r); + dsi_write_reg(dsi, DSI_VC_CTRL(vc), r); - dsi->vc[channel].source = DSI_VC_SOURCE_L4; + dsi->vc[vc].source = DSI_VC_SOURCE_L4; } -static int dsi_vc_config_source(struct dsi_data *dsi, int channel, +static int dsi_vc_config_source(struct dsi_data *dsi, int vc, enum dsi_vc_source source) { - if (dsi->vc[channel].source == source) + if (dsi->vc[vc].source == source) return 0; - DSSDBG("Source config of virtual channel %d", channel); + DSSDBG("Source config of VC %d", vc); - dsi_sync_vc(dsi, channel); + dsi_sync_vc(dsi, vc); - dsi_vc_enable(dsi, channel, 0); + dsi_vc_enable(dsi, vc, 0); /* VC_BUSY */ - if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) { - DSSERR("vc(%d) busy when trying to config for VP\n", channel); + if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 15, 0)) { + DSSERR("vc(%d) busy when trying to config for VP\n", vc); return -EIO; } /* SOURCE, 0 = L4, 1 = video port */ - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1); + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), source, 1, 1); /* DCS_CMD_ENABLE */ if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { bool enable = source == DSI_VC_SOURCE_VP; - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30); + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 30, 30); } - dsi_vc_enable(dsi, channel, 1); + dsi_vc_enable(dsi, vc, 1); - dsi->vc[channel].source = source; + dsi->vc[vc].source = source; return 0; } -static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, +static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc, bool enable) { struct dsi_data *dsi = to_dsi_data(dssdev); - DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); + DSSDBG("dsi_vc_enable_hs(%d, %d)\n", vc, enable); WARN_ON(!dsi_bus_is_locked(dsi)); - dsi_vc_enable(dsi, channel, 0); + dsi_vc_enable(dsi, vc, 0); dsi_if_enable(dsi, 0); - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9); + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9); - dsi_vc_enable(dsi, channel, 1); + dsi_vc_enable(dsi, vc, 1); dsi_if_enable(dsi, 1); dsi_force_tx_stop_mode_io(dsi); /* start the DDR clock by sending a NULL packet */ if (dsi->vm_timings.ddr_clk_always_on && enable) - dsi_vc_send_null(dsi, channel); + dsi_vc_send_null(dsi, vc); dsi->in_lp_mode = !enable; } -static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel) +static void dsi_vc_flush_long_data(struct dsi_data *dsi, int vc) { - while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { + while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { u32 val; - val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); + val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", (val >> 0) & 0xff, (val >> 8) & 0xff, @@ -2510,13 +2510,13 @@ static void dsi_show_rx_ack_with_err(u16 err) DSSERR("\t\tDSI Protocol Violation\n"); } -static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel) +static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int vc) { /* RX_FIFO_NOT_EMPTY */ - while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { + while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { u32 val; u8 dt; - val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); + val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); DSSERR("\trawval %#08x\n", val); dt = FLD_GET(val, 5, 0); if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { @@ -2531,7 +2531,7 @@ static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel) } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { DSSERR("\tDCS long response, len %d\n", FLD_GET(val, 23, 8)); - dsi_vc_flush_long_data(dsi, channel); + dsi_vc_flush_long_data(dsi, vc); } else { DSSERR("\tunknown datatype 0x%02x\n", dt); } @@ -2539,35 +2539,35 @@ static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel) return 0; } -static int dsi_vc_send_bta(struct dsi_data *dsi, int channel) +static int dsi_vc_send_bta(struct dsi_data *dsi, int vc) { if (dsi->debug_write || dsi->debug_read) - DSSDBG("dsi_vc_send_bta %d\n", channel); + DSSDBG("dsi_vc_send_bta %d\n", vc); WARN_ON(!dsi_bus_is_locked(dsi)); /* RX_FIFO_NOT_EMPTY */ - if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { + if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); - dsi_vc_flush_receive_data(dsi, channel); + dsi_vc_flush_receive_data(dsi, vc); } - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 6, 6); /* BTA_EN */ /* flush posted write */ - dsi_read_reg(dsi, DSI_VC_CTRL(channel)); + dsi_read_reg(dsi, DSI_VC_CTRL(vc)); return 0; } -static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) +static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int vc) { struct dsi_data *dsi = to_dsi_data(dssdev); DECLARE_COMPLETION_ONSTACK(completion); int r = 0; u32 err; - r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler, + r = dsi_register_isr_vc(dsi, vc, dsi_completion_handler, &completion, DSI_VC_IRQ_BTA); if (r) goto err0; @@ -2577,7 +2577,7 @@ static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) if (r) goto err1; - r = dsi_vc_send_bta(dsi, channel); + r = dsi_vc_send_bta(dsi, vc); if (r) goto err2; @@ -2598,13 +2598,13 @@ static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) dsi_unregister_isr(dsi, dsi_completion_handler, &completion, DSI_IRQ_ERROR_MASK); err1: - dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler, + dsi_unregister_isr_vc(dsi, vc, dsi_completion_handler, &completion, DSI_VC_IRQ_BTA); err0: return r; } -static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel, +static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc, u8 data_type, u16 len, u8 ecc) { u32 val; @@ -2612,15 +2612,15 @@ static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel, WARN_ON(!dsi_bus_is_locked(dsi)); - data_id = data_type | channel << 6; + data_id = data_type | vc << 6; val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | FLD_VAL(ecc, 31, 24); - dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val); + dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(vc), val); } -static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel, +static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int vc, u8 b1, u8 b2, u8 b3, u8 b4) { u32 val; @@ -2630,7 +2630,7 @@ static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel, /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", b1, b2, b3, b4, val); */ - dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); + dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val); } static int dsi_vc_send_long(struct dsi_data *dsi, @@ -2727,10 +2727,10 @@ static int dsi_vc_send_short(struct dsi_data *dsi, return 0; } -static int dsi_vc_send_null(struct dsi_data *dsi, int channel) +static int dsi_vc_send_null(struct dsi_data *dsi, int vc) { const struct mipi_dsi_msg msg = { - .channel = channel, + .channel = vc, .type = MIPI_DSI_NULL_PACKET, }; @@ -2774,7 +2774,7 @@ static int dsi_vc_write_common(struct omap_dss_device *dssdev, return 0; } -static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, +static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int vc, u8 *buf, int buflen, enum dss_dsi_content_type type) { u32 val; @@ -2782,13 +2782,13 @@ static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, int r; /* RX_FIFO_NOT_EMPTY */ - if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) { + if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) { DSSERR("RX fifo empty when trying to read.\n"); r = -EIO; goto err; } - val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); + val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); if (dsi->debug_read) DSSDBG("\theader: %08x\n", val); dt = FLD_GET(val, 5, 0); @@ -2852,7 +2852,7 @@ static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, for (w = 0; w < len + 2;) { int b; val = dsi_read_reg(dsi, - DSI_VC_SHORT_PACKET_HEADER(channel)); + DSI_VC_SHORT_PACKET_HEADER(vc)); if (dsi->debug_read) DSSDBG("\t\t%02x %02x %02x %02x\n", (val >> 0) & 0xff, @@ -2876,7 +2876,7 @@ static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, } err: - DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, + DSSERR("dsi_vc_read_rx_fifo(vc %d type %s) failed\n", vc, type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); return r; @@ -3631,7 +3631,7 @@ static int dsi_configure_pins(struct dsi_data *dsi, return 0; } -static void dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) +static void dsi_enable_video_output(struct omap_dss_device *dssdev, int vc) { struct dsi_data *dsi = to_dsi_data(dssdev); int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); @@ -3665,17 +3665,17 @@ static void dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) } dsi_if_enable(dsi, false); - dsi_vc_enable(dsi, channel, false); + dsi_vc_enable(dsi, vc, false); /* MODE, 1 = video mode */ - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4); + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4); word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); - dsi_vc_write_long_header(dsi, channel, data_type, + dsi_vc_write_long_header(dsi, vc, data_type, word_count, 0); - dsi_vc_enable(dsi, channel, true); + dsi_vc_enable(dsi, vc, true); dsi_if_enable(dsi, true); } @@ -3688,7 +3688,7 @@ static void dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) err_mgr_enable: if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { dsi_if_enable(dsi, false); - dsi_vc_enable(dsi, channel, false); + dsi_vc_enable(dsi, vc, false); } err_pix_fmt: dsi_display_uninit_dispc(dsi); @@ -3696,18 +3696,18 @@ static void dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) return; } -static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) +static void dsi_disable_video_output(struct omap_dss_device *dssdev, int vc) { struct dsi_data *dsi = to_dsi_data(dssdev); if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { dsi_if_enable(dsi, false); - dsi_vc_enable(dsi, channel, false); + dsi_vc_enable(dsi, vc, false); /* MODE, 0 = command mode */ - REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4); + REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 0, 4, 4); - dsi_vc_enable(dsi, channel, true); + dsi_vc_enable(dsi, vc, true); dsi_if_enable(dsi, true); } @@ -3740,14 +3740,14 @@ static void dsi_update_screen_dispc(struct dsi_data *dsi) unsigned int packet_len; u32 l; int r; - const unsigned channel = dsi->update_channel; + const unsigned vc = dsi->update_vc; const unsigned int line_buf_size = dsi->line_buffer_size; u16 w = dsi->vm.hactive; u16 h = dsi->vm.vactive; DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); - dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP); + dsi_vc_config_source(dsi, vc, DSI_VC_SOURCE_VP); bytespp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; bytespl = w * bytespp; @@ -3768,16 +3768,16 @@ static void dsi_update_screen_dispc(struct dsi_data *dsi) total_len += (bytespf % packet_payload) + 1; l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ - dsi_write_reg(dsi, DSI_VC_TE(channel), l); + dsi_write_reg(dsi, DSI_VC_TE(vc), l); - dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE, + dsi_vc_write_long_header(dsi, vc, MIPI_DSI_DCS_LONG_WRITE, packet_len, 0); if (dsi->te_enabled) l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ else l = FLD_MOD(l, 1, 31, 31); /* TE_START */ - dsi_write_reg(dsi, DSI_VC_TE(channel), l); + dsi_write_reg(dsi, DSI_VC_TE(vc), l); /* We put SIDLEMODE to no-idle for the duration of the transfer, * because DSS interrupts are not capable of waking up the CPU and the @@ -3800,7 +3800,7 @@ static void dsi_update_screen_dispc(struct dsi_data *dsi) * for TE is longer than the timer allows */ REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ - dsi_vc_send_bta(dsi, channel); + dsi_vc_send_bta(dsi, vc); #ifdef DSI_CATCH_MISSING_TE mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); @@ -3897,7 +3897,7 @@ static int _dsi_send_nop(struct dsi_data *dsi, int channel) return _omap_dsi_host_transfer(dsi, &msg); } -static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) +static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) { struct dsi_data *dsi = to_dsi_data(dssdev); int r; @@ -3914,7 +3914,7 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) goto err; } - DSSDBG("dsi_update_channel: %d", channel); + DSSDBG("dsi_update_channel: %d", vc); dsi_set_ulps_auto(dsi, false); @@ -3923,13 +3923,13 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int channel) * updates stop working. This is probably related to DSI spec stating * that the DSI host should transition to LP at least once per frame. */ - r = _dsi_send_nop(dsi, channel); + r = _dsi_send_nop(dsi, vc); if (r < 0) { DSSWARN("failed to send nop between frames: %d\n", r); goto err; } - dsi->update_channel = channel; + dsi->update_vc = vc; if (dsi->te_enabled && dsi->te_gpio) { schedule_delayed_work(&dsi->te_timeout_work, From patchwork Tue Dec 8 12:28:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3225EC433FE for ; Tue, 8 Dec 2020 12:31:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFE3023ABA for ; Tue, 8 Dec 2020 12:31:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728496AbgLHMbL (ORCPT ); Tue, 8 Dec 2020 07:31:11 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33576 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727992AbgLHMbL (ORCPT ); Tue, 8 Dec 2020 07:31:11 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CUBhZ064399; Tue, 8 Dec 2020 06:30:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430611; bh=mbqWdYhHkd9811N/oed4zL3TdB7WbD0GV37g7DUAyJ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ODhxgbvvgwrLkR7Kok2fVoAo96lNMV4eM3qj/3u26Uz4Vu0GVPOC6ZAsUvGSwjbrU tfOvPnUApvZ3NN0fN8NOTqG+nCxQdplNBVGAjeJ4f28vdXS2xoSIJMbhzSJ+aB2yB1 ktoMapCU5RbRN+0zzPSiuuGAaB5n4TpfmDEY2O+M= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CUATF105108 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:10 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:09 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:09 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjP095068; Tue, 8 Dec 2020 06:30:07 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 11/29] drm/omap: dsi: pass vc to various functions Date: Tue, 8 Dec 2020 14:28:37 +0200 Message-ID: <20201208122855.254819-12-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org To start fixing the issues related to channels and vcs described in the previous commit, pass vc to various functions which will need it do properly handle different DSI channels and VCs. No functional changes. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 54 ++++++++++++++++--------------- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 273159e8f992..8d8412199693 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -214,9 +214,9 @@ static void dsi_set_ulps_auto(struct dsi_data *dsi, bool enable); static int dsi_display_init_dispc(struct dsi_data *dsi); static void dsi_display_uninit_dispc(struct dsi_data *dsi); -static int dsi_vc_send_null(struct dsi_data *dsi, int vc); +static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel); -static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, +static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, const struct mipi_dsi_msg *msg); static void dsi_display_disable(struct omap_dss_device *dssdev); @@ -2455,7 +2455,7 @@ static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc, /* start the DDR clock by sending a NULL packet */ if (dsi->vm_timings.ddr_clk_always_on && enable) - dsi_vc_send_null(dsi, vc); + dsi_vc_send_null(dsi, vc, dsi->dsidev->channel); dsi->in_lp_mode = !enable; } @@ -2605,7 +2605,8 @@ static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int vc) } static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc, - u8 data_type, u16 len, u8 ecc) + int channel, u8 data_type, u16 len, + u8 ecc) { u32 val; u8 data_id; @@ -2633,7 +2634,7 @@ static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int vc, dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val); } -static int dsi_vc_send_long(struct dsi_data *dsi, +static int dsi_vc_send_long(struct dsi_data *dsi, int vc, const struct mipi_dsi_msg *msg) { /*u32 val; */ @@ -2653,7 +2654,7 @@ static int dsi_vc_send_long(struct dsi_data *dsi, dsi_vc_config_source(dsi, msg->channel, DSI_VC_SOURCE_L4); - dsi_vc_write_long_header(dsi, msg->channel, msg->type, msg->tx_len, 0); + dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0); p = msg->tx_buf; for (i = 0; i < msg->tx_len >> 2; i++) { @@ -2696,7 +2697,7 @@ static int dsi_vc_send_long(struct dsi_data *dsi, return r; } -static int dsi_vc_send_short(struct dsi_data *dsi, +static int dsi_vc_send_short(struct dsi_data *dsi, int vc, const struct mipi_dsi_msg *msg) { struct mipi_dsi_packet pkt; @@ -2727,26 +2728,26 @@ static int dsi_vc_send_short(struct dsi_data *dsi, return 0; } -static int dsi_vc_send_null(struct dsi_data *dsi, int vc) +static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel) { const struct mipi_dsi_msg msg = { .channel = vc, .type = MIPI_DSI_NULL_PACKET, }; - return dsi_vc_send_long(dsi, &msg); + return dsi_vc_send_long(dsi, vc, &msg); } -static int dsi_vc_write_common(struct omap_dss_device *dssdev, +static int dsi_vc_write_common(struct omap_dss_device *dssdev, int vc, const struct mipi_dsi_msg *msg) { struct dsi_data *dsi = to_dsi_data(dssdev); int r; if (mipi_dsi_packet_format_is_short(msg->type)) - r = dsi_vc_send_short(dsi, msg); + r = dsi_vc_send_short(dsi, vc, msg); else - r = dsi_vc_send_long(dsi, msg); + r = dsi_vc_send_long(dsi, vc, msg); if (r < 0) return r; @@ -2882,7 +2883,7 @@ static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int vc, u8 *buf, return r; } -static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, +static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int vc, const struct mipi_dsi_msg *msg) { struct dsi_data *dsi = to_dsi_data(dssdev); @@ -2893,7 +2894,7 @@ static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, if (dsi->debug_read) DSSDBG("%s(ch %d, cmd %x)\n", __func__, channel, cmd); - r = dsi_vc_send_short(dsi, msg); + r = dsi_vc_send_short(dsi, vc, msg); if (r) goto err; @@ -2917,13 +2918,13 @@ static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, return r; } -static int dsi_vc_generic_read(struct omap_dss_device *dssdev, +static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int vc, const struct mipi_dsi_msg *msg) { struct dsi_data *dsi = to_dsi_data(dssdev); int r; - r = dsi_vc_send_short(dsi, msg); + r = dsi_vc_send_short(dsi, vc, msg); if (r) goto err; @@ -3672,7 +3673,7 @@ static void dsi_enable_video_output(struct omap_dss_device *dssdev, int vc) word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); - dsi_vc_write_long_header(dsi, vc, data_type, + dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, data_type, word_count, 0); dsi_vc_enable(dsi, vc, true); @@ -3770,7 +3771,7 @@ static void dsi_update_screen_dispc(struct dsi_data *dsi) l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ dsi_write_reg(dsi, DSI_VC_TE(vc), l); - dsi_vc_write_long_header(dsi, vc, MIPI_DSI_DCS_LONG_WRITE, + dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, MIPI_DSI_DCS_LONG_WRITE, packet_len, 0); if (dsi->te_enabled) @@ -3882,7 +3883,7 @@ static int _dsi_update(struct dsi_data *dsi) return 0; } -static int _dsi_send_nop(struct dsi_data *dsi, int channel) +static int _dsi_send_nop(struct dsi_data *dsi, int vc, int channel) { const u8 payload[] = { MIPI_DCS_NOP }; const struct mipi_dsi_msg msg = { @@ -3894,7 +3895,7 @@ static int _dsi_send_nop(struct dsi_data *dsi, int channel) WARN_ON(!dsi_bus_is_locked(dsi)); - return _omap_dsi_host_transfer(dsi, &msg); + return _omap_dsi_host_transfer(dsi, vc, &msg); } static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) @@ -3923,7 +3924,7 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) * updates stop working. This is probably related to DSI spec stating * that the DSI host should transition to LP at least once per frame. */ - r = _dsi_send_nop(dsi, vc); + r = _dsi_send_nop(dsi, vc, dsi->dsidev->channel); if (r < 0) { DSSWARN("failed to send nop between frames: %d\n", r); goto err; @@ -4885,7 +4886,7 @@ static enum omap_channel dsi_get_dispc_channel(struct dsi_data *dsi) } } -static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, +static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, const struct mipi_dsi_msg *msg) { struct omap_dss_device *dssdev = &dsi->output; @@ -4905,15 +4906,15 @@ static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, case MIPI_DSI_DCS_LONG_WRITE: case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: case MIPI_DSI_NULL_PACKET: - r = dsi_vc_write_common(dssdev, msg); + r = dsi_vc_write_common(dssdev, vc, msg); break; case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: - r = dsi_vc_generic_read(dssdev, msg); + r = dsi_vc_generic_read(dssdev, vc, msg); break; case MIPI_DSI_DCS_READ: - r = dsi_vc_dcs_read(dssdev, msg); + r = dsi_vc_dcs_read(dssdev, vc, msg); break; default: r = -EINVAL; @@ -4941,12 +4942,13 @@ static ssize_t omap_dsi_host_transfer(struct mipi_dsi_host *host, { struct dsi_data *dsi = host_to_omap(host); int r; + int vc = VC_DEFAULT; dsi_bus_lock(dsi); if (dsi->video_enabled) { dsi_set_ulps_auto(dsi, false); - r = _omap_dsi_host_transfer(dsi, msg); + r = _omap_dsi_host_transfer(dsi, vc, msg); dsi_set_ulps_auto(dsi, true); } else { r = -EIO; From patchwork Tue Dec 8 12:28:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C9AFC4361B for ; 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Tue, 8 Dec 2020 06:30:12 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:12 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:12 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjQ095068; Tue, 8 Dec 2020 06:30:09 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 12/29] drm/omap: dsi: untangle vc & channel Date: Tue, 8 Dec 2020 14:28:38 +0200 Message-ID: <20201208122855.254819-13-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org DSI virtual channel and hardware VC blocks have gotten tangled as described in the previous commits. This has not caused any issues, as the value for both is 0, so it happens to work. To fix the issue, change the code to use the correct one of the two. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 43 +++++++++++++++---------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 8d8412199693..a1f3623f45b1 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -2613,7 +2613,7 @@ static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc, WARN_ON(!dsi_bus_is_locked(dsi)); - data_id = data_type | vc << 6; + data_id = data_type | channel << 6; val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | FLD_VAL(ecc, 31, 24); @@ -2647,12 +2647,12 @@ static int dsi_vc_send_long(struct dsi_data *dsi, int vc, DSSDBG("dsi_vc_send_long, %d bytes\n", msg->tx_len); /* len + header */ - if (dsi->vc[msg->channel].tx_fifo_size * 32 * 4 < msg->tx_len + 4) { + if (dsi->vc[vc].tx_fifo_size * 32 * 4 < msg->tx_len + 4) { DSSERR("unable to send long packet: packet too long.\n"); return -EINVAL; } - dsi_vc_config_source(dsi, msg->channel, DSI_VC_SOURCE_L4); + dsi_vc_config_source(dsi, vc, DSI_VC_SOURCE_L4); dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0); @@ -2666,7 +2666,7 @@ static int dsi_vc_send_long(struct dsi_data *dsi, int vc, b3 = *p++; b4 = *p++; - dsi_vc_write_long_payload(dsi, msg->channel, b1, b2, b3, b4); + dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, b4); } i = msg->tx_len % 4; @@ -2691,7 +2691,7 @@ static int dsi_vc_send_long(struct dsi_data *dsi, int vc, break; } - dsi_vc_write_long_payload(dsi, msg->channel, b1, b2, b3, 0); + dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, 0); } return r; @@ -2711,11 +2711,11 @@ static int dsi_vc_send_short(struct dsi_data *dsi, int vc, if (dsi->debug_write) DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", - msg->channel, msg->type, pkt.header[1], pkt.header[2]); + vc, msg->type, pkt.header[1], pkt.header[2]); - dsi_vc_config_source(dsi, msg->channel, DSI_VC_SOURCE_L4); + dsi_vc_config_source(dsi, vc, DSI_VC_SOURCE_L4); - if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(msg->channel)), 16, 16)) { + if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) { DSSERR("ERROR FIFO FULL, aborting transfer\n"); return -EINVAL; } @@ -2723,7 +2723,7 @@ static int dsi_vc_send_short(struct dsi_data *dsi, int vc, r = pkt.header[3] << 24 | pkt.header[2] << 16 | pkt.header[1] << 8 | pkt.header[0]; - dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(msg->channel), r); + dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc), r); return 0; } @@ -2731,7 +2731,7 @@ static int dsi_vc_send_short(struct dsi_data *dsi, int vc, static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel) { const struct mipi_dsi_msg msg = { - .channel = vc, + .channel = channel, .type = MIPI_DSI_NULL_PACKET, }; @@ -2759,16 +2759,16 @@ static int dsi_vc_write_common(struct omap_dss_device *dssdev, int vc, * In that case we can return early. */ - r = dsi_vc_send_bta_sync(dssdev, msg->channel); + r = dsi_vc_send_bta_sync(dssdev, vc); if (r) { DSSERR("bta sync failed\n"); return r; } /* RX_FIFO_NOT_EMPTY */ - if (REG_GET(dsi, DSI_VC_CTRL(msg->channel), 20, 20)) { + if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { DSSERR("rx fifo not empty after write, dumping data:\n"); - dsi_vc_flush_receive_data(dsi, msg->channel); + dsi_vc_flush_receive_data(dsi, vc); return -EIO; } @@ -2888,21 +2888,20 @@ static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int vc, { struct dsi_data *dsi = to_dsi_data(dssdev); u8 cmd = ((u8 *)msg->tx_buf)[0]; - u8 channel = msg->channel; int r; if (dsi->debug_read) - DSSDBG("%s(ch %d, cmd %x)\n", __func__, channel, cmd); + DSSDBG("%s(ch %d, cmd %x)\n", __func__, vc, cmd); r = dsi_vc_send_short(dsi, vc, msg); if (r) goto err; - r = dsi_vc_send_bta_sync(dssdev, channel); + r = dsi_vc_send_bta_sync(dssdev, vc); if (r) goto err; - r = dsi_vc_read_rx_fifo(dsi, channel, msg->rx_buf, msg->rx_len, + r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, DSS_DSI_CONTENT_DCS); if (r < 0) goto err; @@ -2914,7 +2913,7 @@ static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int vc, return 0; err: - DSSERR("%s(ch %d, cmd 0x%02x) failed\n", __func__, msg->channel, cmd); + DSSERR("%s(ch %d, cmd 0x%02x) failed\n", __func__, vc, cmd); return r; } @@ -2928,11 +2927,11 @@ static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int vc, if (r) goto err; - r = dsi_vc_send_bta_sync(dssdev, msg->channel); + r = dsi_vc_send_bta_sync(dssdev, vc); if (r) goto err; - r = dsi_vc_read_rx_fifo(dsi, msg->channel, msg->rx_buf, msg->rx_len, + r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, DSS_DSI_CONTENT_GENERIC); if (r < 0) goto err; @@ -2944,7 +2943,7 @@ static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int vc, return 0; err: - DSSERR("%s(ch %d, reqlen %d) failed\n", __func__, msg->channel, msg->tx_len); + DSSERR("%s(ch %d, reqlen %d) failed\n", __func__, vc, msg->tx_len); return r; } @@ -4893,7 +4892,7 @@ static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, int r; if (!!(msg->flags & MIPI_DSI_MSG_USE_LPM) != dsi->in_lp_mode) - dsi_vc_enable_hs(dssdev, msg->channel, + dsi_vc_enable_hs(dssdev, vc, !(msg->flags & MIPI_DSI_MSG_USE_LPM)); switch (msg->type) { From patchwork Tue Dec 8 12:28:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5965C4361B for ; Tue, 8 Dec 2020 12:32:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B50C23AC0 for ; Tue, 8 Dec 2020 12:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728935AbgLHMb7 (ORCPT ); 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Tue, 8 Dec 2020 06:30:14 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:14 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjR095068; Tue, 8 Dec 2020 06:30:12 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 13/29] drm/omap: dsi: skip dsi_vc_enable_hs when already in correct mode Date: Tue, 8 Dec 2020 14:28:39 +0200 Message-ID: <20201208122855.254819-14-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Simplify and optimize dsi_vc_enable_hs() so that it can be called without checking the current HS/LP mode. Make dsi_vc_enable_hs() return if the VC is already in the correct mode. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index a1f3623f45b1..544f5f1eed91 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -341,7 +341,6 @@ struct dsi_data { int irq; bool is_enabled; - bool in_lp_mode; struct clk *dss_clk; struct regmap *syscon; @@ -2441,6 +2440,9 @@ static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc, DSSDBG("dsi_vc_enable_hs(%d, %d)\n", vc, enable); + if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable) + return; + WARN_ON(!dsi_bus_is_locked(dsi)); dsi_vc_enable(dsi, vc, 0); @@ -2456,8 +2458,6 @@ static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc, /* start the DDR clock by sending a NULL packet */ if (dsi->vm_timings.ddr_clk_always_on && enable) dsi_vc_send_null(dsi, vc, dsi->dsidev->channel); - - dsi->in_lp_mode = !enable; } static void dsi_vc_flush_long_data(struct dsi_data *dsi, int vc) @@ -4891,9 +4891,7 @@ static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, struct omap_dss_device *dssdev = &dsi->output; int r; - if (!!(msg->flags & MIPI_DSI_MSG_USE_LPM) != dsi->in_lp_mode) - dsi_vc_enable_hs(dssdev, vc, - !(msg->flags & MIPI_DSI_MSG_USE_LPM)); + dsi_vc_enable_hs(dssdev, vc, !(msg->flags & MIPI_DSI_MSG_USE_LPM)); switch (msg->type) { case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: From patchwork Tue Dec 8 12:28:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B88C433FE for ; Tue, 8 Dec 2020 12:32:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E70D723ABA for ; Tue, 8 Dec 2020 12:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728964AbgLHMcD (ORCPT ); Tue, 8 Dec 2020 07:32:03 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45280 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726138AbgLHMcD (ORCPT ); Tue, 8 Dec 2020 07:32:03 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CUHC5067103; Tue, 8 Dec 2020 06:30:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430617; bh=p8fgXDo0kWiZis2f4fiEK5csDQUggLZyPg0XkKn0Bvc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lmbk+ysF0DyBJ257hsAfT4DPhPUbbNTiMVdxYo5Gymkv+W7CycyrM5jrPl3WJs5Bk Vv//gkDW5TMz7lUNUHndpI5QoRR7TDDWCW/SxLhdCRIzJXCQfbPu11yWSqOMJyWFgJ Z+u7BjsjYTDO/HCMgqQjutcNiQQ+yKf2idZLaYmI= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CUHiV088096 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:17 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:17 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:17 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjS095068; Tue, 8 Dec 2020 06:30:15 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 14/29] drm/omap: dsi: enable HS before sending the frame Date: Tue, 8 Dec 2020 14:28:40 +0200 Message-ID: <20201208122855.254819-15-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org We currently use a single VC for sending commands and pixel data. The LP/HS mode for pixel data is correctly set to HS by accident, as we have set the VC to HS already earlier. However, if we use a different VC for video data, the VC is in LP mode. Fix this by always enabling HS mode before starting a frame update. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 544f5f1eed91..9d210a020916 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -3918,6 +3918,8 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) dsi_set_ulps_auto(dsi, false); + dsi_vc_enable_hs(dssdev, vc, true); + /* * Send NOP between the frames. If we don't send something here, the * updates stop working. This is probably related to DSI spec stating From patchwork Tue Dec 8 12:28:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06812C4361B for ; Tue, 8 Dec 2020 12:31:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D454523ABA for ; Tue, 8 Dec 2020 12:31:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728548AbgLHMbU (ORCPT ); Tue, 8 Dec 2020 07:31:20 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33608 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727992AbgLHMbT (ORCPT ); Tue, 8 Dec 2020 07:31:19 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CUKpE064474; Tue, 8 Dec 2020 06:30:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430620; bh=1dCEnoODmf/uf86HI8DG1XPvwgsxHhJzTZoSkz0WNb8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rhboifzp4iI0oGov4ikbejaJtbA644xphHtH6IVDjqj/xonpDK5BOGTn/HA/vEnnV 70peldcyexpV5hyr0G0WFvzycW/bMT3wQoYkW35QWLc5D6GSsl48GAh7ZOJ/lw+89v lRBB+RvwRqdZgfoxZl/B5e4KIeeDOfCsib/dM+ro= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CUKBq038795 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:20 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:19 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:19 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjT095068; Tue, 8 Dec 2020 06:30:17 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 15/29] drm/omap: dsi: use separate VCs for cmd and video Date: Tue, 8 Dec 2020 14:28:41 +0200 Message-ID: <20201208122855.254819-16-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org For command mode panels we can use a single VC for sending command and video data, even if we have to change the data source for that VC when going from command to video or vice versa. However, with video mode panels we want to keep the pixel data VC enabled, and use another VC for command data, and the commands will get interleaved into the pixel data. This patch makes the driver use VC0 for commands and VC1 for video. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/omapdrm/dss/dsi.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 9d210a020916..0795efdd8902 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -452,7 +452,9 @@ static bool dsi_perf; module_param(dsi_perf, bool, 0644); #endif -#define VC_DEFAULT 0 +/* Note: for some reason video mode seems to work only if VC_VIDEO is 0 */ +#define VC_VIDEO 0 +#define VC_CMD 1 #define drm_bridge_to_dsi(bridge) \ container_of(bridge, struct dsi_data, bridge) @@ -3723,7 +3725,7 @@ static void dsi_disable_video_outputs(struct omap_dss_device *dssdev) dsi_bus_lock(dsi); dsi->video_enabled = false; - dsi_disable_video_output(dssdev, VC_DEFAULT); + dsi_disable_video_output(dssdev, VC_VIDEO); dsi_display_disable(dssdev); @@ -3951,7 +3953,7 @@ static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) static int dsi_update_all(struct omap_dss_device *dssdev) { - return dsi_update_channel(dssdev, VC_DEFAULT); + return dsi_update_channel(dssdev, VC_VIDEO); } /* Display funcs */ @@ -4184,7 +4186,7 @@ static void dsi_enable_video_outputs(struct omap_dss_device *dssdev) dsi_display_enable(dssdev); - dsi_enable_video_output(dssdev, VC_DEFAULT); + dsi_enable_video_output(dssdev, VC_VIDEO); dsi->video_enabled = true; @@ -4941,7 +4943,7 @@ static ssize_t omap_dsi_host_transfer(struct mipi_dsi_host *host, { struct dsi_data *dsi = host_to_omap(host); int r; - int vc = VC_DEFAULT; + int vc = VC_CMD; dsi_bus_lock(dsi); From patchwork Tue Dec 8 12:28:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39F90C4361B for ; Tue, 8 Dec 2020 12:31:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09AC523ABA for ; Tue, 8 Dec 2020 12:31:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728671AbgLHMbW (ORCPT ); Tue, 8 Dec 2020 07:31:22 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45328 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727992AbgLHMbW (ORCPT ); Tue, 8 Dec 2020 07:31:22 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CUMSJ067118; Tue, 8 Dec 2020 06:30:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430622; bh=7qaic8oBzhOGxIzW8dafxwEH0G1wJEv0kwjGjnXYmPE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=n0LwHDM8/UAB823z63a+lDCFU+B+4yQDr8/VMThj+maS8RNXjO+VZjOfSk3nTdPIu TfOC0C8BZmexQXGDqx/QbW+eL8bB0ST3NaYeSeyXtesZGfUS46uMiYuCJxwrdwMEgV rNTsUwKn6oxY7lLYb6YdL1B1pohD0gUTURMRa1wI= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CUMxT088302 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:22 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:22 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:22 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjU095068; Tue, 8 Dec 2020 06:30:20 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 16/29] drm/panel: panel-dsi-cm: remove extra 'if' Date: Tue, 8 Dec 2020 14:28:42 +0200 Message-ID: <20201208122855.254819-17-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org We have a useless 'if' in the dsicm_bl_update_status(), a left over from the conversion to DRM model. Drop the if. Signed-off-by: Tomi Valkeinen Reviewed-by: Sam Ravnborg Reviewed-by: Laurent Pinchart Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/panel/panel-dsi-cm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-dsi-cm.c b/drivers/gpu/drm/panel/panel-dsi-cm.c index 556f9a2c5c0c..fa564aad7f25 100644 --- a/drivers/gpu/drm/panel/panel-dsi-cm.c +++ b/drivers/gpu/drm/panel/panel-dsi-cm.c @@ -202,11 +202,9 @@ static int dsicm_bl_update_status(struct backlight_device *dev) mutex_lock(&ddata->lock); - if (ddata->enabled) { - if (!r) - r = dsicm_dcs_write_1( - ddata, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, level); - } + if (ddata->enabled) + r = dsicm_dcs_write_1(ddata, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + level); mutex_unlock(&ddata->lock); From patchwork Tue Dec 8 12:28:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11958525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 206C1C4361B for ; Tue, 8 Dec 2020 12:32:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E94EE23ABA for ; Tue, 8 Dec 2020 12:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728956AbgLHMcK (ORCPT ); Tue, 8 Dec 2020 07:32:10 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33704 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726138AbgLHMcK (ORCPT ); Tue, 8 Dec 2020 07:32:10 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CUPkZ064482; Tue, 8 Dec 2020 06:30:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607430625; bh=3b2609oIQlT2iz7RzdR0SCU/skLSyH9xtXCKimHUvQQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BggVxOAyMJv1gHPfh4B1KBTSzh9V/0XhYN+muhKevoNj9Cd19NS3uWWkipo0HNtha fWf+iXA0tGK/i1z0XsLJUDNMeIEG870lYilW+ue6YDA29/hbKAUwOGsgUQGBXogQc0 6cAffuTpQ2Emot7Ksbmh3HYWEH/Wpu+fPQl/hM4o= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8CUP3Z014448 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 06:30:25 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 06:30:25 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 06:30:25 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B8CTcjV095068; Tue, 8 Dec 2020 06:30:22 -0600 From: Tomi Valkeinen To: Sebastian Reichel , Laurent Pinchart , Nikhil Devshatwar , CC: , Sekhar Nori , Tony Lindgren , , Sam Ravnborg , Tomi Valkeinen Subject: [PATCH v5 17/29] drm/panel: panel-dsi-cm: add panel database to driver Date: Tue, 8 Dec 2020 14:28:43 +0200 Message-ID: <20201208122855.254819-18-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208122855.254819-1-tomi.valkeinen@ti.com> References: <20201208122855.254819-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add a panel database to the driver instead of reading propertes from DT data. This is similar to panel-simple, and I believe it's more future safe way to handle the panels. Signed-off-by: Tomi Valkeinen Reviewed-by: Sam Ravnborg Reviewed-by: Sebastian Reichel --- drivers/gpu/drm/panel/panel-dsi-cm.c | 107 +++++++++++++++++---------- 1 file changed, 69 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-dsi-cm.c b/drivers/gpu/drm/panel/panel-dsi-cm.c index fa564aad7f25..3fb5b2856283 100644 --- a/drivers/gpu/drm/panel/panel-dsi-cm.c +++ b/drivers/gpu/drm/panel/panel-dsi-cm.c @@ -21,10 +21,7 @@ #include #include -#include