From patchwork Thu Nov 8 07:04:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 10673609 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84E7C17D4 for ; Thu, 8 Nov 2018 07:05:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74C2B2D701 for ; Thu, 8 Nov 2018 07:05:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68D542D801; Thu, 8 Nov 2018 07:05:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED87E2D725 for ; Thu, 8 Nov 2018 07:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725724AbeKHQja (ORCPT ); Thu, 8 Nov 2018 11:39:30 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:43322 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbeKHQja (ORCPT ); Thu, 8 Nov 2018 11:39:30 -0500 Received: by mail-pf1-f196.google.com with SMTP id g7-v6so6626011pfo.10 for ; Wed, 07 Nov 2018 23:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3vMxLtPf9r6hzmpfaef+RgAfUttYAOF79DIGRd82YSo=; b=bH/9IRHngeLTJxG4V4rnbQTFFcZwgE2I/NXi9zaplan6xTtRa9r18D5jcWATa6Qwbv xmH6Bj8o9p/dtXXSnBRkMN0sZty3dbVVqXhDbgQuQGVhlJTTXNtawMH+YSXEZO52H77O G28vluSynRk8+0CWkZVuXOEbtIeiAVB3lz+CE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3vMxLtPf9r6hzmpfaef+RgAfUttYAOF79DIGRd82YSo=; b=CGZpVD9k2wxtExJen6apgPF5gTs2Po1mrShqiMzA6gF9Pu3PbZoftzZD5UA7mq3vb5 ZmhDhz7yB/6YMsOz4zrGlWNQT2N7ZITgKJAMTvtc2vzO25jnECLqvKeO7m433qzIDsg+ R83x8HrmCkfl0D4Rwr7reR/9vxevW9/SY6+Zt0qIvsAYlwtN6jX5NQXBwWxQIAj/fPRf HScJ2dsvzJ7gTJmZ86FQr7nyYin5YyC+YxJ+HQfgCU4v7osGc9kMP1Tv/HOoJW/V9eQZ XSxvgVC9Jtv+IXL6W9vVZPDgJ3z4YHbkJhbcikhVMbe8WfGU1z6qLdwA1clHfrxS2Qtd DlvA== X-Gm-Message-State: AGRZ1gLqGxj0v2AyNjhkdZ52U+jjqQjQk9CkQmcgwwUqvU+XvxpzzUeG R5ARt6+acPiCUbQPlSAUhHLNxg== X-Google-Smtp-Source: AJdET5e8RhLLfaOy053JijMlGtP/0besP084dHmIO15CD5Km2YRS4yppepg/qrgjFjmAk4kdLQJ5QQ== X-Received: by 2002:aa7:804e:: with SMTP id y14-v6mr3361226pfm.73.1541660725587; Wed, 07 Nov 2018 23:05:25 -0800 (PST) Received: from localhost.localdomain (61-216-91-114.HINET-IP.hinet.net. [61.216.91.114]) by smtp.gmail.com with ESMTPSA id w63-v6sm2550618pgw.60.2018.11.07.23.05.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Nov 2018 23:05:24 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Sriharsha Allenki , Anu Ramanathan , Bjorn Andersson , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 1/2] dt-bindings: phy: Add Qualcomm Synopsys High-Speed USB PHY binding Date: Thu, 8 Nov 2018 15:04:48 +0800 Message-Id: <20181108070449.23572-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181108070449.23572-1-shawn.guo@linaro.org> References: <20181108070449.23572-1-shawn.guo@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sriharsha Allenki It adds bindings for Synopsys 28nm femto phy controller that supports LS/FS/HS usb connectivity on Qualcomm chipsets. Signed-off-by: Sriharsha Allenki Signed-off-by: Anu Ramanathan Signed-off-by: Bjorn Andersson Signed-off-by: Shawn Guo --- .../phy/qcom,snps-28nm-usb-hs-phy.txt | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt new file mode 100644 index 000000000000..75e7a09dd558 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt @@ -0,0 +1,101 @@ +Qualcomm Synopsys 28nm Femto phy controller +=========================================== + +Synopsys 28nm femto phy controller supports LS/FS/HS usb connectivity on +Qualcomm chipsets. + +Required properties: + +- compatible: + Value type: + Definition: Should contain "qcom,usb-snps-hsphy". + +- reg: + Value type: + Definition: USB PHY base address and length of the register map. + +- #phy-cells: + Value type: + Definition: Should be 0. + +- clocks: + Value type: + Definition: See clock-bindings.txt section "consumers". List of + three clock specifiers for reference, phy core and + sleep clocks. + +- clock-names: + Value type: + Definition: Names of the clocks in 1-1 correspondence with the "clocks" + property. Must contain "ref", "phy" and "sleep". + +- resets: + Value type: + Definition: See reset.txt section "consumers". PHY reset specifiers + for phy core and POR resets. + +- reset-names: + Value type: + Definition: Names of the resets in 1-1 correspondence with the "resets" + property. Must contain "phy" and "por". + +- vdd-supply: + Value type: + Definition: phandle to the regulator VDD supply node. + +- vdda1p8-supply: + Value type: + Definition: phandle to the regulator 1.8V supply node. + +- vdda3p3-supply: + Value type: + Definition: phandle to the regulator 3.3V supply node. + +- qcom,vdd-voltage-level: + Value type: + Definition: This is a list of three integer values where + each value corresponding to voltage corner in uV. + +Optional properties: + +- extcon: + Value type: + Definition: Should contain the vbus extcon. + +- qcom,init-seq: + Value type: + Definition: Should contain a sequence of tuples to + program 'value' into phy register at 'offset' with 'delay' + in us afterwards. + +Example: + + phy@7a000 { + compatible = "qcom,usb-snps-hsphy"; + reg = <0x7a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + qcom,init-seq = <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>; + }; From patchwork Thu Nov 8 07:04:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 10673611 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CD6C1057 for ; Thu, 8 Nov 2018 07:05:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B22A2D701 for ; Thu, 8 Nov 2018 07:05:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0E0832D725; Thu, 8 Nov 2018 07:05:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 036552D701 for ; Thu, 8 Nov 2018 07:05:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726736AbeKHQje (ORCPT ); Thu, 8 Nov 2018 11:39:34 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:39425 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbeKHQje (ORCPT ); Thu, 8 Nov 2018 11:39:34 -0500 Received: by mail-pg1-f196.google.com with SMTP id r9-v6so8458378pgv.6 for ; Wed, 07 Nov 2018 23:05:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b3XtQ7D3beA3BnefTuij4ySch3VdSSh3R1/oIOCMKaQ=; b=UeL0O7xaZWkTh/t3OyrOLhLe0o4cq8wQNaI6ZN1yyzff84xQhKldzQGkUEWIGYDSq2 i0rc29ikIOyPSg20+rFT/VGCzX8k+wOhhsxIIa5V9gakZveFiyUfSnrOLcbPJ3l2pSj/ tfQlmNDtMdu0hsHOKxOJE1AeW4qsdZYfEn5ec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b3XtQ7D3beA3BnefTuij4ySch3VdSSh3R1/oIOCMKaQ=; b=Wd5w8H/+9kyxO7/LAfUYEmJyrAjaCXybUg/oji0H2wLFxF5zaUBc3ZI15zw32QD/jK RmzW+DbhnQjjttXBF+DNFFcbfoWj0POA5PefxU9GPs5n4k5MsgASMn3w5k0O18zgZF2p dBJ+vKo+RoGU/slpQfQMwyWyIf185a7ISNe52YuhN2Fyi3oh1JlxsTmZ6SknPPT6EdDv 2sTlzA5+i12FG3EzdQZ7fYl2q1FeXbW17OM7hfuoGQGV55f7QN6kg/XF/ZUgLdxsziXq NOZPUzF0GSaeIgo7n05yG75XYNFFcGt0n1a/Ufb4ivLfdoYaERFlYcuNa9+47BUZinHT gguQ== X-Gm-Message-State: AGRZ1gIVH+50nQQRDxKU+tlRN+npvm+W+1UpMv2BQxtgwBN9tslb0ZFJ xSIPv+peXYL2IGEI4PdKkDymZA== X-Google-Smtp-Source: AJdET5d9xZvcBznxzQQVOLEd1Gpi+xy2SmDqWbm6xpWBxmamHCJbe0xQA2gFiC2lvqGqZwYSneq1Ig== X-Received: by 2002:a62:3687:: with SMTP id d129-v6mr3500787pfa.56.1541660729577; Wed, 07 Nov 2018 23:05:29 -0800 (PST) Received: from localhost.localdomain (61-216-91-114.HINET-IP.hinet.net. [61.216.91.114]) by smtp.gmail.com with ESMTPSA id w63-v6sm2550618pgw.60.2018.11.07.23.05.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Nov 2018 23:05:28 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Sriharsha Allenki , Anu Ramanathan , Bjorn Andersson , Vinod Koul , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 2/2] phy: qualcomm: Add Synopsys High-Speed USB PHY driver Date: Thu, 8 Nov 2018 15:04:49 +0800 Message-Id: <20181108070449.23572-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181108070449.23572-1-shawn.guo@linaro.org> References: <20181108070449.23572-1-shawn.guo@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It adds Synopsys 28nm Femto High-Speed USB PHY driver support, which is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. Signed-off-by: Shawn Guo --- drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + .../phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c | 494 ++++++++++++++++++ 3 files changed, 505 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 32f7d34eb784..c7b5ee82895d 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -82,3 +82,13 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_USB_HS_SNPS_28NM + tristate "Qualcomm Synopsys 28nm USB HS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Synopsys 28nm Femto USB PHY on Qualcomm + chips. This driver supports the high-speed PHY which is usually + paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index c56efd3af205..dc238d95b18c 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_USB_HS_SNPS_28NM) += phy-qcom-usb-hs-snsp-28nm.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c new file mode 100644 index 000000000000..e3b23ccd4d37 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2018, Linux Foundation. All rights reserved. + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PHY register and bit definitions */ +#define PHY_CTRL_COMMON0 0x078 +#define SIDDQ BIT(2) +#define PHY_IRQ_CMD 0x0d0 +#define PHY_INTR_CLEAR0 0x0dc +#define PHY_INTR_MASK0 0x0d4 +#define DPDM_MASK 0x1e +#define DP_1_0 BIT(4) +#define DP_0_1 BIT(3) +#define DM_1_0 BIT(2) +#define DM_0_1 BIT(1) + +enum hsphy_voltage { + VOL_NONE, + VOL_MIN, + VOL_MAX, + VOL_NUM, +}; + +enum hsphy_vreg { + VDD, + VDDA_1P8, + VDDA_3P3, + VREG_NUM, +}; + +struct hsphy_init_seq { + int offset; + int val; + int delay; +}; + +struct hsphy_priv { + void __iomem *base; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *phy_reset; + struct reset_control *por_reset; + struct regulator_bulk_data vregs[VREG_NUM]; + unsigned int voltages[VREG_NUM][VOL_NUM]; + struct hsphy_init_seq *init_seq; + bool cable_connected; + struct extcon_dev *vbus_edev; + struct notifier_block vbus_notify; + enum phy_mode mode; +}; + +static int qcom_snps_hsphy_config_regulators(struct hsphy_priv *priv, int high) +{ + int min, ret, i; + + min = high ? 1 : 0; /* low or none? */ + + for (i = 0; i < VREG_NUM; i++) { + ret = regulator_set_voltage(priv->vregs[i].consumer, + priv->voltages[i][min], + priv->voltages[i][VOL_MAX]); + if (ret) + return ret; + } + + return 0; +} + +static int qcom_snps_hsphy_enable_regulators(struct hsphy_priv *priv) +{ + int ret; + + ret = qcom_snps_hsphy_config_regulators(priv, 1); + if (ret) + return ret; + + ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000); + if (ret < 0) + goto unconfig_regulators; + + ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000); + if (ret < 0) + goto unset_1p8_load; + + ret = regulator_bulk_enable(VREG_NUM, priv->vregs); + if (ret) + goto unset_3p3_load; + + return 0; + +unset_3p3_load: + regulator_set_load(priv->vregs[VDDA_3P3].consumer, 0); +unset_1p8_load: + regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0); +unconfig_regulators: + qcom_snps_hsphy_config_regulators(priv, 0); + return ret; +} + +static void qcom_snps_hsphy_disable_regulators(struct hsphy_priv *priv) +{ + regulator_bulk_disable(VREG_NUM, priv->vregs); + regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0); + regulator_set_load(priv->vregs[VDDA_3P3].consumer, 0); + qcom_snps_hsphy_config_regulators(priv, 0); +} + +static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + priv->mode = mode; + + return 0; +} + +static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + /* Clear any existing interrupts before enabling the interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + writeb(0x1, priv->base + PHY_IRQ_CMD); + + /* Make sure the interrupts are cleared */ + usleep_range(200, 220); + + val = readb(priv->base + PHY_INTR_MASK0); + switch (priv->mode) { + case PHY_MODE_USB_HOST_HS: + case PHY_MODE_USB_HOST_FS: + case PHY_MODE_USB_DEVICE_HS: + case PHY_MODE_USB_DEVICE_FS: + val |= DP_1_0 | DM_0_1; + break; + case PHY_MODE_USB_HOST_LS: + case PHY_MODE_USB_DEVICE_LS: + val |= DP_0_1 | DM_1_0; + break; + default: + /* No device connected */ + val |= DP_0_1 | DM_0_1; + break; + } + writeb(val, priv->base + PHY_INTR_MASK0); +} + +static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_INTR_MASK0); + val &= ~DPDM_MASK; + writeb(val, priv->base + PHY_INTR_MASK0); + + /* Clear any pending interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + + writeb(0x1, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); +} + +static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val |= SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val &= ~SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static int qcom_snps_hsphy_vbus_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct hsphy_priv *priv = container_of(nb, struct hsphy_priv, + vbus_notify); + priv->cable_connected = !!event; + return 0; +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + if (priv->cable_connected) { + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return ret; + qcom_snps_hsphy_disable_hv_interrupts(priv); + } else { + ret = qcom_snps_hsphy_enable_regulators(priv); + if (ret) + return ret; + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return ret; + qcom_snps_hsphy_exit_retention(priv); + } + + return 0; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + if (priv->cable_connected) { + qcom_snps_hsphy_enable_hv_interrupts(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } else { + qcom_snps_hsphy_enter_retention(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + qcom_snps_hsphy_disable_regulators(priv); + } + + return 0; +} + +static int qcom_snps_hsphy_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(10, 15); + + ret = reset_control_deassert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(80, 100); + + return 0; +} + +static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv) +{ + struct hsphy_init_seq *seq; + + for (seq = priv->init_seq; seq->offset != -1; seq++) { + writeb(seq->val, priv->base + seq->offset); + if (seq->delay) + usleep_range(seq->delay, seq->delay + 10); + } + + /* Ensure that the above parameter overrides is successful. */ + mb(); +} + +static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->por_reset); + if (ret) + return ret; + + /* + * The Femto PHY is POR reset in the following scenarios. + * + * 1. After overriding the parameter registers. + * 2. Low power mode exit from PHY retention. + * + * Ensure that SIDDQ is cleared before bringing the PHY + * out of reset. + */ + qcom_snps_hsphy_exit_retention(priv); + + /* + * As per databook, 10 usec delay is required between + * PHY POR assert and de-assert. + */ + usleep_range(10, 20); + ret = reset_control_deassert(priv->por_reset); + if (ret) + return ret; + + /* + * As per databook, it takes 75 usec for PHY to stabilize + * after the reset. + */ + usleep_range(80, 100); + + /* Ensure that RESET operation is completed. */ + mb(); + + return 0; +} + +static int qcom_snps_hsphy_init(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int state; + int ret; + + ret = qcom_snps_hsphy_reset(priv); + if (ret) + return ret; + + qcom_snps_hsphy_init_sequence(priv); + + ret = qcom_snps_hsphy_por_reset(priv); + if (ret) + return ret; + + /* Setup initial state */ + if (priv->vbus_edev) { + state = extcon_get_state(priv->vbus_edev, EXTCON_USB); + ret = qcom_snps_hsphy_vbus_notifier(&priv->vbus_notify, state, + priv->vbus_edev); + if (ret) + return ret; + } + + return 0; +} + +static const struct phy_ops qcom_snps_hsphy_ops = { + .init = qcom_snps_hsphy_init, + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, + .set_mode = qcom_snps_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static const char * const qcom_snps_hsphy_clks[] = { + "ref", + "phy", + "sleep", +}; + +static int qcom_snps_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct hsphy_priv *priv; + struct resource *res; + struct phy *phy; + int size; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks); + priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks), + GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + + for (i = 0; i < priv->num_clks; i++) + priv->clks[i].id = qcom_snps_hsphy_clks[i]; + + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return ret; + + priv->phy_reset = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->phy_reset)) + return PTR_ERR(priv->phy_reset); + + priv->por_reset = devm_reset_control_get(dev, "por"); + if (IS_ERR(priv->por_reset)) + return PTR_ERR(priv->por_reset); + + priv->vregs[VDD].supply = "vdd"; + priv->vregs[VDDA_1P8].supply = "vdda1p8"; + priv->vregs[VDDA_3P3].supply = "vdda3p3"; + + ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs); + if (ret) + return ret; + + priv->voltages[VDDA_1P8][VOL_NONE] = 0; + priv->voltages[VDDA_1P8][VOL_MIN] = 1800000; + priv->voltages[VDDA_1P8][VOL_MAX] = 1800000; + + priv->voltages[VDDA_3P3][VOL_NONE] = 0; + priv->voltages[VDDA_3P3][VOL_MIN] = 3050000; + priv->voltages[VDDA_3P3][VOL_MAX] = 3300000; + + ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level", + priv->voltages[VDD], VOL_NUM); + if (ret) { + dev_err(dev, "failed to read qcom,vdd-voltage-level\n"); + return ret; + } + + size = of_property_count_u32_elems(dev->of_node, "qcom,init-seq"); + if (size < 0) + size = 0; + + priv->init_seq = devm_kcalloc(dev, (size / 3) + 1, + sizeof(*priv->init_seq), GFP_KERNEL); + if (!priv->init_seq) + return -ENOMEM; + + ret = of_property_read_u32_array(dev->of_node, "qcom,init-seq", + (u32 *) priv->init_seq, size); + if (ret && size) + return ret; + + /* terminator */ + priv->init_seq[size / 3].offset = -1; + + phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + priv->vbus_edev = extcon_get_edev_by_phandle(dev, 0); + if (IS_ERR(priv->vbus_edev)) { + if (PTR_ERR(priv->vbus_edev) != -ENODEV) + return PTR_ERR(priv->vbus_edev); + priv->vbus_edev = NULL; + } + + if (priv->vbus_edev) { + priv->vbus_notify.notifier_call = qcom_snps_hsphy_vbus_notifier; + ret = devm_extcon_register_notifier(dev, priv->vbus_edev, + EXTCON_USB, + &priv->vbus_notify); + if (ret) + return ret; + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_snps_hsphy_match[] = { + { .compatible = "qcom,usb-snps-hsphy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match); + +static struct platform_driver qcom_snps_hsphy_driver = { + .probe = qcom_snps_hsphy_probe, + .driver = { + .name = "qcom-usb-snps-hsphy", + .of_match_table = qcom_snps_hsphy_match, + }, +}; +module_platform_driver(qcom_snps_hsphy_driver); + +MODULE_DESCRIPTION("Qualcomm Synopsys 28nm USB High-Speed PHY driver"); +MODULE_LICENSE("GPL v2");