From patchwork Thu Dec 17 21:49:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C6AFC4361B for ; Thu, 17 Dec 2020 21:49:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 063C123A58 for ; Thu, 17 Dec 2020 21:49:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 063C123A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 29F3489A0F; Thu, 17 Dec 2020 21:49:33 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBADA89A0F for ; Thu, 17 Dec 2020 21:49:31 +0000 (UTC) IronPort-SDR: 8N2QgALWVY3PJTEQb/4Na4hztvtXbXyWQKwMx6EDzCfnFgk5N9b+9sdfUpkgDHcxUhoSZd/GVk V0dLBpyfIp8g== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906266" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906266" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: w+2O0McqfjWxWhlWThSaLacp7a9iruDgfSmqjU1QKjg9QxRFvIpw49Opiz75LYHZp1XeE79i/2 Hb8j+mg/HJDg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780450" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:19 -0800 Message-Id: <20201217214931.13340-2-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 01/13] drm/i915/pxp: Introduce Intel PXP component X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" PXP (Protected Xe Path) is an i915 componment, available on GEN12+, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a default session or arbitrary session). So Mesa can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Kconfig | 22 +++++++++++++++++ drivers/gpu/drm/i915/Makefile | 5 ++++ drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 24 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 ++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 ++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 21 ++++++++++++++++ 9 files changed, 144 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 1e1cb245fca7..594775c11e19 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT Choose this option if you want to enable KVMGT support for Intel GVT-g. +config DRM_I915_PXP + bool "Enable Intel PXP support for Intel Gen12+ platform" + depends on DRM_I915 + select INTEL_MEI + select INTEL_MEI_ME + select INTEL_MEI_TXE + select INTEL_MEI_PXP + default y + help + This option selects INTEL_MEI_ME if it isn't already selected to + enabled full PXP Services on Intel platforms. + + PXP (Protected Xe Path) is an i915 componment, available on GEN12+, + that helps to establish the hardware protected session and manage + the status of the alive software session, as well as its life cycle. + + This patch series is to allow the kernel space to create and + manage a single hardware session (a.k.a default session or + arbitrary session). So Mesa can allocate the protected buffer, + which is encrypted with the leverage of the arbitrary hardware + session. + menu "drm/i915 Debugging" depends on DRM_I915 depends on EXPERT diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f9ef5199b124..53be29dbc07d 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -255,6 +255,11 @@ i915-y += \ i915-y += i915_perf.o +# Protected execution platform (PXP) support +i915-$(CONFIG_DRM_I915_PXP) += \ + pxp/intel_pxp.o \ + pxp/intel_pxp_context.o + # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o i915-$(CONFIG_DRM_I915_SELFTEST) += \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 44f1d51e5ae5..d2448be36ded 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -18,6 +18,7 @@ #include "intel_uncore.h" #include "intel_pm.h" #include "shmem_utils.h" +#include "pxp/intel_pxp.h" void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) { @@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt) if (err) goto err_gt; + intel_pxp_init(>->pxp); + goto out_fw; err_gt: __intel_gt_disable(gt); @@ -638,6 +641,7 @@ void intel_gt_driver_release(struct intel_gt *gt) if (vm) /* FIXME being called twice on error paths :( */ i915_vm_put(vm); + intel_pxp_fini(>->pxp); intel_gt_pm_fini(gt); intel_gt_fini_scratch(gt); intel_gt_fini_buffer_pool(gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 6d39a4a11bf3..caa3e1403945 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -23,6 +23,7 @@ #include "intel_rc6_types.h" #include "intel_rps_types.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_types.h" struct drm_i915_private; struct i915_ggtt; @@ -120,6 +121,8 @@ struct intel_gt { /* Slice/subslice/EU info */ struct sseu_dev_info sseu; } info; + + struct intel_pxp pxp; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c new file mode 100644 index 000000000000..1e757efb7f5f --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ +#include "i915_drv.h" +#include "intel_pxp.h" +#include "intel_pxp_context.h" + +void intel_pxp_init(struct intel_pxp *pxp) +{ + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + + if (INTEL_GEN(gt->i915) < 12) + return; + + intel_pxp_ctx_init(&pxp->ctx); + + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); +} + +void intel_pxp_fini(struct intel_pxp *pxp) +{ + intel_pxp_ctx_fini(&pxp->ctx); +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h new file mode 100644 index 000000000000..f47bc6bea34f --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_H__ +#define __INTEL_PXP_H__ + +#include "intel_pxp_types.h" + +#ifdef CONFIG_DRM_I915_PXP +void intel_pxp_init(struct intel_pxp *pxp); +void intel_pxp_fini(struct intel_pxp *pxp); +#else +static inline void intel_pxp_init(struct intel_pxp *pxp) +{ + return 0; +} + +static inline void intel_pxp_fini(struct intel_pxp *pxp) +{ +} +#endif + +#endif /* __INTEL_PXP_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c new file mode 100644 index 000000000000..2be6bf2f0d0f --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "intel_pxp_context.h" + +/** + * intel_pxp_ctx_init - To init a pxp context. + * @ctx: pointer to ctx structure. + */ +void intel_pxp_ctx_init(struct pxp_context *ctx) +{ + mutex_init(&ctx->mutex); + ctx->inited = true; +} + +/** + * intel_pxp_ctx_fini - To finish the pxp context. + * @ctx: pointer to ctx structure. + */ +void intel_pxp_ctx_fini(struct pxp_context *ctx) +{ + ctx->inited = false; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h new file mode 100644 index 000000000000..f51021c33d45 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_CONTEXT_H__ +#define __INTEL_PXP_CONTEXT_H__ + +#include +#include "intel_pxp_types.h" + +void intel_pxp_ctx_init(struct pxp_context *ctx); +void intel_pxp_ctx_fini(struct pxp_context *ctx); + +#endif /* __INTEL_PXP_CONTEXT_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h new file mode 100644 index 000000000000..d12d9e372b48 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_TYPES_H__ +#define __INTEL_PXP_TYPES_H__ + +/* struct pxp_context - Represents combined view of driver and logical HW states. */ +struct pxp_context { + /** @mutex: mutex to protect the pxp context */ + struct mutex mutex; + + bool inited; +}; + +struct intel_pxp { + struct pxp_context ctx; +}; + +#endif /* __INTEL_PXP_TYPES_H__ */ From patchwork Thu Dec 17 21:49:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AB1FC2BBD4 for ; Thu, 17 Dec 2020 21:49:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6C7FF23A57 for ; Thu, 17 Dec 2020 21:49:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6C7FF23A57 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 53422895CA; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 310D589A16 for ; Thu, 17 Dec 2020 21:49:32 +0000 (UTC) IronPort-SDR: NYCu5qQFu9CwTfwnbFWt3NAesiqOFyQINo5tPzH8E/IX8SUKQUGiji5FikQ0pvR83LIxxfS2ro E6vUXgQc+7eQ== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906268" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906268" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: LipMrTvcFJcPIrM1iqcgCQ/b637BWv/WxicECfD01ACj/B5+3H2u59Mu+czS4LfdzJYrafJrRu f0YAwr3xPdwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780451" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:20 -0800 Message-Id: <20201217214931.13340-3-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 02/13] drm/i915/pxp: set KCR reg init during the boot time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set the KCR init during the boot time, which is required by hardware, to allow us doing further protection operation such as sending commands to GPU or TEE. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 1e757efb7f5f..cf22006222ce 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -6,6 +6,12 @@ #include "intel_pxp.h" #include "intel_pxp_context.h" +/* KCR register definitions */ +#define KCR_INIT _MMIO(0x320f0) +#define KCR_INIT_MASK_SHIFT (16) +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT)) + void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); @@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp) intel_pxp_ctx_init(&pxp->ctx); + intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); } From patchwork Thu Dec 17 21:49:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1113BC4361B for ; Thu, 17 Dec 2020 21:49:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF07C23A58 for ; Thu, 17 Dec 2020 21:49:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CF07C23A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D009689A4F; Thu, 17 Dec 2020 21:49:37 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 40C3289A16 for ; Thu, 17 Dec 2020 21:49:33 +0000 (UTC) IronPort-SDR: 9fPD6IpNQsEvM2OutZWWTokQNnX+va2oFIgNHaEPUg7j3Mu1xDy3/BNNawh4UE6nmd0pngfdw7 tlm1Y2Zk79SQ== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906270" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906270" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: t66bz5gsnFrfDRXRqexIDcuk7oIpKzn/9HaKifZ/ocdNrP/l7HxSmE/On88+XS2wiNmR9GSEs0 ty+D0gUKTbXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780452" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:21 -0800 Message-Id: <20201217214931.13340-4-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC-v11 03/13] drm/i915/pxp: Implement funcs to create the TEE channel X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement the funcs to create the TEE channel, so kernel can send the TEE commands directly to TEE for creating the arbitrary (defualt) session. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 ++++++++ 8 files changed, 206 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h create mode 100644 include/drm/i915_pxp_tee_interface.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 53be29dbc07d..57447887d352 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -258,7 +258,8 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ - pxp/intel_pxp_context.o + pxp/intel_pxp_context.o \ + pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5708e11d917b..9299a456adb0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) mutex_init(&dev_priv->wm.wm_mutex); mutex_init(&dev_priv->pps_mutex); mutex_init(&dev_priv->hdcp_comp_mutex); + mutex_init(&dev_priv->pxp_tee_comp_mutex); i915_memcpy_init_early(dev_priv); intel_runtime_pm_init_early(&dev_priv->runtime_pm); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c2d0156e8a5d..aaf452115c2f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1212,6 +1212,12 @@ struct drm_i915_private { /* Mutex to protect the above hdcp component related values. */ struct mutex hdcp_comp_mutex; + struct i915_pxp_comp_master *pxp_tee_master; + bool pxp_tee_comp_added; + + /* Mutex to protect the above pxp_tee component related values. */ + struct mutex pxp_tee_comp_mutex; + I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) /* diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index cf22006222ce..5a3461272fe9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "intel_pxp.h" #include "intel_pxp_context.h" +#include "intel_pxp_tee.h" /* KCR register definitions */ #define KCR_INIT _MMIO(0x320f0) @@ -23,10 +24,14 @@ void intel_pxp_init(struct intel_pxp *pxp) intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + intel_pxp_tee_component_init(pxp); + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); } void intel_pxp_fini(struct intel_pxp *pxp) { + intel_pxp_tee_component_fini(pxp); + intel_pxp_ctx_fini(&pxp->ctx); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c new file mode 100644 index 000000000000..ca6b61099aee --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include +#include "drm/i915_pxp_tee_interface.h" +#include "drm/i915_component.h" +#include "i915_drv.h" +#include "intel_pxp.h" +#include "intel_pxp_context.h" +#include "intel_pxp_tee.h" + +static int intel_pxp_tee_io_message(struct intel_pxp *pxp, + void *msg_in, u32 msg_in_size, + void *msg_out, u32 *msg_out_size_ptr, + u32 msg_out_buf_size) +{ + int ret; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + struct drm_i915_private *i915 = gt->i915; + struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master; + + if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr) + return -EINVAL; + + lockdep_assert_held(&i915->pxp_tee_comp_mutex); + + if (drm_debug_enabled(DRM_UT_DRIVER)) + print_hex_dump(KERN_DEBUG, "TEE input message binaries:", + DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true); + + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size); + if (ret) { + drm_err(&i915->drm, "Failed to send TEE message\n"); + return -EFAULT; + } + + ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size); + if (ret < 0) { + drm_err(&i915->drm, "Failed to receive TEE message\n"); + return -EFAULT; + } + + if (ret > msg_out_buf_size) { + drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n"); + return -EFAULT; + } + + *msg_out_size_ptr = ret; + ret = 0; + + if (drm_debug_enabled(DRM_UT_DRIVER)) + print_hex_dump(KERN_DEBUG, "TEE output message binaries:", + DUMP_PREFIX_OFFSET, 4, 4, msg_out, *msg_out_size_ptr, true); + + return ret; +} + +/** + * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee + * @i915_kdev: pointer to i915 kernel device + * @tee_kdev: pointer to tee kernel device + * @data: pointer to pxp_tee_master containing the function pointers + * + * This bind function is called during the system boot or resume from system sleep. + * + * Return: return 0 if successful. + */ +static int i915_pxp_tee_component_bind(struct device *i915_kdev, + struct device *tee_kdev, void *data) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + + if (!i915 || !tee_kdev || !data) + return -EPERM; + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_master = (struct i915_pxp_comp_master *)data; + i915->pxp_tee_master->tee_dev = tee_kdev; + mutex_unlock(&i915->pxp_tee_comp_mutex); + + return 0; +} + +static void i915_pxp_tee_component_unbind(struct device *i915_kdev, + struct device *tee_kdev, void *data) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + + if (!i915 || !tee_kdev || !data) + return; + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_master = NULL; + mutex_unlock(&i915->pxp_tee_comp_mutex); +} + +static const struct component_ops i915_pxp_tee_component_ops = { + .bind = i915_pxp_tee_component_bind, + .unbind = i915_pxp_tee_component_unbind, +}; + +void intel_pxp_tee_component_init(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + struct drm_i915_private *i915 = gt->i915; + + ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops, + I915_COMPONENT_PXP); + if (ret < 0) { + drm_err(&i915->drm, "Failed at component add(%d)\n", ret); + return; + } + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_comp_added = true; + mutex_unlock(&i915->pxp_tee_comp_mutex); +} + +void intel_pxp_tee_component_fini(struct intel_pxp *pxp) +{ + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + struct drm_i915_private *i915 = gt->i915; + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_comp_added = false; + mutex_unlock(&i915->pxp_tee_comp_mutex); + + component_del(i915->drm.dev, &i915_pxp_tee_component_ops); +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h new file mode 100644 index 000000000000..4b5e3edb1d9b --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_TEE_H__ +#define __INTEL_PXP_TEE_H__ + +#include "intel_pxp.h" + +void intel_pxp_tee_component_init(struct intel_pxp *pxp); +void intel_pxp_tee_component_fini(struct intel_pxp *pxp); + +#endif /* __INTEL_PXP_TEE_H__ */ diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h index 55c3b123581b..c1e2a43d2d1e 100644 --- a/include/drm/i915_component.h +++ b/include/drm/i915_component.h @@ -29,6 +29,7 @@ enum i915_component_type { I915_COMPONENT_AUDIO = 1, I915_COMPONENT_HDCP, + I915_COMPONENT_PXP }; /* MAX_PORT is the number of port diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h new file mode 100644 index 000000000000..3999e255e145 --- /dev/null +++ b/include/drm/i915_pxp_tee_interface.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + * + * Authors: + * Vitaly Lubart + */ + +#ifndef _I915_PXP_TEE_INTERFACE_H_ +#define _I915_PXP_TEE_INTERFACE_H_ + +#include +#include + +/** + * struct i915_pxp_component_ops - ops for PXP services. + * @owner: Module providing the ops + * @send: sends data to PXP + * @receive: receives data from PXP + */ +struct i915_pxp_component_ops { + /** + * @owner: owner of the module provding the ops + */ + struct module *owner; + + int (*send)(struct device *dev, const void *message, size_t size); + int (*receive)(struct device *dev, void *buffer, size_t size); +}; + +/** + * struct i915_pxp_component_master - Used for communication between i915 + * and TEE drivers for the PXP services + * @tee_dev: device that provide the PXP service from TEE Bus. + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver. + */ +struct i915_pxp_comp_master { + struct device *tee_dev; + const struct i915_pxp_component_ops *ops; + + /* To protect the above members. */ + struct mutex mutex; +}; + +#endif /* _I915_TEE_PXP_INTERFACE_H_ */ From patchwork Thu Dec 17 21:49:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F788C2BBCD for ; Thu, 17 Dec 2020 21:49:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E553523A58 for ; Thu, 17 Dec 2020 21:49:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E553523A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ABC1489A4E; Thu, 17 Dec 2020 21:49:37 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 83F5889A16 for ; Thu, 17 Dec 2020 21:49:34 +0000 (UTC) IronPort-SDR: quRMs+L33EoIcDmgLQpx6t4RdYQnhZLWYJ8mZ0xC4a0QFUHNWVlj+pQPNj3GUl1RU5fCm7lyYR O77xQSinH67Q== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906271" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906271" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: sILGNYoE7I12a5Kf+CXzlZ75hQ2+bhfYzwphbS3bQjSVLt7j535IH8SWl31CroUmFZLpu7oUQY kqHm66nV80Nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780453" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:22 -0800 Message-Id: <20201217214931.13340-5-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 04/13] drm/i915/pxp: Create the arbitrary session after boot X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Create the arbitrary session, with the fixed session id 0xf, after system boot, for the case that application allocates the protected buffer without establishing any protection session. Because the hardware requires at least one alive session for protected buffer creation. This arbitrary session needs to be re-created after teardown or power event because hardware encryption key won't be valid after such cases. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++ drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 133 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 15 +++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 38 ++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 + drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26 ++++ 9 files changed, 237 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 57447887d352..2c84f75b41da 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -258,6 +258,7 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ + pxp/intel_pxp_arb.o \ pxp/intel_pxp_context.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 5a3461272fe9..2203464c76bc 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -6,6 +6,7 @@ #include "intel_pxp.h" #include "intel_pxp_context.h" #include "intel_pxp_tee.h" +#include "intel_pxp_arb.h" /* KCR register definitions */ #define KCR_INIT _MMIO(0x320f0) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index f47bc6bea34f..8fc91e900b16 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -8,6 +8,22 @@ #include "intel_pxp_types.h" +enum pxp_session_types { + SESSION_TYPE_TYPE0 = 0, + SESSION_TYPE_TYPE1 = 1, + + SESSION_TYPE_MAX +}; + +enum pxp_protection_modes { + PROTECTION_MODE_NONE = 0, + PROTECTION_MODE_LM = 2, + PROTECTION_MODE_HM = 3, + PROTECTION_MODE_SM = 6, + + PROTECTION_MODE_ALL +}; + #ifdef CONFIG_DRM_I915_PXP void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c new file mode 100644 index 000000000000..d3da72969349 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "gt/intel_context.h" +#include "gt/intel_engine_pm.h" + +#include "intel_pxp_types.h" +#include "intel_pxp_arb.h" +#include "intel_pxp.h" +#include "intel_pxp_tee.h" + +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */ + +/* Arbitrary session */ +#define ARB_SESSION_INDEX 0xf +#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0 +#define ARB_PROTECTION_MODE PROTECTION_MODE_HM + +static bool is_hw_arb_session_in_play(struct intel_pxp *pxp) +{ + u32 regval_sip = 0; + intel_wakeref_t wakeref; + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) { + regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP); + } + + return regval_sip & BIT(ARB_SESSION_INDEX); +} + +/* wait hw session_in_play reg to match the current sw state */ +static int wait_arb_hw_sw_state(struct intel_pxp *pxp) +{ + const int max_retry = 10; + const int ms_delay = 10; + int retry = 0; + int ret; + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + ret = -EINVAL; + for (retry = 0; retry < max_retry; retry++) { + if (is_hw_arb_session_in_play(pxp) == + arb->is_in_play) { + ret = 0; + break; + } + + msleep(ms_delay); + } + + return ret; +} + +static void arb_session_entry_init(struct intel_pxp *pxp) +{ + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + arb->type = ARB_SESSION_TYPE; + arb->protection_mode = ARB_PROTECTION_MODE; + arb->index = ARB_SESSION_INDEX; + arb->is_in_play = false; +} + +int intel_pxp_arb_reserve_session(struct intel_pxp *pxp) +{ + int ret; + + lockdep_assert_held(&pxp->ctx.mutex); + + arb_session_entry_init(pxp); + ret = wait_arb_hw_sw_state(pxp); + + return ret; +} + +/** + * intel_pxp_arb_mark_session_in_play - To put an reserved protected session to "in_play" state + * @pxp: pointer to pxp struct. + * + * Return: status. 0 means update is successful. + */ +static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp) +{ + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + lockdep_assert_held(&pxp->ctx.mutex); + + if (arb->is_in_play) + return -EINVAL; + + arb->is_in_play = true; + return 0; +} + +int intel_pxp_arb_create_session(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + lockdep_assert_held(&pxp->ctx.mutex); + + if (pxp->ctx.flag_display_hm_surface_keys) { + drm_err(>->i915->drm, "%s: arb session is alive so skipping the creation\n", + __func__); + return 0; + } + + ret = intel_pxp_arb_reserve_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to reserve arb session\n"); + goto end; + } + + ret = intel_pxp_tee_cmd_create_arb_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to send tee cmd for arb session creation\n"); + goto end; + } + + ret = intel_pxp_arb_mark_session_in_play(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to mark arb session status in play\n"); + goto end; + } + + pxp->ctx.flag_display_hm_surface_keys = true; + +end: + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h new file mode 100644 index 000000000000..1eb8db6deb0e --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_ARB_H__ +#define __INTEL_PXP_ARB_H__ + +#include + +struct intel_pxp; + +int intel_pxp_arb_create_session(struct intel_pxp *pxp); + +#endif /* __INTEL_PXP_ARB_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h index f51021c33d45..bf2feb4aaf6d 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h @@ -8,6 +8,7 @@ #include #include "intel_pxp_types.h" +#include "intel_pxp_arb.h" void intel_pxp_ctx_init(struct pxp_context *ctx); void intel_pxp_ctx_fini(struct pxp_context *ctx); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index ca6b61099aee..816a6d5a54e4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -10,6 +10,7 @@ #include "intel_pxp.h" #include "intel_pxp_context.h" #include "intel_pxp_tee.h" +#include "intel_pxp_arb.h" static int intel_pxp_tee_io_message(struct intel_pxp *pxp, void *msg_in, u32 msg_in_size, @@ -70,7 +71,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp, static int i915_pxp_tee_component_bind(struct device *i915_kdev, struct device *tee_kdev, void *data) { + int ret; struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_pxp *pxp = &i915->gt.pxp; if (!i915 || !tee_kdev || !data) return -EPERM; @@ -80,6 +83,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, i915->pxp_tee_master->tee_dev = tee_kdev; mutex_unlock(&i915->pxp_tee_comp_mutex); + mutex_lock(&pxp->ctx.mutex); + /* Create arb session only if tee is ready, during system boot or sleep/resume */ + ret = intel_pxp_arb_create_session(pxp); + mutex_unlock(&pxp->ctx.mutex); + + if (ret) { + drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret); + return ret; + } + return 0; } @@ -130,3 +143,28 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp) component_del(i915->drm.dev, &i915_pxp_tee_component_ops); } + +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp) +{ + int ret; + u32 msg_out_size_received = 0; + u32 msg_in[PXP_TEE_ARB_CMD_DW_LEN] = PXP_TEE_ARB_CMD_BIN; + u32 msg_out[PXP_TEE_ARB_CMD_DW_LEN] = {0}; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + struct drm_i915_private *i915 = gt->i915; + + mutex_lock(&i915->pxp_tee_comp_mutex); + + ret = intel_pxp_tee_io_message(pxp, + &msg_in, + sizeof(msg_in), + &msg_out, &msg_out_size_received, + sizeof(msg_out)); + + mutex_unlock(&i915->pxp_tee_comp_mutex); + + if (ret) + drm_err(&i915->drm, "Failed to send/receive tee message\n"); + + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h index 4b5e3edb1d9b..757a54208a4d 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -11,4 +11,10 @@ void intel_pxp_tee_component_init(struct intel_pxp *pxp); void intel_pxp_tee_component_fini(struct intel_pxp *pxp); +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp); + +/* TEE command to create the arbitrary session */ +#define PXP_TEE_ARB_CMD_BIN {0x00040000, 0x0000001e, 0x00000000, 0x00000008, 0x00000002, 0x0000000f} +#define PXP_TEE_ARB_CMD_DW_LEN (6) + #endif /* __INTEL_PXP_TEE_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index d12d9e372b48..a8985d91cfef 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -6,12 +6,38 @@ #ifndef __INTEL_PXP_TYPES_H__ #define __INTEL_PXP_TYPES_H__ +/** + * struct pxp_protected_session - structure to track all active sessions. + */ +struct pxp_protected_session { + /** @index: Numeric identifier for this protected session */ + int index; + /** @type: Type of session */ + int type; + /** @protection_mode: mode of protection requested */ + int protection_mode; + + /** + * @is_in_play: indicates whether the session has been established + * in the HW root of trust if this flag is false, it + * indicates an application has reserved this session, + * but has not * established the session in the + * hardware yet. + */ + bool is_in_play; +}; + /* struct pxp_context - Represents combined view of driver and logical HW states. */ struct pxp_context { /** @mutex: mutex to protect the pxp context */ struct mutex mutex; bool inited; + + struct pxp_protected_session arb_session; + u32 arb_session_pxp_tag; + + bool flag_display_hm_surface_keys; }; struct intel_pxp { From patchwork Thu Dec 17 21:49:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71846C4361B for ; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34FF923A58 for ; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 34FF923A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F2A78938F; Thu, 17 Dec 2020 21:49:45 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 060E289A1F for ; Thu, 17 Dec 2020 21:49:34 +0000 (UTC) IronPort-SDR: 4IaIYSGAaOo74+XbJebR2q/0OzzrEtl/4AOVV1gpehzRZIVhlWjjXPGerxJ06O+OdD354YNSAg SZDvlWY4Dkjg== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906272" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906272" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: 0g4tJAnJJApchSOlHJWG74L0/j7m92iZh3IUbEFZ5oWt55eqY7HSUtWQHxAw2Raa/5Ckwbeec9 2PwBvpxCFFfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780456" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:23 -0800 Message-Id: <20201217214931.13340-6-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 05/13] drm/i915/pxp: Func to send hardware session termination X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement the functions to allow PXP to send a GPU command, in order to terminate the hardware session, so hardware can recycle this session slot for the next usage. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 159 +++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++ 3 files changed, 178 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 2c84f75b41da..abe52189986a 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -259,6 +259,7 @@ i915-y += i915_perf.o i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ pxp/intel_pxp_arb.o \ + pxp/intel_pxp_cmd.o \ pxp/intel_pxp_context.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c new file mode 100644 index 000000000000..e86d914e7629 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "intel_pxp_cmd.h" +#include "i915_drv.h" +#include "gt/intel_context.h" +#include "gt/intel_engine_pm.h" + +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, + struct intel_context *ce, + struct intel_gt_buffer_pool_node *pool, + u32 *cmd_buf, int cmd_size_in_dw) +{ + struct i915_vma *batch = ERR_PTR(-EINVAL); + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + u32 *cmd; + + if (!ce || !ce->engine || !cmd_buf) + return ERR_PTR(-EINVAL); + + if (cmd_size_in_dw * 4 > PAGE_SIZE) { + drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n", + __func__, cmd_size_in_dw); + return ERR_PTR(-EINVAL); + } + + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC); + if (IS_ERR(cmd)) { + drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n"); + return ERR_PTR(-EINVAL); + } + + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4); + + if (drm_debug_enabled(DRM_UT_DRIVER)) { + print_hex_dump(KERN_DEBUG, "cmd binaries:", + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true); + } + + i915_gem_object_unpin_map(pool->obj); + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + drm_err(>->i915->drm, "Failed to i915_vma_instance()\n"); + return batch; + } + + return batch; +} + +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw) +{ + int err = -EINVAL; + struct i915_vma *batch; + struct i915_request *rq; + struct intel_context *ce = NULL; + bool is_engine_pm_get = false; + bool is_batch_vma_pin = false; + bool is_skip_req_on_err = false; + bool is_engine_get_pool = false; + struct intel_gt_buffer_pool_node *pool = NULL; + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + + if (!HAS_ENGINE(gt, VCS0) || + !gt->engine[VCS0]->kernel_context) { + err = -EINVAL; + goto end; + } + + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) { + drm_err(>->i915->drm, "Failed to %s bad params\n", __func__); + return -EINVAL; + } + + ce = gt->engine[VCS0]->kernel_context; + + intel_engine_pm_get(ce->engine); + is_engine_pm_get = true; + + pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE); + if (IS_ERR(pool)) { + drm_err(>->i915->drm, "Failed to intel_engine_get_pool()\n"); + err = PTR_ERR(pool); + goto end; + } + is_engine_get_pool = true; + + batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw); + if (IS_ERR(batch)) { + drm_err(>->i915->drm, "Failed to intel_pxp_cmd_get_batch()\n"); + err = PTR_ERR(batch); + goto end; + } + + err = i915_vma_pin(batch, 0, 0, PIN_USER); + if (err) { + drm_err(>->i915->drm, "Failed to i915_vma_pin()\n"); + goto end; + } + is_batch_vma_pin = true; + + rq = intel_context_create_request(ce); + if (IS_ERR(rq)) { + drm_err(>->i915->drm, "Failed to intel_context_create_request()\n"); + err = PTR_ERR(rq); + goto end; + } + is_skip_req_on_err = true; + + err = intel_gt_buffer_pool_mark_active(pool, rq); + if (err) { + drm_err(>->i915->drm, "Failed to intel_engine_pool_mark_active()\n"); + goto end; + } + + i915_vma_lock(batch); + err = i915_request_await_object(rq, batch->obj, false); + if (!err) + err = i915_vma_move_to_active(batch, rq, 0); + i915_vma_unlock(batch); + if (err) { + drm_err(>->i915->drm, "Failed to i915_request_await_object()\n"); + goto end; + } + + if (ce->engine->emit_init_breadcrumb) { + err = ce->engine->emit_init_breadcrumb(rq); + if (err) { + drm_err(>->i915->drm, "Failed to emit_init_breadcrumb()\n"); + goto end; + } + } + + err = ce->engine->emit_bb_start(rq, batch->node.start, + batch->node.size, 0); + if (err) { + drm_err(>->i915->drm, "Failed to emit_bb_start()\n"); + goto end; + } + + i915_request_add(rq); + +end: + if (unlikely(err) && is_skip_req_on_err) + i915_request_set_error_once(rq, err); + + if (is_batch_vma_pin) + i915_vma_unpin(batch); + + if (is_engine_get_pool) + intel_gt_buffer_pool_put(pool); + + if (is_engine_pm_get) + intel_engine_pm_put(ce->engine); + + return err; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h new file mode 100644 index 000000000000..d04463962421 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_CMD_H__ +#define __INTEL_PXP_CMD_H__ + +#include "gt/intel_gt_buffer_pool.h" +#include "intel_pxp.h" + +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, + struct intel_context *ce, + struct intel_gt_buffer_pool_node *pool, + u32 *cmd_buf, int cmd_size_in_dw); + +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw); +#endif /* __INTEL_PXP_SM_H__ */ From patchwork Thu Dec 17 21:49:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA70FC2BBCF for ; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 99F2B23A58 for ; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 99F2B23A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A0BE9894C3; Thu, 17 Dec 2020 21:49:45 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 30C5489A32 for ; Thu, 17 Dec 2020 21:49:35 +0000 (UTC) IronPort-SDR: 6sXh5UJDXWQePi0T3u4K25YXnNcru7kqtZtpci7lZY4sSMXuXdXxem62lgTIZoS9725hLOqdrJ 8cCelqoFFVOw== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906273" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906273" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: 03eMo/YKF5qRzr5FHYmwTILH0p8ZTxwtd6KYWnyeSaLP0UNco3t2R3IkLtKplhInzF2N/6vvRz nUDCng2M0HSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780459" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:24 -0800 Message-Id: <20201217214931.13340-7-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Create the irq worker that serves as callback handler, those callback stubs should be called while the hardware key teardown occurs. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 + drivers/gpu/drm/i915/i915_reg.h | 3 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 ++++- drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 - drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 7 ++ 7 files changed, 140 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 9830342aa6f4..b92072554ab3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -14,6 +14,7 @@ #include "intel_lrc_reg.h" #include "intel_uncore.h" #include "intel_rps.h" +#include "pxp/intel_pxp.h" static void guc_irq_handler(struct intel_guc *guc, u16 iir) { @@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, if (instance == OTHER_GTPM_INSTANCE) return gen11_rps_irq_handler(>->rps, iir); + if (instance == OTHER_KCR_INSTANCE) + return intel_pxp_irq_handler(>->pxp, iir); + WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", instance, iir); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0023c023f472..1e8dfe435ca8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7944,6 +7944,7 @@ enum { /* irq instances for OTHER_CLASS */ #define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE 1 +#define OTHER_KCR_INSTANCE 4 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) @@ -7966,7 +7967,7 @@ enum { #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) -#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) #define ENGINE1_MASK REG_GENMASK(31, 16) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 2203464c76bc..f1bcfdc716ec 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -14,6 +14,70 @@ /* Setting KCR Init bit is required after system boot */ #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT)) +static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask) +{ + lockdep_assert_held(>->irq_lock); + + intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16); +} + +static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp) +{ + int ret; + + mutex_lock(&pxp->ctx.mutex); + + pxp->ctx.global_state_attacked = true; + + mutex_unlock(&pxp->ctx.mutex); + + return ret; +} + +static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp) +{ + int ret = 0; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + mutex_lock(&pxp->ctx.mutex); + + if (pxp->ctx.global_state_attacked) { + pxp->ctx.global_state_attacked = false; + + /* Re-create the arb session after teardown handle complete */ + ret = intel_pxp_arb_create_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to create arb session\n"); + goto end; + } + } +end: + mutex_unlock(&pxp->ctx.mutex); + return ret; +} + +static void intel_pxp_irq_work(struct work_struct *work) +{ + struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work); + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + u32 events = 0; + + spin_lock_irq(>->irq_lock); + events = fetch_and_zero(&pxp->current_events); + spin_unlock_irq(>->irq_lock); + + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED || + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ) + intel_pxp_teardown_required_callback(pxp); + + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE) + intel_pxp_global_terminate_complete_callback(pxp); + + spin_lock_irq(>->irq_lock); + intel_pxp_write_irq_mask_reg(gt, 0); + spin_unlock_irq(>->irq_lock); +} + void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); @@ -27,6 +91,12 @@ void intel_pxp_init(struct intel_pxp *pxp) intel_pxp_tee_component_init(pxp); + INIT_WORK(&pxp->irq_work, intel_pxp_irq_work); + + pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED | + PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ | + PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE); + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); } @@ -36,3 +106,34 @@ void intel_pxp_fini(struct intel_pxp *pxp) intel_pxp_ctx_fini(&pxp->ctx); } + +/** + * intel_pxp_irq_handler - Proxies KCR interrupts to PXP. + * @pxp: pointer to pxp struct + * @iir: GT interrupt vector associated with the interrupt + * + * Dispatches each vector element into an IRQ to PXP. + */ +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) +{ + struct drm_i915_private *i915; + const u32 events = iir & pxp->handled_irr; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + if (!gt || !gt->i915 || INTEL_GEN(i915) < 12) + return; + + i915 = gt->i915; + + lockdep_assert_held(>->irq_lock); + + if (unlikely(!events)) { + drm_err(&i915->drm, "%s returned due to iir=[0x%04x]\n", __func__, iir); + return; + } + + intel_pxp_write_irq_mask_reg(gt, pxp->handled_irr); + + pxp->current_events |= events; + schedule_work(&pxp->irq_work); +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 8fc91e900b16..cdaa6ce6fdca 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -6,8 +6,13 @@ #ifndef __INTEL_PXP_H__ #define __INTEL_PXP_H__ +#include #include "intel_pxp_types.h" +#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1) +#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2) +#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3) + enum pxp_session_types { SESSION_TYPE_TYPE0 = 0, SESSION_TYPE_TYPE1 = 1, @@ -25,14 +30,31 @@ enum pxp_protection_modes { }; #ifdef CONFIG_DRM_I915_PXP +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); +int i915_pxp_teardown_required_callback(struct intel_pxp *pxp); +int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp); + void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); #else -static inline void intel_pxp_init(struct intel_pxp *pxp) +static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) +{ +} + +static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp) +{ + return 0; +} + +static inline int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp) { return 0; } +static inline void intel_pxp_init(struct intel_pxp *pxp) +{ +} + static inline void intel_pxp_fini(struct intel_pxp *pxp) { } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c index 2be6bf2f0d0f..4e820258b7ae 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c @@ -11,7 +11,10 @@ */ void intel_pxp_ctx_init(struct pxp_context *ctx) { + ctx->global_state_attacked = false; + mutex_init(&ctx->mutex); + ctx->inited = true; } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h index bf2feb4aaf6d..f51021c33d45 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h @@ -8,7 +8,6 @@ #include #include "intel_pxp_types.h" -#include "intel_pxp_arb.h" void intel_pxp_ctx_init(struct pxp_context *ctx); void intel_pxp_ctx_fini(struct pxp_context *ctx); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index a8985d91cfef..ac0eb9346781 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -6,6 +6,8 @@ #ifndef __INTEL_PXP_TYPES_H__ #define __INTEL_PXP_TYPES_H__ +#include + /** * struct pxp_protected_session - structure to track all active sessions. */ @@ -38,9 +40,14 @@ struct pxp_context { u32 arb_session_pxp_tag; bool flag_display_hm_surface_keys; + bool global_state_attacked; }; struct intel_pxp { + struct work_struct irq_work; + u32 handled_irr; + u32 current_events; + struct pxp_context ctx; }; From patchwork Thu Dec 17 21:49:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7F32C4361B for ; Thu, 17 Dec 2020 21:49:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB16B23A57 for ; Thu, 17 Dec 2020 21:49:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB16B23A57 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0376F894D7; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E6B089A35 for ; Thu, 17 Dec 2020 21:49:35 +0000 (UTC) IronPort-SDR: a1A0ATvVuioeH8XTkGA8BnvqkZqJmUhYPeCYEtsppJgD5Ep8qqkV0mbMnhz6CBJ0WXkZXIpZzx PNckBt5jNYjw== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906274" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906274" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:31 -0800 IronPort-SDR: PxOLYoixoRLFhni1p4qKJw4E+d8SPNQ8CtgPMwC4bxV742MSAaZ9y9cL23uzGoEYm1PMQHVkIs mxXBkSuw62ow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780460" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:25 -0800 Message-Id: <20201217214931.13340-8-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 07/13] drm/i915/pxp: Destroy arb session upon teardown X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Teardown is triggered when the display topology changes and no long meets the secure playback requirement, and hardware trashes all the encryption keys for display. So as a result, PXP should handle such case and terminate the type0 sessions, which including arb session Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 130 ++++++++++++++++++++++- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++- 5 files changed, 212 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index f1bcfdc716ec..884e9c367911 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp) mutex_lock(&pxp->ctx.mutex); pxp->ctx.global_state_attacked = true; + pxp->ctx.flag_display_hm_surface_keys = false; + + ret = intel_pxp_arb_terminate_session(pxp); mutex_unlock(&pxp->ctx.mutex); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c index d3da72969349..54a5d7c26e4b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c @@ -10,6 +10,7 @@ #include "intel_pxp_arb.h" #include "intel_pxp.h" #include "intel_pxp_tee.h" +#include "intel_pxp_cmd.h" #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */ @@ -131,3 +132,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp) end: return ret; } + +static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp) +{ + u32 *cmd = NULL; + u32 *cmd_ptr = NULL; + int cmd_size_in_dw = 0; + int ret; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + /* Calculate how many bytes need to be alloc */ + cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE, ARB_SESSION_INDEX); + cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL); + cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL); + + cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + /* Program the command */ + cmd_ptr = cmd; + cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE, ARB_SESSION_INDEX); + cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr); + cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr); + + if (cmd_size_in_dw != (cmd_ptr - cmd)) { + ret = -EINVAL; + drm_err(>->i915->drm, "Failed to %s\n", __func__); + goto end; + } + + if (drm_debug_enabled(DRM_UT_DRIVER)) { + print_hex_dump(KERN_DEBUG, "global termination cmd binaries:", + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true); + } + + ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw); + if (ret) { + drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n"); + goto end; + } + +end: + kfree(cmd); + return ret; +} + +/** + * intel_pxp_arb_terminate_session - Terminate the arb hw session and its entries. + * @pxp: pointer to pxp struct. + * + * This function is NOT intended to be called from the ioctl, and need to be protected by + * ctx.mutex to ensure no SIP change during the call. + * + * Return: status. 0 means terminate is successful. + */ +int intel_pxp_arb_terminate_session(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + lockdep_assert_held(&pxp->ctx.mutex); + + /* terminate the hw sessions */ + ret = intel_pxp_arb_session_with_global_termination(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_with_global_termination\n"); + return ret; + } + + arb->is_in_play = false; + + return ret; +} + diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h index 1eb8db6deb0e..c1ed4ab176aa 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h @@ -11,5 +11,6 @@ struct intel_pxp; int intel_pxp_arb_create_session(struct intel_pxp *pxp); +int intel_pxp_arb_terminate_session(struct intel_pxp *pxp); #endif /* __INTEL_PXP_ARB_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c index e86d914e7629..57eca04963a9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -5,13 +5,33 @@ #include "intel_pxp_cmd.h" #include "i915_drv.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_context.h" #include "gt/intel_engine_pm.h" -struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, - struct intel_context *ce, - struct intel_gt_buffer_pool_node *pool, - u32 *cmd_buf, int cmd_size_in_dw) +/* PXP GPU command definitions */ + +/* MI_SET_APPID */ +#define MI_SET_APPID_TYPE1_APP BIT(7) +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0) + +/* MI_FLUSH_DW */ +#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22) + +/* MI_WAIT */ +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9) +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8) + +/* CRYPTO_KEY_EXCHANGE */ +#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16)) + +#define PXP_MAX_TYPE0_SESSIONS 16 +#define PXP_MAX_TYPE1_SESSIONS 6 + +static struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, + struct intel_context *ce, + struct intel_gt_buffer_pool_node *pool, + u32 *cmd_buf, int cmd_size_in_dw) { struct i915_vma *batch = ERR_PTR(-EINVAL); struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); @@ -50,7 +70,8 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, return batch; } -int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw) +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, + int cmd_size_in_dw) { int err = -EINVAL; struct i915_vma *batch; @@ -157,3 +178,102 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw) return err; } + +int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd, + int session_type, + int session_index) +{ + u32 increased_size_in_dw = 0; + u32 *cmd_prolog = cmd; + const int cmd_prolog_size_in_dw = 10; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + if (!cmd) + return cmd_prolog_size_in_dw; + + /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */ + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + /* MI_FLUSH_DW - pxp off */ + *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */ + *cmd_prolog++ = 0; /* DW1 */ + *cmd_prolog++ = 0; /* DW2 */ + + /* MI_SET_APPID */ + if (session_type == SESSION_TYPE_TYPE1) { + if (session_index >= PXP_MAX_TYPE1_SESSIONS) { + drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__); + goto end; + } + + *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP | + MI_SET_APPID_SESSION_ID(session_index)); + } else { + if (session_index >= PXP_MAX_TYPE0_SESSIONS) { + drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__); + goto end; + } + + *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index)); + } + + /* MFX_WAIT */ + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + /* MI_FLUSH_DW - pxp on */ + *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */ + *cmd_prolog++ = 0; /* DW1 */ + *cmd_prolog++ = 0; /* DW2 */ + + /* MFX_WAIT */ + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + increased_size_in_dw = (cmd_prolog - cmd); +end: + return increased_size_in_dw; +} + +int intel_pxp_cmd_add_epilog(u32 *cmd) +{ + u32 increased_size_in_dw = 0; + u32 *cmd_epilog = cmd; + const int cmd_epilog_size_in_dw = 5; + + if (!cmd) + return cmd_epilog_size_in_dw; + + /* MI_FLUSH_DW - pxp off */ + *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */ + *cmd_epilog++ = 0; /* DW1 */ + *cmd_epilog++ = 0; /* DW2 */ + + /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */ + *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + /* MI_BATCH_BUFFER_END */ + *cmd_epilog++ = MI_BATCH_BUFFER_END; + + increased_size_in_dw = (cmd_epilog - cmd); + return increased_size_in_dw; +} + +int intel_pxp_cmd_add_inline_termination(u32 *cmd) +{ + u32 increased_size_in_dw = 0; + u32 *cmd_termin = cmd; + const int cmd_termin_size_in_dw = 2; + + if (!cmd) + return cmd_termin_size_in_dw; + + /* CRYPTO_KEY_EXCHANGE - session inline termination */ + *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */ + *cmd_termin++ = 0; /* DW1 */ + + increased_size_in_dw = (cmd_termin - cmd); + return increased_size_in_dw; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h index d04463962421..087f260034c4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h @@ -9,10 +9,12 @@ #include "gt/intel_gt_buffer_pool.h" #include "intel_pxp.h" -struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, - struct intel_context *ce, - struct intel_gt_buffer_pool_node *pool, - u32 *cmd_buf, int cmd_size_in_dw); +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, + int cmd_size_in_dw); +int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd, + int session_type, + int session_index); +int intel_pxp_cmd_add_epilog(u32 *cmd); +int intel_pxp_cmd_add_inline_termination(u32 *cmd); -int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw); #endif /* __INTEL_PXP_SM_H__ */ From patchwork Thu Dec 17 21:49:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4B79C2BBCF for ; Thu, 17 Dec 2020 21:49:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 98AEE23A57 for ; Thu, 17 Dec 2020 21:49:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 98AEE23A57 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 177DF8951E; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FEF989A4E for ; Thu, 17 Dec 2020 21:49:35 +0000 (UTC) IronPort-SDR: CNxlaYAp63p5YGP+U4LS02TJPR+dI+HRgGA7ONaFRZ/R5Z0cUBaUz/sXOwiPiHexSysgTH0bAV 1tRKAsC5F5HA== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906276" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906276" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:32 -0800 IronPort-SDR: gQ41aBLsH3e7Hp3+yH8DOOHYdccJZ8YfdQZll7mqeweV36OCKjKQzLNTrrFbQ61bfuQNjaREzS nVZoBoCgsCaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780461" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:31 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:26 -0800 Message-Id: <20201217214931.13340-9-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 08/13] drm/i915/pxp: Enable PXP power management X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During the power event S3+ sleep/resume, hardware will lose all the encryption keys for every hardware session, even though the software session state was marked as alive after resume. So to handle such case, PXP should terminate all the hardware sessions and cleanup all the software states after the power cycle. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++ drivers/gpu/drm/i915/i915_drv.c | 4 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 + 6 files changed, 106 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index abe52189986a..d419dfa4923d 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp_arb.o \ pxp/intel_pxp_cmd.o \ pxp/intel_pxp_context.o \ + pxp/intel_pxp_pm.o \ pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 274aa0dd7050..09a64d0feafe 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -20,6 +20,7 @@ #include "intel_rc6.h" #include "intel_rps.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_pm.h" static void user_forcewake(struct intel_gt *gt, bool suspend) { @@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt) intel_uc_resume(>->uc); + intel_pxp_pm_resume(>->pxp); + user_forcewake(gt, false); out_fw: @@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt) user_forcewake(gt, true); wait_for_suspend(gt); + intel_pxp_pm_prepare_suspend(>->pxp); intel_uc_suspend(>->uc); } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9299a456adb0..af06c85e6ba7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -68,6 +68,8 @@ #include "gt/intel_gt_pm.h" #include "gt/intel_rc6.h" +#include "pxp/intel_pxp_pm.h" + #include "i915_debugfs.h" #include "i915_drv.h" #include "i915_ioc32.h" @@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_power_domains_resume(dev_priv); + intel_pxp_pm_resume_early(&dev_priv->gt.pxp); + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c new file mode 100644 index 000000000000..ebe89262485c --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include "intel_pxp_context.h" +#include "intel_pxp_arb.h" +#include "intel_pxp_pm.h" + +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ + if (!pxp->ctx.inited) + return; + + mutex_lock(&pxp->ctx.mutex); + + /* Disable PXP-IOCTLs */ + pxp->ctx.global_state_in_suspend = true; + + mutex_unlock(&pxp->ctx.mutex); +} + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ + if (!pxp->ctx.inited) + return; + + mutex_lock(&pxp->ctx.mutex); + + if (pxp->ctx.global_state_in_suspend) { + /* reset the attacked flag even there was a pending */ + pxp->ctx.global_state_attacked = false; + + pxp->ctx.flag_display_hm_surface_keys = false; + } + + mutex_unlock(&pxp->ctx.mutex); +} + +int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + int ret = 0; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + if (!pxp->ctx.inited) + return 0; + + mutex_lock(&pxp->ctx.mutex); + + /* Re-enable PXP-IOCTLs */ + if (pxp->ctx.global_state_in_suspend) { + ret = intel_pxp_arb_terminate_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to terminate the arb session\n"); + goto end; + } + + pxp->ctx.global_state_in_suspend = false; + } + +end: + mutex_unlock(&pxp->ctx.mutex); + + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h new file mode 100644 index 000000000000..135bfb59aaf7 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_PM_H__ +#define __INTEL_PXP_PM_H__ + +#include "i915_drv.h" + +#ifdef CONFIG_DRM_I915_PXP +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp); + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp); +int intel_pxp_pm_resume(struct intel_pxp *pxp); +#else +static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ +} + +static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ +} + +static inline int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + return 0; +} +#endif + +#endif /* __INTEL_PXP_PM_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index ac0eb9346781..a2e372621590 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -41,6 +41,7 @@ struct pxp_context { bool flag_display_hm_surface_keys; bool global_state_attacked; + bool global_state_in_suspend; }; struct intel_pxp { From patchwork Thu Dec 17 21:49:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA459C4361B for ; Thu, 17 Dec 2020 21:49:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72AE823A58 for ; Thu, 17 Dec 2020 21:49:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 72AE823A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDFCE89A16; Thu, 17 Dec 2020 21:49:36 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6631F89A16 for ; Thu, 17 Dec 2020 21:49:35 +0000 (UTC) IronPort-SDR: 6HQj5IV5ytGBo8wlMnhBDMfkk0dDQr1V668SzS1RBVj5YU4U7y0E1WSpkhr6lygcrO1N1Zr/5M EZlj41LTQIuw== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906277" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906277" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:32 -0800 IronPort-SDR: wVEr9VC+ugg5kMTQV/0TjbrON3IiX7lTXMFV603hD1e7b3kCeodoteQkWIrzqgA2J7kQmv4vTy W67fImTQimRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780463" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:32 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:27 -0800 Message-Id: <20201217214931.13340-10-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 09/13] drm/i915/pxp: Expose session state for display protection flip X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement the intel_pxp_gem_object_status() to allow i915 display querying the current PXP session state. In the design, display should not perform protection flip on the protected buffers if there is no PXP session alive. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +++++++++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 884e9c367911..a36f73bae480 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -140,3 +140,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) pxp->current_events |= events; schedule_work(&pxp->irq_work); } + +bool intel_pxp_gem_object_status(struct drm_i915_private *i915) +{ + if (i915->gt.pxp.ctx.inited && + i915->gt.pxp.ctx.flag_display_hm_surface_keys) + return true; + else + return false; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index cdaa6ce6fdca..976baf9b08e3 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -29,6 +29,8 @@ enum pxp_protection_modes { PROTECTION_MODE_ALL }; +struct drm_i915_private; + #ifdef CONFIG_DRM_I915_PXP void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); int i915_pxp_teardown_required_callback(struct intel_pxp *pxp); @@ -36,6 +38,7 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp); void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); +bool intel_pxp_gem_object_status(struct drm_i915_private *i915); #else static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { @@ -58,6 +61,11 @@ static inline void intel_pxp_init(struct intel_pxp *pxp) static inline void intel_pxp_fini(struct intel_pxp *pxp) { } + +static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915) +{ + return false; +} #endif #endif /* __INTEL_PXP_H__ */ From patchwork Thu Dec 17 21:49:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB191C2BBCF for ; Thu, 17 Dec 2020 21:49:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9EEEE23A58 for ; Thu, 17 Dec 2020 21:49:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9EEEE23A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A0E689A1F; Thu, 17 Dec 2020 21:49:37 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 82DBE89A1F for ; Thu, 17 Dec 2020 21:49:35 +0000 (UTC) IronPort-SDR: xxIve/pC3vnJ4gjtRyixXEASBivD7CLMes7GQBD7UJ7oHxVgJXydtzT0bZIqDutHuTcrmz1Nh8 uJTXKGwdR2wQ== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="236906278" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="236906278" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:33 -0800 IronPort-SDR: P8xJpWtXkclNnSrpT/+ueN1SQ/LS+WZ3rL6gK4QGLy2mv2cYMAJ9V3/g79q5BnOPvjpks2fCox 3oXiBMlZYI+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780468" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:32 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:28 -0800 Message-Id: <20201217214931.13340-11-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC-v11 10/13] mei: pxp: export pavp client to me client bus X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Lubart Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Vitaly Lubart Export PAVP client to work with i915_cp driver, for binding it uses kernel component framework. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 ++ drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++ drivers/misc/mei/pxp/mei_pxp.h | 18 +++ 6 files changed, 271 insertions(+) create mode 100644 drivers/misc/mei/pxp/Kconfig create mode 100644 drivers/misc/mei/pxp/Makefile create mode 100644 drivers/misc/mei/pxp/mei_pxp.c create mode 100644 drivers/misc/mei/pxp/mei_pxp.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index f5fd5b786607..0e0bcd0da852 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -47,3 +47,5 @@ config INTEL_MEI_TXE Intel Bay Trail source "drivers/misc/mei/hdcp/Kconfig" +source "drivers/misc/mei/pxp/Kconfig" + diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index f1c76f7ee804..d8e5165917f2 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o CFLAGS_mei-trace.o = -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/ +obj-$(CONFIG_INTEL_MEI_PXP) += pxp/ diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig new file mode 100644 index 000000000000..4029b96afc04 --- /dev/null +++ b/drivers/misc/mei/pxp/Kconfig @@ -0,0 +1,13 @@ + +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +config INTEL_MEI_PXP + tristate "Intel PXP services of ME Interface" + select INTEL_MEI_ME + depends on DRM_I915 + help + MEI Support for PXP Services on Intel platforms. + + Enables the ME FW services required for PXP support through + I915 display driver of Intel. diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile new file mode 100644 index 000000000000..0329950d5794 --- /dev/null +++ b/drivers/misc/mei/pxp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +# Makefile - PXP client driver for Intel MEI Bus Driver. + +obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c new file mode 100644 index 000000000000..5bd61fe445e3 --- /dev/null +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2020 Intel Corporation + */ + +/** + * DOC: MEI_PXP Client Driver + * + * The mei_pxp driver acts as a translation layer between PXP + * protocol implementer (I915) and ME FW by translating PXP + * negotiation messages to ME FW command payloads and vice versa. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mei_pxp.h" + +/** + * mei_pxp_send_message() - Sends a PXP message to ME FW. + * @dev: device corresponding to the mei_cl_device + * @message: a message buffer to send + * @size: size of the message + * Return: 0 on Success, <0 on Failure + */ +static int +mei_pxp_send_message(struct device *dev, const void *message, size_t size) +{ + struct mei_cl_device *cldev; + ssize_t byte; + + if (!dev || !message) + return -EINVAL; + + cldev = to_mei_cl_device(dev); + + /* temporary drop const qualifier till the API is fixed */ + byte = mei_cldev_send(cldev, (u8 *)message, size); + if (byte < 0) { + dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte); + return byte; + } + + return 0; +} + +/** + * mei_pxp_receive_message() - Receives a PXP message from ME FW. + * @dev: device corresponding to the mei_cl_device + * @buffer: a message buffer to contain the received message + * @size: size of the buffer + * Return: bytes sent on Success, <0 on Failure + */ +static int +mei_pxp_receive_message(struct device *dev, void *buffer, size_t size) +{ + struct mei_cl_device *cldev; + ssize_t byte; + + if (!dev || !buffer) + return -EINVAL; + + cldev = to_mei_cl_device(dev); + + byte = mei_cldev_recv(cldev, buffer, size); + if (byte < 0) { + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte); + return byte; + } + + return byte; +} + +static const struct i915_pxp_component_ops mei_pxp_ops = { + .owner = THIS_MODULE, + .send = mei_pxp_send_message, + .receive = mei_pxp_receive_message, +}; + +static int mei_component_master_bind(struct device *dev) +{ + struct mei_cl_device *cldev = to_mei_cl_device(dev); + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + int ret; + + dev_dbg(dev, "%s\n", __func__); + comp_master->ops = &mei_pxp_ops; + comp_master->tee_dev = dev; + ret = component_bind_all(dev, comp_master); + if (ret < 0) + return ret; + + return 0; +} + +static void mei_component_master_unbind(struct device *dev) +{ + struct mei_cl_device *cldev = to_mei_cl_device(dev); + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + + dev_dbg(dev, "%s\n", __func__); + component_unbind_all(dev, comp_master); +} + +static const struct component_master_ops mei_component_master_ops = { + .bind = mei_component_master_bind, + .unbind = mei_component_master_unbind, +}; + +/** + * mei_pxp_component_match - compare function for matching mei pxp. + * + * The function checks if the driver is i915, the subcomponent is PXP + * and the grand parent of pxp and the parent of i915 are the same + * PCH device. + * + * @dev: master device + * @subcomponent: subcomponent to match (I915_COMPONENT_PXP) + * @data: compare data (mei pxp device) + * + * Return: + * * 1 - if components match + * * 0 - otherwise + */ +static int mei_pxp_component_match(struct device *dev, int subcomponent, + void *data) +{ + struct device *base = data; + + if (subcomponent != I915_COMPONENT_PXP) + return 0; + + if (strcmp(dev->driver->name, "i915") == 0) { + base = base->parent; + if (!base) + return 0; + + base = base->parent; + dev = dev->parent; + return (base && dev && dev == base); + } + + return 0; +} + +static int mei_pxp_probe(struct mei_cl_device *cldev, + const struct mei_cl_device_id *id) +{ + struct i915_pxp_comp_master *comp_master; + struct component_match *master_match; + int ret; + + ret = mei_cldev_enable(cldev); + if (ret < 0) { + dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret); + goto enable_err_exit; + } + + comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL); + if (!comp_master) { + ret = -ENOMEM; + goto err_exit; + } + + master_match = NULL; + component_match_add_typed(&cldev->dev, &master_match, + mei_pxp_component_match, &cldev->dev); + if (IS_ERR_OR_NULL(master_match)) { + ret = -ENOMEM; + goto err_exit; + } + + mei_cldev_set_drvdata(cldev, comp_master); + ret = component_master_add_with_match(&cldev->dev, + &mei_component_master_ops, + master_match); + if (ret < 0) { + dev_err(&cldev->dev, "Master comp add failed %d\n", ret); + goto err_exit; + } + + return 0; + +err_exit: + mei_cldev_set_drvdata(cldev, NULL); + kfree(comp_master); + mei_cldev_disable(cldev); +enable_err_exit: + return ret; +} + +static int mei_pxp_remove(struct mei_cl_device *cldev) +{ + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + + component_master_del(&cldev->dev, &mei_component_master_ops); + kfree(comp_master); + mei_cldev_set_drvdata(cldev, NULL); + + return mei_cldev_disable(cldev); +} + +/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/ +#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \ + 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1) + +static struct mei_cl_device_id mei_pxp_tbl[] = { + { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(mei, mei_pxp_tbl); + +static struct mei_cl_driver mei_pxp_driver = { + .id_table = mei_pxp_tbl, + .name = KBUILD_MODNAME, + .probe = mei_pxp_probe, + .remove = mei_pxp_remove, +}; + +module_mei_cl_driver(mei_pxp_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MEI PXP"); diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h new file mode 100644 index 000000000000..e7b15373fefd --- /dev/null +++ b/drivers/misc/mei/pxp/mei_pxp.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright © 2020 Intel Corporation + * + * Authors: + * Vitaly Lubart + */ + +#ifndef __MEI_PXP_H__ +#define __MEI_PXP_H__ + +/* me_pxp_status: Enumeration of all PXP Status Codes */ +enum me_pxp_status { + ME_PXP_STATUS_SUCCESS = 0x0000, + +}; + +#endif /* __MEI_PXP_H__ */ From patchwork Thu Dec 17 21:49:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22AA3C2BBD4 for ; Thu, 17 Dec 2020 21:49:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD31023A57 for ; Thu, 17 Dec 2020 21:49:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD31023A57 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 25D998952F; Thu, 17 Dec 2020 21:49:46 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8286789A32 for ; Thu, 17 Dec 2020 21:49:33 +0000 (UTC) IronPort-SDR: +SbiEfxhc5W59SHK1h8fc25+7UhT+hFA6mClwrsQ4ri0zLAE9ruQzM4CvHYLm2kkBzGV00kE5/ 81HeQMjv410A== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="154561850" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="154561850" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:32 -0800 IronPort-SDR: GWGU9rPol5EZNGAhuvoX24SOOjsZ3e15u/V6AWSz9JBTjsXM8GPhbUaSmdjgFRoMlDnIEBUBno GxfS76EmBqog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780472" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:32 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:29 -0800 Message-Id: <20201217214931.13340-12-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joonas@freedesktop.org, Bommu Krishnaiah , Matthew@freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Bommu Krishnaiah Same old gem_create but with now with extensions support. This is needed to support various upcoming usecases. For now we use the extensions mechanism to support PAVP. Signed-off-by: Bommu Krishnaiah Signed-off-by: Matthew Auld Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Matthew Auld matthew.auld@intel.com Cc: Telukuntla Sreedhar --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++++++++++++- include/uapi/drm/i915_drm.h | 47 +++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index af06c85e6ba7..3dbda949bf71 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 17a4636ee542..c53b13c02e59 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -53,6 +53,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" +#include "i915_user_extensions.h" #include "intel_pm.h" @@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file, &args->size, &args->handle); } +struct create_ext { + struct drm_i915_private *i915; +}; + +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) +{ + if (!(args->param & I915_OBJECT_PARAM)) { + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n"); + return -EINVAL; + } + + return -EINVAL; +} + +static int create_setparam(struct i915_user_extension __user *base, void *data) +{ + struct drm_i915_gem_create_ext_setparam ext; + + if (copy_from_user(&ext, base, sizeof(ext))) + return -EFAULT; + + return __create_setparam(&ext.param, data); +} + +static const i915_user_extension_fn create_extensions[] = { + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam, +}; + /** * Creates a new mm object and returns a handle to it. * @dev: drm device pointer @@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_i915_private *i915 = to_i915(dev); - struct drm_i915_gem_create *args = data; + struct create_ext ext_data = { .i915 = i915 }; + struct drm_i915_gem_create_ext *args = data; + int ret; i915_gem_flush_free_objects(i915); + ret = i915_user_extensions(u64_to_user_ptr(args->extensions), + create_extensions, + ARRAY_SIZE(create_extensions), + &ext_data); + if (ret) + return ret; + + return i915_gem_create(file, intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM), diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 6edcb2b6c708..e918ccc81c74 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) @@ -728,6 +729,27 @@ struct drm_i915_gem_create { __u32 pad; }; +struct drm_i915_gem_create_ext { + /** + * Requested size for the object. + * + * The (page-aligned) allocated size for the object will be returned. + */ + __u64 size; + /** + * Returned handle for the object. + * + * Object handles are nonzero. + */ + __u32 handle; + __u32 pad; +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0) +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \ + (-(I915_GEM_CREATE_EXT_SETPARAM << 1)) + __u64 extensions; + +}; + struct drm_i915_gem_pread { /** Handle for the object being read. */ __u32 handle; @@ -1698,6 +1720,31 @@ struct drm_i915_gem_context_param { __u64 value; }; +struct drm_i915_gem_object_param { + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */ + __u32 handle; + + /* Data pointer size */ + __u32 size; + +/* + * I915_OBJECT_PARAM: + * + * Select object namespace for the param. + */ +#define I915_OBJECT_PARAM (1ull<<32) + + __u64 param; + + /* Data value or pointer */ + __u64 data; +}; + +struct drm_i915_gem_create_ext_setparam { + struct i915_user_extension base; + struct drm_i915_gem_object_param param; +}; + /** * Context SSEU programming * From patchwork Thu Dec 17 21:49:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3442AC2BBD4 for ; Thu, 17 Dec 2020 21:49:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4D1823A58 for ; Thu, 17 Dec 2020 21:49:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E4D1823A58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFCBF89A32; Thu, 17 Dec 2020 21:49:37 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C6D989A35 for ; Thu, 17 Dec 2020 21:49:33 +0000 (UTC) IronPort-SDR: 3n2FAUx6cWjwwJcfE0M6BQz20XtSiJ6SlPTxY+JCXe4HEL5BJR5OnPQPq1m0Pt5unekBatMJTw lyjTiCQkdF/A== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="154561851" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="154561851" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 13:49:33 -0800 IronPort-SDR: 9AwrbObxG6mEd0n0dFj0OmsOEKUENMYqMTuFTEmw1qCFDqtuRp8J3DpZvBAos91ze6E84wvnHt WEBNKuwWQj7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="342780478" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:32 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:30 -0800 Message-Id: <20201217214931.13340-13-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 12/13] drm/i915/pxp: User interface for Protected buffer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bommu Krishnaiah , Huang Sean Z , Kondapally Kalyan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Bommu Krishnaiah This api allow user mode to create Protected buffer and context creation. Signed-off-by: Bommu Krishnaiah Cc: Telukuntla Sreedhar Cc: Kondapally Kalyan Cc: Gupta Anshuman Cc: Huang Sean Z --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++++++++++-- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 ++++++++ .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++ drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++---- include/uapi/drm/i915_drm.h | 19 +++++++++++++++ 6 files changed, 67 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index c7363036765a..12847edec751 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -2019,12 +2019,23 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv, case I915_CONTEXT_PARAM_RECOVERABLE: if (args->size) ret = -EINVAL; - else if (args->value) - i915_gem_context_set_recoverable(ctx); + else if (args->value) { + if (!i915_gem_context_is_protected(ctx)) + i915_gem_context_set_recoverable(ctx); + else + ret = -EPERM; + } else i915_gem_context_clear_recoverable(ctx); break; + case I915_CONTEXT_PARAM_PROTECTED_CONTENT: + if (args->size) + ret = -EINVAL; + else if (args->value) + i915_gem_context_set_protected(ctx); + break; + case I915_CONTEXT_PARAM_PRIORITY: ret = set_priority(ctx, args); break; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h index b5c908f3f4f2..f991e882bbe0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h @@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); } +static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx) +{ + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags); +} + +static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx) +{ + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags); +} + static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx) { clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h index 1449f54924e0..0917c9431c65 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h @@ -134,7 +134,7 @@ struct i915_gem_context { #define UCONTEXT_BANNABLE 2 #define UCONTEXT_RECOVERABLE 3 #define UCONTEXT_PERSISTENCE 4 - +#define UCONTEXT_PROTECTED 5 /** * @flags: small set of booleans */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index e2d9b7e1e152..90ac955463f4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -161,6 +161,11 @@ struct drm_i915_gem_object { } mmo; I915_SELFTEST_DECLARE(struct list_head st_link); + /** + * @user_flags: small set of booleans set by the user + */ + unsigned long user_flags; +#define I915_BO_PROTECTED BIT(0) unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c53b13c02e59..611a0b5ab51f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -184,7 +184,8 @@ static int i915_gem_create(struct drm_file *file, struct intel_memory_region *mr, u64 *size_p, - u32 *handle_p) + u32 *handle_p, + u64 user_flags) { struct drm_i915_gem_object *obj; u32 handle; @@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file, if (IS_ERR(obj)) return PTR_ERR(obj); + obj->user_flags = user_flags; + ret = drm_gem_handle_create(file, &obj->base, &handle); /* drop reference from allocate - handle holds it now */ i915_gem_object_put(obj); @@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file, return i915_gem_create(file, intel_memory_region_by_type(to_i915(dev), mem_type), - &args->size, &args->handle); + &args->size, &args->handle, 0); } struct create_ext { - struct drm_i915_private *i915; + struct drm_i915_private *i915; + unsigned long user_flags; }; static int __create_setparam(struct drm_i915_gem_object_param *args, @@ -273,6 +277,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args, return -EINVAL; } + switch (lower_32_bits(args->param)) { + case I915_PARAM_PROTECTED_CONTENT: + if (args->size) { + return -EINVAL; + } else if (args->data) { + ext_data->user_flags = args->data; + return 0; + } + break; + } + return -EINVAL; } @@ -318,7 +333,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, return i915_gem_create(file, intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM), - &args->size, &args->handle); + &args->size, &args->handle, ext_data.user_flags); } static int diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index e918ccc81c74..d6085a328b2c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1715,6 +1715,15 @@ struct drm_i915_gem_context_param { * Default is 16 KiB. */ #define I915_CONTEXT_PARAM_RINGSIZE 0xc + +/* + * I915_CONTEXT_PARAM_PROTECTED_CONTENT: + * + * If set to true (1) PAVP content protection is enabled. + * When enabled, the context is marked unrecoverable and may + * become invalid due to PAVP teardown event or other error. + */ +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd /* Must be kept compact -- no holes and well documented */ __u64 value; @@ -1734,6 +1743,16 @@ struct drm_i915_gem_object_param { */ #define I915_OBJECT_PARAM (1ull<<32) +/* + * I915_PARAM_PROTECTED_CONTENT: + * + * If set to true (1) buffer contents is expected to be protected by + * PAVP encryption and requires decryption for scan out and processing. + * Protected buffers can only be used in PAVP protected contexts. + * A protected buffer may become invalid as a result of PAVP teardown. + */ +#define I915_PARAM_PROTECTED_CONTENT 0x1 + __u64 param; /* Data value or pointer */ From patchwork Thu Dec 17 21:49:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11980841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDB2FC4361B for ; Thu, 17 Dec 2020 21:49:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8C4323A57 for ; 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d="scan'208";a="342780481" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga006.jf.intel.com with ESMTP; 17 Dec 2020 13:49:32 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Thu, 17 Dec 2020 13:49:31 -0800 Message-Id: <20201217214931.13340-14-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201217214931.13340-1-sean.z.huang@intel.com> References: <20201217214931.13340-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v11 13/13] drm/i915/pxp: Add plane decryption support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bommu Krishnaiah MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anshuman Gupta Add support to enable/disable PLANE_SURF Decryption Request bit. It requires only to enable plane decryption support when following condition met. 1. PAVP session is enabled. 2. Buffer object is protected. v2: - Rebased to libva_cp-drm-tip_tgl_cp tree. - Used gen fb obj user_flags instead gem_object_metadata. [Krishna] Cc: Bommu Krishnaiah Cc: Huang, Sean Z Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index b7e208816074..273bdc031e8d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -39,6 +39,8 @@ #include #include +#include "pxp/intel_pxp.h" + #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" @@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj) +{ + return obj->user_flags & I915_BO_PROTECTED ? true : false; +} + static void skl_plane_async_flip(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane, u32 surf_addr = plane_state->color_plane[color_plane].offset; u32 stride = skl_plane_stride(plane_state, color_plane); const struct drm_framebuffer *fb = plane_state->hw.fb; + const struct drm_i915_gem_object *obj = intel_fb_obj(fb); int aux_plane = intel_main_to_aux_plane(fb, color_plane); int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane, u8 alpha = plane_state->hw.alpha >> 8; u32 plane_color_ctl = 0, aux_dist = 0; unsigned long irqflags; - u32 keymsk, keymax; + u32 keymsk, keymax, plane_surf; u32 plane_ctl = plane_state->ctl; plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane, * the control register just before the surface register. */ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr; + + if (intel_pxp_gem_object_status(dev_priv) && + intel_fb_obj_protected(obj)) + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED; + else + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED; + + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1e8dfe435ca8..0ea7e2a402ae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7209,6 +7209,7 @@ enum { #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2) #define _PLANE_OFFSET_1_B 0x711a4 #define _PLANE_OFFSET_2_B 0x712a4