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Fri, 18 Dec 2020 15:30:42 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, robh@kernel.org, bhelgaas@google.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH] PCI: dwc: Add upper limit address for outbound iATU Date: Fri, 18 Dec 2020 21:00:34 +0530 Message-Id: <1608305434-31685-1-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBIsWRmVeSWpSXmKPExsWy7bCmlu4BhgfxBtf2qFssacqw2HW3g91i xZeZ7BaXd81hszg77zibxZvfL9gtFm39wm7xf88Odovew7UOnB5r5q1h9Ng56y67x4JNpR6b VnWyefRtWcXosWX/Z0aPz5vkAtijuGxSUnMyy1KL9O0SuDIeX/rGUtAiUNHx4h9jA+Mt3i5G Tg4JAROJw32fGbsYuTiEBHYzSpzetI8FJCEk8IlR4v45VojEN0aJ5n1zWGE6NnVNYIdI7GWU WPz/BFRHC5PEiV4XEJtNQEui8WsXM4gtImAtcbh9CxtIA7PAHkaJH4vuM4EkhAVcJJadWAzW zCKgKnGxaReYzSvgKvHyxUpmiG1yEjfPdTKDNEsInGKX2D7rNyNEwkXi0t9Z7BC2sMSr41ug bCmJl/1tUHa+xNQLT4GGcgDZFRLLe+ogwvYSB67MAQszC2hKrN+lDxGWlZh6ah3YacwCfBK9 v58wQcR5JXbMg7GVJb783cMCYUtKzDt2GRooHhIzfuyChkOsxPql71kmMMrOQtiwgJFxFaNk akFxbnpqsWmBYV5quV5xYm5xaV66XnJ+7iZGcGLQ8tzBePfBB71DjEwcjIcYJTiYlUR4zaTu xwvxpiRWVqUW5ccXleakFh9ilOZgURLnVfpxJk5IID2xJDU7NbUgtQgmy8TBKdXAtND0+tyu Z852UetPtcduObxg/Z1X99tkD/5LLWCqdqjfsKtqb8H8iw84zxv+ybXMTLS3kREteDw7Sf/n US75a2vTlA4v+73gCf+mKVOuzZBp8+BcVRh7xPTPhAvheen793MvnPFbepdfT7KYlgWDF9+T EKmr5gtKy0Pt18n1X+I89r296OFHsRN/Ak7ELHnl7mmwlP+R/KUntruvy4ce+HTZyGjDuvzl qyQid9+4yxdse/5xutmd69OC7Pqi86dz9ci+rz2adllq+ZF0YW3nE5felvVmRDI6n2hzWMrH EyO9ueeQ8q27AW+e92zK6NGYbvjvvOla47aIwoPfI3++vZC27o1i3q0zclF33oV/yVFiKc5I NNRiLipOBADkgbq+ewMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprILMWRmVeSWpSXmKPExsWy7bCSvK7y6TvxBlf26Fosacqw2HW3g91i xZeZ7BaXd81hszg77zibxZvfL9gtFm39wm7xf88Odovew7UOnB5r5q1h9Ng56y67x4JNpR6b VnWyefRtWcXosWX/Z0aPz5vkAtijuGxSUnMyy1KL9O0SuDIeX/rGUtAiUNHx4h9jA+Mt3i5G Tg4JAROJTV0T2LsYuTiEBHYzSsz7tYAVIiEp8fniOiYIW1hi5b/nUEVNTBK9By4zgyTYBLQk Gr92gdkiArYS9x9NZgUpYhY4wijR8+AuG0hCWMBFYtmJxSwgNouAqsTFpl1gNq+Aq8TLFyuZ ITbISdw818k8gZFnASPDKkbJ1ILi3PTcYsMCw7zUcr3ixNzi0rx0veT83E2M4FDT0tzBuH3V B71DjEwcjIcYJTiYlUR4Qx/cjhfiTUmsrEotyo8vKs1JLT7EKM3BoiTOe6HrZLyQQHpiSWp2 ampBahFMlomDU6qBaYnktpinM8r1nC5dO/16xfe/E+N/fX2ezvzp63F/iy61U98iLItPR0bx tVh4l5UvNd3/4MXPY+nC3VNK9opNiu7fuX53gW7xuc/nIg/zvbcykfqmaGYXpW6Re1L/5Y3F zD+y66ZsfBbJxv1E4OuVd+uFA8XKuBaqxh2wXROlqyn47WLOizrjYy6qhq8e/G55wSKcHJGS Uxpw99J8+Xsr/u7Kl47eYnxjddbuvKyL99/PM1i2xVtMzGbZ6b7cR1Yn//5rX7v66VnmfYvY Z2Tvf+zrdLTQT//RrR8PhOpuJnJPF0+K+af8XZ338NurZzletrXsOLHtd6dElHVFibXPIZu1 SazppqGLzy72ylxT8UWJpTgj0VCLuag4EQDNMhWNpAIAAA== X-CMS-MailID: 20201218153043epcas5p1831d9bc440e9e05609792f19dfeb4012 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20201218153043epcas5p1831d9bc440e9e05609792f19dfeb4012 References: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The size parameter is unsigned long type which can accept size > 4GB. In that case, the upper limit address must be programmed. Add support to program the upper limit address and set INCREASE_REGION_SIZE in case size > 4GB. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 28c56a1..7eba3b2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -290,12 +290,16 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, upper_32_bits(cpu_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT, + upper_32_bits(cpu_addr + size - 1)); dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(pci_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(pci_addr)); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | - PCIE_ATU_FUNC_NUM(func_no)); + val = type | PCIE_ATU_FUNC_NUM(func_no); + val = upper_32_bits(size - 1) ? + val | PCIE_ATU_INCREASE_REGION_SIZE : val; + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val); dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); /* diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b09329b..28b72fb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -106,6 +106,7 @@ #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) #define PCIE_ATU_UPPER_TARGET 0x91C +#define PCIE_ATU_UPPER_LIMIT 0x924 #define PCIE_MISC_CONTROL_1_OFF 0x8BC #define PCIE_DBI_RO_WR_EN BIT(0)