From patchwork Wed Dec 23 09:08:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D7F7C433E0 for ; Wed, 23 Dec 2020 09:13:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CDF222482 for ; Wed, 23 Dec 2020 09:13:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3CDF222482 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0DW-0000AM-9K for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:13:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09w-0003hH-MI for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:16 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2627) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09r-0002YU-4j for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:16 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4D16pP5P89z7K20; Wed, 23 Dec 2020 17:09:17 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:51 +0800 From: Jiahui Cen To: Subject: [PATCH v3 1/8] acpi: Allow DSDT acpi table changes Date: Wed, 23 Dec 2020 17:08:29 +0800 Message-ID: <20201223090836.9075-2-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.35; envelope-from=cenjiahui@huawei.com; helo=szxga07-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Jiahui Cen --- tests/qtest/bios-tables-test-allowed-diff.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..42418e58e7 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,6 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/microvm/DSDT.pcie", +"tests/data/acpi/virt/DSDT", +"tests/data/acpi/virt/DSDT.memhp", +"tests/data/acpi/virt/DSDT.numamem", +"tests/data/acpi/virt/DSDT.pxb", From patchwork Wed Dec 23 09:08:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02A97C433E0 for ; Wed, 23 Dec 2020 09:13:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 646DD207A2 for ; Wed, 23 Dec 2020 09:13:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 646DD207A2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:43434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0Cd-0006eu-CI for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:13:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0Av-0004l2-Nd for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:11:17 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3007) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0Aq-0002Xq-Tj for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:11:17 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D16pN1Xl9zhwSf; Wed, 23 Dec 2020 17:09:16 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:52 +0800 From: Jiahui Cen To: Subject: [PATCH v3 2/8] acpi: Add addr offset in build_crs Date: Wed, 23 Dec 2020 17:08:30 +0800 Message-ID: <20201223090836.9075-3-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" AML needs Address Translation offset to describe how a bridge translates addresses accross the bridge when using an address descriptor, and especially on ARM, the translation offset of pio resource is usually non zero. Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus number into build_crs. Signed-off-by: Jiahui Cen --- hw/acpi/aml-build.c | 18 ++++++++++-------- hw/i386/acpi-build.c | 3 ++- hw/pci-host/gpex-acpi.c | 3 ++- include/hw/acpi/aml-build.h | 4 +++- 4 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index f976aa667b..7b6ebb0cc8 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL); } -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, + uint32_t mmio32_offset, uint64_t mmio64_offset, + uint16_t bus_nr_offset) { Aml *crs = aml_resource_template(); CrsRangeSet temp_range_set; @@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) for (i = 0; i < temp_range_set.io_ranges->len; i++) { entry = g_ptr_array_index(temp_range_set.io_ranges, i); aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0, entry->base, entry->limit, io_offset, + entry->limit - entry->base + 1)); crs_range_insert(range_set->io_ranges, entry->base, entry->limit); } @@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, 0, + 0, entry->base, entry->limit, mmio32_offset, entry->limit - entry->base + 1)); crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); } @@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, 0, + 0, entry->base, entry->limit, mmio64_offset, entry->limit - entry->base + 1)); crs_range_insert(range_set->mem_64bit_ranges, entry->base, entry->limit); @@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 0, pci_bus_num(host->bus), max_bus, - 0, + bus_nr_offset, max_bus - pci_bus_num(host->bus) + 1)); return crs; diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f18b71dea9..f56d699c7f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1360,7 +1360,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dev, build_prt(false)); - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, + 0, 0, 0, 0); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 7f20ee1c98..11b3db8f71 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -168,7 +168,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) * 1. The resources the pci-brige/pcie-root-port need. * 2. The resources the devices behind pxb need. */ - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, + cfg->pio.base, 0, 0, 0); aml_append(dev, aml_name_decl("_CRS", crs)); acpi_dsdt_add_pci_osc(dev); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index e727bea1bc..54a5aec4d7 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -452,7 +452,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges, void crs_range_set_init(CrsRangeSet *range_set); void crs_range_set_free(CrsRangeSet *range_set); -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, + uint32_t mmio32_offset, uint64_t mmio64_offset, + uint16_t bus_nr_offset); void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, uint64_t len, int node, MemoryAffinityFlags flags); From patchwork Wed Dec 23 09:08:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9821EC43381 for ; Wed, 23 Dec 2020 09:11:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ECBE420760 for ; Wed, 23 Dec 2020 09:11:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ECBE420760 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0BS-00055W-MT for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:11:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09w-0003hA-0q for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:16 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09q-0002Xp-Qa for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:15 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4D16pX4Wp9zhvKV; Wed, 23 Dec 2020 17:09:24 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:53 +0800 From: Jiahui Cen To: Subject: [PATCH v3 3/8] acpi/gpex: Inform os to keep firmware resource map Date: Wed, 23 Dec 2020 17:08:31 +0800 Message-ID: <20201223090836.9075-4-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=cenjiahui@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There may be some differences in pci resource assignment between guest os and firmware. Eg. A Bridge with Bus [d2] -+-[0000:d2]---01.0-[d3]----01.0 where [d2:01.00] is a pcie-pci-bridge with BAR0 (mem, 64-bit, non-pref) [size=256] [d3:01.00] is a PCI Device with BAR0 (mem, 64-bit, pref) [size=128K] BAR4 (mem, 64-bit, pref) [size=64M] In EDK2, the Resource Map would be: PciBus: Resource Map for Bridge [D2|01|00] Type = PMem64; Base = 0x8004000000; Length = 0x4100000; Alignment = 0x3FFFFFF Base = 0x8004000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [D3|01|00:20] Base = 0x8008000000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [D3|01|00:10] Type = Mem64; Base = 0x8008100000; Length = 0x100; Alignment = 0xFFF It would use 0x4100000 to calculate the root bus's PMem64 resource window. While in Linux, kernel will use 0x1FFFFFF as the alignment to calculate the PMem64 size, which would be 0x6000000. So kernel would try to allocate 0x6000000 from the PMem64 resource window, but since the window size is 0x4100000 as assigned by EDK2, the allocation would fail. The diffences could result in resource assignment failure. Using _DSM #5 method to inform guest os not to ignore the PCI configuration that firmware has done at boot time could handle the differences. Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 11b3db8f71..c189306599 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -112,10 +112,24 @@ static void acpi_dsdt_add_pci_osc(Aml *dev) UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); ifctx = aml_if(aml_equal(aml_arg(0), UUID)); ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); - uint8_t byte_list[1] = {1}; - buf = aml_buffer(1, byte_list); + uint8_t byte_list[] = { + 0x1 << 0 /* support for functions other than function 0 */ | + 0x1 << 5 /* support for function 5 */ + }; + buf = aml_buffer(ARRAY_SIZE(byte_list), byte_list); aml_append(ifctx1, aml_return(buf)); aml_append(ifctx, ifctx1); + + /* PCI Firmware Specification 3.1 + * 4.6.5. _DSM for Ignoring PCI Boot Configurations + */ + /* Arg2: Function Index: 5 */ + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(5))); + /* 0 - The operating system must not ignore the PCI configuration that + * firmware has done at boot time. + */ + aml_append(ifctx1, aml_return(aml_int(0))); + aml_append(ifctx, ifctx1); aml_append(method, ifctx); byte_list[0] = 0; From patchwork Wed Dec 23 09:08:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D415DC433E6 for ; Wed, 23 Dec 2020 09:11:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D79620760 for ; Wed, 23 Dec 2020 09:11:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D79620760 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:40066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0BT-00057o-Si for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:11:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09y-0003iJ-Ld for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:18 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09s-0002Zg-23 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:18 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D16pB19trzM8Jw; Wed, 23 Dec 2020 17:09:06 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:54 +0800 From: Jiahui Cen To: Subject: [PATCH v3 4/8] acpi/gpex: Exclude pxb's resources from PCI0 Date: Wed, 23 Dec 2020 17:08:32 +0800 Message-ID: <20201223090836.9075-5-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise, the resource windows would overlap in guest, and the IO resource window would fail to be registered. Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 64 +++++++++++++------- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index c189306599..4bf1e94309 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -144,6 +144,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) Aml *method, *crs, *dev, *rbuf; PCIBus *bus = cfg->bus; CrsRangeSet crs_range_set; + CrsRangeEntry *entry; + int i; /* start to construct the tables for pxb */ crs_range_set_init(&crs_range_set); @@ -191,7 +193,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(scope, dev); } } - crs_range_set_free(&crs_range_set); /* tables for the main */ dev = aml_device("%s", "PCI0"); @@ -209,36 +210,55 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(method, aml_return(aml_int(cfg->ecam.base))); aml_append(dev, method); + /* + * At this point crs_range_set has all the ranges used by pci + * busses *other* than PCI0. These ranges will be excluded from + * the PCI0._CRS. + */ rbuf = aml_resource_template(); aml_append(rbuf, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, nr_pcie_buses)); if (cfg->mmio32.size) { - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - cfg->mmio32.base, - cfg->mmio32.base + cfg->mmio32.size - 1, - 0x0000, - cfg->mmio32.size)); + crs_replace_with_free_ranges(crs_range_set.mem_ranges, + cfg->mmio32.base, + cfg->mmio32.base + cfg->mmio32.size - 1); + for (i = 0; i < crs_range_set.mem_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_ranges, i); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, entry->limit, + 0x0000, entry->limit - entry->base + 1)); + } } if (cfg->pio.size) { - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, - cfg->pio.size - 1, - cfg->pio.base, - cfg->pio.size)); + crs_replace_with_free_ranges(crs_range_set.io_ranges, + 0x0000, + cfg->pio.size - 1); + for (i = 0; i < crs_range_set.io_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.io_ranges, i); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, entry->base, + entry->limit, cfg->pio.base, + entry->limit - entry->base + 1)); + } } if (cfg->mmio64.size) { - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - cfg->mmio64.base, - cfg->mmio64.base + cfg->mmio64.size - 1, - 0x0000, - cfg->mmio64.size)); + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + cfg->mmio64.base, + cfg->mmio64.base + cfg->mmio64.size - 1); + for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, + entry->limit, 0x0000, + entry->limit - entry->base + 1)); + } } aml_append(dev, aml_name_decl("_CRS", rbuf)); @@ -257,4 +277,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(dev_res0, aml_name_decl("_CRS", crs)); aml_append(dev, dev_res0); aml_append(scope, dev); + + crs_range_set_free(&crs_range_set); } From patchwork Wed Dec 23 09:08:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19407C433DB for ; Wed, 23 Dec 2020 09:17:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65335207A4 for ; Wed, 23 Dec 2020 09:17:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65335207A4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:55428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0Gg-0003Cd-1x for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:17:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0A5-0003jg-L0 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:26 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09r-0002aT-LL for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:23 -0500 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D16pF6XGVzM7yb; Wed, 23 Dec 2020 17:09:09 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:54 +0800 From: Jiahui Cen To: Subject: [PATCH v3 5/8] acpi/gpex: Append pxb devs in ascending order Date: Wed, 23 Dec 2020 17:08:33 +0800 Message-ID: <20201223090836.9075-6-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The overlap check of IO resource window would fail when Linux kernel registers an IO resource [b, c) earlier than another resource [a, b). Though this incorrect check could be fixed by [1], it would be better to append pxb devs into DSDT table in ascending order. [1]: https://lore.kernel.org/lkml/20201218062335.5320-1-cenjiahui@huawei.com/ Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 4bf1e94309..95a7a0f12b 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -141,7 +141,7 @@ static void acpi_dsdt_add_pci_osc(Aml *dev) void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) { int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; - Aml *method, *crs, *dev, *rbuf; + Aml *method, *crs, *dev, *rbuf, *pxb_devs[nr_pcie_buses]; PCIBus *bus = cfg->bus; CrsRangeSet crs_range_set; CrsRangeEntry *entry; @@ -149,6 +149,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) /* start to construct the tables for pxb */ crs_range_set_init(&crs_range_set); + memset(pxb_devs, 0, sizeof(pxb_devs)); if (bus) { QLIST_FOREACH(bus, &bus->child, sibling) { uint8_t bus_num = pci_bus_num(bus); @@ -190,7 +191,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) acpi_dsdt_add_pci_osc(dev); - aml_append(scope, dev); + pxb_devs[bus_num] = dev; } } @@ -278,5 +279,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(dev, dev_res0); aml_append(scope, dev); + for (i = 0; i < ARRAY_SIZE(pxb_devs); i++) { + if (pxb_devs[i]) { + aml_append(scope, pxb_devs[i]); + } + } + crs_range_set_free(&crs_range_set); } From patchwork Wed Dec 23 09:08:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F4FDC433E9 for ; Wed, 23 Dec 2020 09:11:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F02202247F for ; Wed, 23 Dec 2020 09:11:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F02202247F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0BS-00055x-LO for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:11:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09u-0003h4-5K for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:14 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2901) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09q-0002ZW-Pg for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:13 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4D16pQ4RNqz15hM8; Wed, 23 Dec 2020 17:09:18 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:55 +0800 From: Jiahui Cen To: Subject: [PATCH v3 6/8] Kconfig: Enable PXB for ARM_VIRT by default Date: Wed, 23 Dec 2020 17:08:34 +0800 Message-ID: <20201223090836.9075-7-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.190; envelope-from=cenjiahui@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PXB is now supported on ARM, so let's enable it by default. Signed-off-by: Jiahui Cen --- hw/pci-bridge/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/Kconfig b/hw/pci-bridge/Kconfig index a51ec716f5..f8df4315ba 100644 --- a/hw/pci-bridge/Kconfig +++ b/hw/pci-bridge/Kconfig @@ -5,7 +5,7 @@ config PCIE_PORT config PXB bool - default y if Q35 + default y if Q35 || ARM_VIRT config XIO3130 bool From patchwork Wed Dec 23 09:08:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C115FC433E6 for ; Wed, 23 Dec 2020 09:14:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E810207A4 for ; Wed, 23 Dec 2020 09:14:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E810207A4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0DY-0000E0-7Y for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:14:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0A6-0003jq-CF for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:27 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2902) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09u-0002bB-Iq for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:26 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4D16pX45Mmz15hVK; Wed, 23 Dec 2020 17:09:24 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:56 +0800 From: Jiahui Cen To: Subject: [PATCH v3 7/8] acpi: Enable pxb unit-test for ARM virt machine Date: Wed, 23 Dec 2020 17:08:35 +0800 Message-ID: <20201223090836.9075-8-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.190; envelope-from=cenjiahui@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" No matter whether the pxb is enabled or not, the CONFIG_PXB macro in test would keep undefined. And since pxb is now enabled for ARM Virt machine by default, let's enable pxb unit-test by removing the CONFIG_PXB. Signed-off-by: Jiahui Cen --- tests/qtest/bios-tables-test.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 4e026f90d0..669202fc95 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1196,7 +1196,6 @@ static void test_acpi_virt_tcg_numamem(void) } -#ifdef CONFIG_PXB static void test_acpi_virt_tcg_pxb(void) { test_data data = { @@ -1228,7 +1227,6 @@ static void test_acpi_virt_tcg_pxb(void) free_test_data(&data); } -#endif static void test_acpi_tcg_acpi_hmat(const char *machine) { @@ -1342,9 +1340,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); -#ifdef CONFIG_PXB qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); -#endif } ret = g_test_run(); boot_sector_cleanup(disk); From patchwork Wed Dec 23 09:08:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahui Cen X-Patchwork-Id: 11987959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BF74C433DB for ; Wed, 23 Dec 2020 09:15:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6498C207A4 for ; Wed, 23 Dec 2020 09:15:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6498C207A4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:52832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0Er-0001zG-7Z for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:15:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0A5-0003jh-LV for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:26 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3008) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks09s-0002aA-RI for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:10:22 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D16pW0vHzzhwn7; Wed, 23 Dec 2020 17:09:23 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:56 +0800 From: Jiahui Cen To: Subject: [PATCH v3 8/8] acpi: Update addr_trans and _DSM in expected files Date: Wed, 23 Dec 2020 17:08:36 +0800 Message-ID: <20201223090836.9075-9-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Addr_trans in _CRS is changed and a new _DSM #5 method is added. Also the expected file for pxb for ARM virt does not match the source code. Update expected DSDT files accordingly, and re-enable their testing. Full diff of changed files disassembly: diff -ru /tmp/old/tests/data/acpi/microvm/DSDT.pcie.dsl /tmp/new/tests/data/acpi/microvm/DSDT.pcie.dsl --- /tmp/old/tests/data/acpi/microvm/DSDT.pcie.dsl 2020-12-23 15:49:57.161081285 +0800 +++ /tmp/new/tests/data/acpi/microvm/DSDT.pcie.dsl 2020-12-23 15:55:11.837769953 +0800 @@ -9,9 +9,9 @@ * * Original Table Header: * Signature "DSDT" - * Length 0x00000BCF (3023) + * Length 0x00000BD7 (3031) * Revision 0x02 - * Checksum 0x29 + * Checksum 0x99 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1302,9 +1302,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) diff -ru /tmp/old/tests/data/acpi/virt/DSDT.dsl /tmp/new/tests/data/acpi/virt/DSDT.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.dsl 2020-12-23 15:49:57.421095066 +0800 +++ /tmp/new/tests/data/acpi/virt/DSDT.dsl 2020-12-23 15:55:12.267792771 +0800 @@ -9,9 +9,9 @@ * * Original Table Header: * Signature "DSDT" - * Length 0x0000144C (5196) + * Length 0x00001454 (5204) * Revision 0x02 - * Checksum 0xF0 + * Checksum 0x60 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1838,9 +1838,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) diff -ru /tmp/old/tests/data/acpi/virt/DSDT.memhp.dsl /tmp/new/tests/data/acpi/virt/DSDT.memhp.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.memhp.dsl 2020-12-23 15:49:57.421095066 +0800 +++ /tmp/new/tests/data/acpi/virt/DSDT.memhp.dsl 2020-12-23 15:55:12.277793302 +0800 @@ -9,9 +9,9 @@ * * Original Table Header: * Signature "DSDT" - * Length 0x0000199D (6557) + * Length 0x000019A5 (6565) * Revision 0x02 - * Checksum 0x11 + * Checksum 0x90 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1840,9 +1840,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) diff -ru /tmp/old/tests/data/acpi/virt/DSDT.numamem.dsl /tmp/new/tests/data/acpi/virt/DSDT.numamem.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.numamem.dsl 2020-12-23 15:49:57.431095596 +0800 +++ /tmp/new/tests/data/acpi/virt/DSDT.numamem.dsl 2020-12-23 15:55:12.287793832 +0800 @@ -9,9 +9,9 @@ * * Original Table Header: * Signature "DSDT" - * Length 0x0000144C (5196) + * Length 0x00001454 (5204) * Revision 0x02 - * Checksum 0xF0 + * Checksum 0x60 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1838,9 +1838,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) diff -ru /tmp/old/tests/data/acpi/virt/DSDT.pxb.dsl /tmp/new/tests/data/acpi/virt/DSDT.pxb.dsl --- /tmp/old/tests/data/acpi/virt/DSDT.pxb.dsl 2020-12-23 15:49:57.441096126 +0800 +++ /tmp/new/tests/data/acpi/virt/DSDT.pxb.dsl 2020-12-23 15:55:12.287793832 +0800 @@ -9,9 +9,9 @@ * * Original Table Header: * Signature "DSDT" - * Length 0x00001E7A (7802) + * Length 0x00001E09 (7689) * Revision 0x02 - * Checksum 0x57 + * Checksum 0x30 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -45,32 +45,6 @@ }) } - Device (FLS0) - { - Name (_HID, "LNRO0015") // _HID: Hardware ID - Name (_UID, Zero) // _UID: Unique ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0x00000000, // Address Base - 0x04000000, // Address Length - ) - }) - } - - Device (FLS1) - { - Name (_HID, "LNRO0015") // _HID: Hardware ID - Name (_UID, One) // _UID: Unique ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0x04000000, // Address Base - 0x04000000, // Address Length - ) - }) - } - Device (FWCF) { Name (_HID, "QEMU0002") // _HID: Hardware ID @@ -661,16 +635,15 @@ }) } - Device (PC80) + Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID - Name (_ADR, Zero) // _ADR: Address - Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_SEG, Zero) // _SEG: PCI Segment - Name (_BBN, 0x80) // _BBN: BIOS Bus Number - Name (_UID, 0x80) // _UID: Unique ID - Name (_STR, Unicode ("pxb Device")) // _STR: Description String + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, Zero) // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) @@ -1789,15 +1762,41 @@ } } + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity - 0x0080, // Range Minimum - 0x0080, // Range Maximum + 0x0000, // Range Minimum + 0x007F, // Range Maximum 0x0000, // Translation Offset - 0x0001, // Length + 0x0080, // Length ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) }) Name (SUPP, Zero) Name (CTRL, Zero) @@ -1808,8 +1807,8 @@ { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) - SUPP = CDW2 /* \_SB_.PC80._OSC.CDW2 */ - CTRL = CDW3 /* \_SB_.PC80._OSC.CDW3 */ + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ CTRL &= 0x1F If ((Arg1 != One)) { @@ -1821,7 +1820,7 @@ CDW1 |= 0x10 } - CDW3 = CTRL /* \_SB_.PC80.CTRL */ + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ Return (Arg3) } Else @@ -1839,9 +1838,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) @@ -1849,17 +1853,30 @@ 0x00 // . }) } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } } - Device (PCI0) + Device (PC80) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID - Name (_SEG, Zero) // _SEG: PCI Segment - Name (_BBN, Zero) // _BBN: BIOS Bus Number - Name (_UID, "PCI0") // _UID: Unique ID - Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String - Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_BBN, 0x80) // _BBN: BIOS Bus Number + Name (_UID, 0x80) // _UID: Unique ID + Name (_STR, Unicode ("pxb Device")) // _STR: Description String Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) @@ -2978,46 +2995,16 @@ } } - Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address - { - Return (0x0000004010000000) - } - - Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { - Return (ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x007F, // Range Maximum - 0x0000, // Translation Offset - 0x0080, // Length - ,, ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0x10000000, // Range Minimum - 0x3EFEFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x2EFF0000, // Length - ,, , AddressRangeMemory, TypeStatic) - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Granularity - 0x00000000, // Range Minimum - 0x0000FFFF, // Range Maximum - 0x3EFF0000, // Translation Offset - 0x00010000, // Length - ,, , TypeStatic, DenseTranslation) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000008000000000, // Range Minimum - 0x000000FFFFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000008000000000, // Length - ,, , AddressRangeMemory, TypeStatic) - }) - } - + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0080, // Range Minimum + 0x0080, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) Name (SUPP, Zero) Name (CTRL, Zero) Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities @@ -3027,8 +3014,8 @@ { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) - SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ - CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + SUPP = CDW2 /* \_SB_.PC80._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PC80._OSC.CDW3 */ CTRL &= 0x1F If ((Arg1 != One)) { @@ -3040,7 +3027,7 @@ CDW1 |= 0x10 } - CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + CDW3 = CTRL /* \_SB_.PC80.CTRL */ Return (Arg3) } Else @@ -3058,9 +3045,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) @@ -3068,21 +3060,6 @@ 0x00 // . }) } - - Device (RES0) - { - Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000004010000000, // Range Minimum - 0x000000401FFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length - ,, , AddressRangeMemory, TypeStatic) - }) - } } Device (\_SB.GED) Signed-off-by: Jiahui Cen --- tests/data/acpi/microvm/DSDT.pcie | Bin 3023 -> 3031 bytes tests/data/acpi/virt/DSDT | Bin 5196 -> 5204 bytes tests/data/acpi/virt/DSDT.memhp | Bin 6557 -> 6565 bytes tests/data/acpi/virt/DSDT.numamem | Bin 5196 -> 5204 bytes tests/data/acpi/virt/DSDT.pxb | Bin 7802 -> 7689 bytes tests/qtest/bios-tables-test-allowed-diff.h | 5 ----- 6 files changed, 5 deletions(-) diff --git a/tests/data/acpi/microvm/DSDT.pcie b/tests/data/acpi/microvm/DSDT.pcie index 4b765541e372f4ba4e25529c14acf696516c8f61..e590b98f9960025f75dd0544492d3088781406dc 100644 GIT binary patch delta 59 zcmV-B0L1^#7uOdGL{mgm*9!mu0-2Et8v;SPu_reH0Z6l70pke>HD5$iO$4ARlS&I8 R2_c{dlWGbDqyUp@3uOk*5ZC|! delta 51 zcmcaEeqNl*CDBB@WX~y=AYLc8xe#;j-a&mF##=8XjvMf-X>?thI$T+!B G_%Q%yeGTXU diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp index 54728e2b4b8b959f3f829386f6a388ef2600e747..897648637cc6c8af47c67a9a349477c0240f833b 100644 GIT binary patch delta 60 zcmV-C0K@;CGo>>ML{mgmr5OMK0+5jk8v=lsu_qV_0!FB#K?w>7HD5$iO$4ARlSvaF S2_c{dlWGbDqyV#N6Ep_<;t(eQ delta 52 zcmZ2#JlB}ZCDBB@WX~y=AYLc8xe#;j-a&mF##=8XjvMf-X>?thI$T+!B G_%Q%yeGTXU diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb index d5f0533a02d62bc2ae2db9b9de9484e5c06652fe..f380e6023e7fc209a43280d71bf8a91286e35b63 100644 GIT binary patch delta 127 zcmexm(`m!y66_MfDaXLTWH6CSnyKa9MD>J?Z+CF8x~&Ls_ME(mQ+{%XF#qN`!fQEL zIpUpzf;R`r$TD)6#=8XjvMkV?Y%46!sknfBauyfs5{AjsWy2VqCokhv-h7)giW5Z@ QFI?3UL1xCuuVg0x0IJI-00000 delta 259 zcmeCQ`DMf966_LECC9+P6h4tlnyK~aMD>JvLpPsb1CDqPPZwSvzaW1D14B~=j`&bd z7a-{z6f7vn#n;Bkz{mgrER_t=O&~3X*t9UBYheNE0&B5w3wL&dXbE)n4K*+@Fanw% z9OAff!F&!z-^nM0mH8cAf