From patchwork Thu Dec 24 11:16:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8808C433E0 for ; Thu, 24 Dec 2020 11:18:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D2C1207A5 for ; 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Thu, 24 Dec 2020 05:16:44 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:43 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:43 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWG7116630; Thu, 24 Dec 2020 05:16:38 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 01/15] phy: cadence: Sierra: Fix PHY power_on sequence Date: Thu, 24 Dec 2020 16:46:13 +0530 Message-ID: <20201224111627.32590-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061646_664516_574E36B4 X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I Cc: # v5.4+ --- drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 26a0badabe38..19f32ae877b9 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -319,6 +319,12 @@ static int cdns_sierra_phy_on(struct phy *gphy) u32 val; int ret; + ret = reset_control_deassert(sp->phy_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY out of reset\n"); + return ret; + } + /* Take the PHY lane group out of reset */ ret = reset_control_deassert(ins->lnk_rst); if (ret) { @@ -616,7 +622,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - reset_control_deassert(sp->phy_rst); return PTR_ERR_OR_ZERO(phy_provider); put_child: From patchwork Thu Dec 24 11:16:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CE4BC433E6 for ; Thu, 24 Dec 2020 11:18:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C58C3207A5 for ; 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Thu, 24 Dec 2020 05:16:50 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:50 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:50 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWG8116630; Thu, 24 Dec 2020 05:16:44 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 02/15] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Date: Thu, 24 Dec 2020 16:46:14 +0530 Message-ID: <20201224111627.32590-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061652_587809_46215D3C X-CRM114-Status: GOOD ( 13.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Invoke wiz_init() before configuring anything else in Sierra/Torrent (invoked as part of of_platform_device_create()). wiz_init() resets the SERDES device and any configuration done in the probe() of Sierra/Torrent will be lost. In order to prevent SERDES configuration from getting reset, invoke wiz_init() immediately before invoking of_platform_device_create(). Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I Cc: # v5.10 --- drivers/phy/ti/phy-j721e-wiz.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c9cfafe89cbf..a75433b459dd 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -947,27 +947,24 @@ static int wiz_probe(struct platform_device *pdev) goto err_get_sync; } + ret = wiz_init(wiz); + if (ret) { + dev_err(dev, "WIZ initialization failed\n"); + goto err_wiz_init; + } + serdes_pdev = of_platform_device_create(child_node, NULL, dev); if (!serdes_pdev) { dev_WARN(dev, "Unable to create SERDES platform device\n"); ret = -ENOMEM; - goto err_pdev_create; - } - wiz->serdes_pdev = serdes_pdev; - - ret = wiz_init(wiz); - if (ret) { - dev_err(dev, "WIZ initialization failed\n"); goto err_wiz_init; } + wiz->serdes_pdev = serdes_pdev; of_node_put(child_node); return 0; err_wiz_init: - of_platform_device_destroy(&serdes_pdev->dev, NULL); - -err_pdev_create: wiz_clock_cleanup(wiz, node); err_get_sync: From patchwork Thu Dec 24 11:16:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96AC8C433E0 for ; Thu, 24 Dec 2020 11:18:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 57F9D207A5 for ; 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Thu, 24 Dec 2020 05:16:55 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:55 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:55 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWG9116630; Thu, 24 Dec 2020 05:16:51 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 03/15] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Date: Thu, 24 Dec 2020 16:46:15 +0530 Message-ID: <20201224111627.32590-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061657_934283_079F9CFD X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add binding for the PLLs within SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-cadence-sierra.yaml | 89 ++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index d210843863df..f574b8ed358c 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -49,12 +49,14 @@ properties: const: serdes clocks: - maxItems: 2 + maxItems: 4 clock-names: items: - const: cmn_refclk_dig_div - const: cmn_refclk1_dig_div + - const: pll_cmnlc + - const: pll_cmnlc1 cdns,autoconf: type: boolean @@ -107,6 +109,58 @@ patternProperties: additionalProperties: false + "^refrcv1?$": + type: object + description: | + Reference receivers that enables routing external clocks to the alternate + PLLCMNLC. + properties: + clocks: + maxItems: 1 + description: Phandle to clock nodes representing the input to the + reference receiver. + + clock-names: + items: + - const: pll_refclk + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + + "^pll_cmnlc1?$": + type: object + description: | + SERDES node should have subnodes for each of the PLLs present in + the SERDES. + properties: + clocks: + maxItems: 2 + description: Phandle to clock nodes representing the two inputs to PLL. + + clock-names: + items: + - const: pll_refclk + - const: refrcv + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + required: - compatible - "#address-cells" @@ -130,10 +184,39 @@ examples: reg = <0x0 0xfd240000 0x0 0x40000>; resets = <&phyrst 0>, <&phyrst 1>; reset-names = "sierra_reset", "sierra_apb"; - clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>, <&serdes_pll_cmnlc>, <&serdes_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; #address-cells = <1>; #size-cells = <0>; + + serdes_refrcv: refrcv { + clocks = <&pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_refrcv1: refrcv1 { + clocks = <&pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_pll_cmnlc: pll_cmnlc { + clocks = <&pll0_refclk>, <&serdes_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc>; + assigned-clock-parents = <&pll0_refclk>; + }; + + serdes_pll_cmnlc1: pll_cmnlc1 { + clocks = <&pll1_refclk>, <&serdes_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc1>; + assigned-clock-parents = <&pll1_refclk>; + }; + pcie0_phy0: phy@0 { reg = <0>; resets = <&phyrst 2>; From patchwork Thu Dec 24 11:16:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D67F4C433E0 for ; Thu, 24 Dec 2020 11:18:43 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 99465207A5 for ; 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Thu, 24 Dec 2020 05:17:00 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:59 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:59 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGA116630; Thu, 24 Dec 2020 05:16:55 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 04/15] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Date: Thu, 24 Dec 2020 16:46:16 +0530 Message-ID: <20201224111627.32590-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061701_690184_17DF6A64 X-CRM114-Status: GOOD ( 12.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org "serdes" node (child node of WIZ) can have sub-nodes for representing links or it can have sub-nodes for representing the various clocks within the serdes. Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy" or "link" subnode. Ideally all PHY dt nodes should have node name as "phy", however existing devicetree used "link" as subnode. So in order to maintain old DT compatibility get PHY properties for "phy" or "link" subnode. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index a75433b459dd..2a03191eac64 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -787,6 +787,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) u32 reg, num_lanes = 1, phy_type = PHY_NONE; int ret, i; + if (!(of_node_name_eq(subnode, "phy") || + of_node_name_eq(subnode, "link"))) + continue; + ret = of_property_read_u32(subnode, "reg", ®); if (ret) { dev_err(dev, From patchwork Thu Dec 24 11:16:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5191DC433DB for ; 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Thu, 24 Dec 2020 05:17:00 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 05/15] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Date: Thu, 24 Dec 2020 16:46:17 +0530 Message-ID: <20201224111627.32590-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061707_501368_9E9A4E41 X-CRM114-Status: GOOD ( 11.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 19f32ae877b9..f7ba0ed416bc 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -577,6 +577,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dn, child) { struct phy *gphy; + if (!(of_node_name_eq(child, "phy") || + of_node_name_eq(child, "link"))) + continue; + sp->phys[node].lnk_rst = of_reset_control_array_get_exclusive(child); From patchwork Thu Dec 24 11:16:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07AA8C43381 for ; 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Thu, 24 Dec 2020 05:17:05 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 06/15] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Date: Thu, 24 Dec 2020 16:46:18 +0530 Message-ID: <20201224111627.32590-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061710_721137_7DC26C63 X-CRM114-Status: GOOD ( 15.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++--------- 1 file changed, 35 insertions(+), 22 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index f7ba0ed416bc..7bf1b4c7774a 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -477,6 +477,38 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get_optional(dev, "phy_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clock phy_clk\n"); + return PTR_ERR(clk); + } + sp->clk = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk_dig_div = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1_dig_div = clk; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -487,7 +519,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) unsigned int id_value; int i, ret, node = 0; void __iomem *base; - struct clk *clk; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) @@ -524,11 +555,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get_optional(dev, "phy_clk"); - if (IS_ERR(sp->clk)) { - dev_err(dev, "failed to get clock phy_clk\n"); - return PTR_ERR(sp->clk); - } + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + return ret; sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); if (IS_ERR(sp->phy_rst)) { @@ -542,22 +571,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->apb_rst); } - clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk_dig_div = clk; - - clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk1_dig_div = clk; - ret = clk_prepare_enable(sp->clk); if (ret) return ret; From patchwork Thu Dec 24 11:16:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B67C433E0 for ; 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Thu, 24 Dec 2020 05:17:09 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 07/15] phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function Date: Thu, 24 Dec 2020 16:46:19 +0530 Message-ID: <20201224111627.32590-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061715_979009_FFF2DE68 X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 36 ++++++++++++++++-------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 7bf1b4c7774a..935f165404e4 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -509,6 +509,28 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct reset_control *rst; + + rst = devm_reset_control_get(dev, "sierra_reset"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get reset\n"); + return PTR_ERR(rst); + } + sp->phy_rst = rst; + + rst = devm_reset_control_get_optional(dev, "sierra_apb"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get apb reset\n"); + return PTR_ERR(rst); + } + sp->apb_rst = rst; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -559,17 +581,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); - if (IS_ERR(sp->phy_rst)) { - dev_err(dev, "failed to get reset\n"); - return PTR_ERR(sp->phy_rst); - } - - sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); - if (IS_ERR(sp->apb_rst)) { - dev_err(dev, "failed to get apb reset\n"); - return PTR_ERR(sp->apb_rst); - } + ret = cdns_sierra_phy_get_resets(sp, dev); + if (ret) + return ret; ret = clk_prepare_enable(sp->clk); if (ret) From patchwork Thu Dec 24 11:16:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAFAAC433DB for ; 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Thu, 24 Dec 2020 05:17:15 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 08/15] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Date: Thu, 24 Dec 2020 16:46:20 +0530 Message-ID: <20201224111627.32590-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061721_439272_FB7D939A X-CRM114-Status: GOOD ( 13.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 935f165404e4..44c52a0842dc 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -514,14 +514,14 @@ static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, { struct reset_control *rst; - rst = devm_reset_control_get(dev, "sierra_reset"); + rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); if (IS_ERR(rst)) { dev_err(dev, "failed to get reset\n"); return PTR_ERR(rst); } sp->phy_rst = rst; - rst = devm_reset_control_get_optional(dev, "sierra_apb"); + rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); if (IS_ERR(rst)) { dev_err(dev, "failed to get apb reset\n"); return PTR_ERR(rst); From patchwork Thu Dec 24 11:16:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D836C433E6 for ; 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Thu, 24 Dec 2020 05:17:23 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGF116630; Thu, 24 Dec 2020 05:17:19 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 09/15] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Date: Thu, 24 Dec 2020 16:46:21 +0530 Message-ID: <20201224111627.32590-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061726_384323_34401FE6 X-CRM114-Status: GOOD ( 23.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Sierra has two reference recievers REFRCV and REFRCV1. REFRCV is used to drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to be able to seamlessly use any of the external reference clocks. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/Kconfig | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 209 ++++++++++++++++++++++- 2 files changed, 207 insertions(+), 3 deletions(-) diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 432832bdbd16..23d5382c34ed 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -24,6 +24,7 @@ config PHY_CADENCE_DPHY config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on OF && HAS_IOMEM && RESET_CONTROLLER + depends on COMMON_CLK select GENERIC_PHY help Enable this to support the Cadence Sierra PHY driver diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 44c52a0842dc..8b7b2a838f5f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -7,6 +7,7 @@ * */ #include +#include #include #include #include @@ -31,6 +32,8 @@ #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 +#define SIERRA_CMN_REFRCV_PREG 0x98 +#define SIERRA_CMN_REFRCV1_PREG 0xB8 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -151,6 +154,35 @@ static const struct reg_field phy_pll_cfg_1 = static const struct reg_field pllctrl_lock = REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); +enum cdns_sierra_cmn_refrcv { + CMN_REFRCV, + CMN_REFRCV1, +}; + +#define SIERRA_NUM_REFRCV 0x2 + +static const struct reg_field cmn_refrcv_refclk_plllc1en_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), +}; + +static const struct reg_field cmn_refrcv_refclk_termen_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), +}; + +static char *refrcv_node_name[] = { "refrcv", "refrcv1" }; + +struct cdns_sierra_refrcv { + struct clk_hw hw; + struct regmap_field *plllc1en_field; + struct regmap_field *termen_field; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_refrcv(_hw) \ + container_of(_hw, struct cdns_sierra_refrcv, hw) + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -197,6 +229,8 @@ struct cdns_sierra_phy { struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; + struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -364,6 +398,146 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static int cdns_sierra_refrcv_enable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 1); + regmap_field_write(termen_field, 1); + + return 0; +} + +static void cdns_sierra_refrcv_disable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 0); + regmap_field_write(termen_field, 0); +} + +static int cdns_sierra_refrcv_is_enabled(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + int val; + + regmap_field_read(plllc1en_field, &val); + + return !!val; +} + +static const struct clk_ops cdns_sierra_refrcv_ops = { + .enable = cdns_sierra_refrcv_enable, + .disable = cdns_sierra_refrcv_disable, + .is_enabled = cdns_sierra_refrcv_is_enabled, +}; + +static int cdns_sierra_refrcv_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *plllc1en_field, + struct regmap_field *termen_field) +{ + struct cdns_sierra_refrcv *refrcv; + struct device *dev = sp->dev; + struct clk_init_data *init; + unsigned int num_parents; + const char *parent_name; + char clk_name[100]; + struct clk *clk; + int ret; + + refrcv = devm_kzalloc(dev, sizeof(*refrcv), GFP_KERNEL); + if (!refrcv) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + parent_name = of_clk_get_parent_name(node, 0); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &refrcv->clk_data; + + init->ops = &cdns_sierra_refrcv_ops; + init->flags = 0; + init->parent_names = parent_name ? &parent_name : NULL; + init->num_parents = num_parents ? 1 : 0; + init->name = clk_name; + + refrcv->plllc1en_field = plllc1en_field; + refrcv->termen_field = termen_field; + refrcv->hw.init = init; + + clk = devm_clk_register(dev, &refrcv->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add refrcv clock provider: %s\n", + clk_name); + + return ret; +} + +static void cdns_sierra_refrcv_unregister(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct device_node *of_node; + int i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(node, refrcv_node_name[i]); + if (!of_node) + return; + + of_clk_del_provider(of_node); + of_node_put(of_node); + } +} + +static int cdns_sierra_phy_register_refrcv(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct regmap_field *plllc1en_field; + struct device_node *of_node = NULL; + struct regmap_field *termen_field; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(node, refrcv_node_name[i]); + if (!of_node) + return 0; + + plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; + termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; + + ret = cdns_sierra_refrcv_register(sp, of_node, plllc1en_field, + termen_field); + if (ret) { + dev_err(dev, "Fail to register reference receiver %s\n", + refrcv_node_name[i]); + of_node_put(of_node); + goto err; + } + + of_node_put(of_node); + } + + return 0; + +err: + cdns_sierra_refrcv_unregister(sp, node); + + return ret; +} + static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { @@ -402,6 +576,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) { struct device *dev = sp->dev; struct regmap_field *field; + struct reg_field reg_field; struct regmap *regmap; int i; @@ -413,6 +588,24 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) } sp->macro_id_type = field; + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + reg_field = cmn_refrcv_refclk_plllc1en_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; + + reg_field = cmn_refrcv_refclk_termen_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_termen_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -577,17 +770,21 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - ret = cdns_sierra_phy_get_clocks(sp, dev); + ret = cdns_sierra_phy_register_refrcv(sp, dn); if (ret) return ret; + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + goto unregister_refrcv; + ret = cdns_sierra_phy_get_resets(sp, dev); if (ret) - return ret; + goto unregister_refrcv; ret = clk_prepare_enable(sp->clk); if (ret) - return ret; + goto unregister_refrcv; /* Enable APB */ reset_control_deassert(sp->apb_rst); @@ -664,12 +861,17 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) clk_disable: clk_disable_unprepare(sp->clk); reset_control_assert(sp->apb_rst); +unregister_refrcv: + cdns_sierra_refrcv_unregister(sp, dn); + return ret; } static int cdns_sierra_phy_remove(struct platform_device *pdev) { struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct device_node *dn = dev->of_node; int i; reset_control_assert(phy->phy_rst); @@ -684,6 +886,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->phys[i].lnk_rst); reset_control_put(phy->phys[i].lnk_rst); } + cdns_sierra_refrcv_unregister(phy, dn); return 0; } From patchwork Thu Dec 24 11:16:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A891CC433E0 for ; Thu, 24 Dec 2020 11:20:16 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4F7DF207A5 for ; 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Thu, 24 Dec 2020 05:17:28 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:28 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:28 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGG116630; Thu, 24 Dec 2020 05:17:24 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 10/15] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Date: Thu, 24 Dec 2020 16:46:22 +0530 Message-ID: <20201224111627.32590-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061730_435062_600AB41A X-CRM114-Status: GOOD ( 21.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 188 ++++++++++++++++++++++- 1 file changed, 185 insertions(+), 3 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 8b7b2a838f5f..2a509be80c80 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -25,6 +25,7 @@ /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET 0x0 #define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A @@ -34,6 +35,7 @@ #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 #define SIERRA_CMN_REFRCV_PREG 0x98 #define SIERRA_CMN_REFRCV1_PREG 0xB8 +#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -183,6 +185,36 @@ struct cdns_sierra_refrcv { #define to_cdns_sierra_refrcv(_hw) \ container_of(_hw, struct cdns_sierra_refrcv, hw) +enum cdns_sierra_cmn_plllc { + CMN_PLLLC, + CMN_PLLLC1, +}; + +#define SIERRA_NUM_CMN_PLLC 0x2 + +static const struct reg_field cmn_plllc_pfdclk1_sel_preg[] = { + [CMN_PLLLC] = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), + [CMN_PLLLC1] = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), +}; + +static char *cmn_plllc_node_name[] = { "pll_cmnlc", "pll_cmnlc1" }; + +struct cdns_sierra_pll_mux { + struct clk_hw hw; + struct regmap_field *pfdclk_sel_preg; + u32 *table; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_pll_mux(_hw) \ + container_of(_hw, struct cdns_sierra_pll_mux, hw) + +/* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ +static u32 cdns_sierra_pll_mux_table[] = { 0, 1 }; + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -231,6 +263,7 @@ struct cdns_sierra_phy { struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -398,6 +431,138 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, mux->table, 0, val); +} + +static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + int val; + + val = mux->table[index]; + return regmap_field_write(field, val); +} + +static const struct clk_ops cdns_sierra_pll_mux_ops = { + .set_parent = cdns_sierra_pll_mux_set_parent, + .get_parent = cdns_sierra_pll_mux_get_parent, +}; + +static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *field) +{ + struct cdns_sierra_pll_mux *mux; + struct device *dev = sp->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + char clk_name[100]; + struct clk *clk; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &mux->clk_data; + + init->ops = &cdns_sierra_pll_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->pfdclk_sel_preg = field; + mux->table = cdns_sierra_pll_mux_table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Fail to add pll mux clock provider: %s\n", + clk_name); + + return ret; +} + +static void cdns_sierra_pll_mux_unregister(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct device_node *of_node; + int i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(node, cmn_plllc_node_name[i]); + if (!of_node) + return; + + of_clk_del_provider(of_node); + of_node_put(of_node); + } +} + +static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct regmap_field *pfdclk1_sel_field; + struct device_node *of_node = NULL; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(node, cmn_plllc_node_name[i]); + if (!of_node) + return 0; + + pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; + ret = cdns_sierra_pll_mux_register(sp, of_node, + pfdclk1_sel_field); + if (ret) { + dev_err(dev, "Fail to register cmn plllc mux %s\n", + cmn_plllc_node_name[i]); + of_node_put(of_node); + goto err; + } + + of_node_put(of_node); + } + + return 0; + +err: + cdns_sierra_pll_mux_unregister(sp, node); + + return 0; +} + static int cdns_sierra_refrcv_enable(struct clk_hw *hw) { struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); @@ -606,6 +771,16 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) sp->cmn_refrcv_refclk_termen_preg[i] = field; } + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + reg_field = cmn_plllc_pfdclk1_sel_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); + return PTR_ERR(field); + } + sp->cmn_plllc_pfdclk1_sel_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -774,17 +949,21 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - ret = cdns_sierra_phy_get_clocks(sp, dev); + ret = cdns_sierra_phy_register_pll_mux(sp, dn); if (ret) goto unregister_refrcv; + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + goto unregister_pll_mux; + ret = cdns_sierra_phy_get_resets(sp, dev); if (ret) - goto unregister_refrcv; + goto unregister_pll_mux; ret = clk_prepare_enable(sp->clk); if (ret) - goto unregister_refrcv; + goto unregister_pll_mux; /* Enable APB */ reset_control_deassert(sp->apb_rst); @@ -861,6 +1040,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) clk_disable: clk_disable_unprepare(sp->clk); reset_control_assert(sp->apb_rst); +unregister_pll_mux: + cdns_sierra_pll_mux_unregister(sp, dn); unregister_refrcv: cdns_sierra_refrcv_unregister(sp, dn); @@ -886,6 +1067,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->phys[i].lnk_rst); reset_control_put(phy->phys[i].lnk_rst); } + cdns_sierra_pll_mux_unregister(phy, dn); cdns_sierra_refrcv_unregister(phy, dn); return 0; } From patchwork Thu Dec 24 11:16:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA42C433E0 for ; Thu, 24 Dec 2020 11:20:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF6A3207A5 for ; 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Thu, 24 Dec 2020 05:17:33 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:32 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:32 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGH116630; Thu, 24 Dec 2020 05:17:29 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 11/15] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Date: Thu, 24 Dec 2020 16:46:23 +0530 Message-ID: <20201224111627.32590-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061734_990916_2379870C X-CRM114-Status: GOOD ( 16.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 2a509be80c80..ad0ea74515d6 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -267,6 +267,8 @@ struct cdns_sierra_phy { struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; + struct clk *pll_cmnlc; + struct clk *pll_cmnlc1; int nsubnodes; u32 num_lanes; bool autoconf; @@ -874,9 +876,59 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, } sp->cmn_refclk1_dig_div = clk; + clk = devm_clk_get_optional(dev, "pll_cmnlc"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc = clk; + + clk = devm_clk_get_optional(dev, "pll_cmnlc1"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc1 clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc1 = clk; + return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->clk); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->pll_cmnlc); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->pll_cmnlc1); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc: + clk_disable_unprepare(sp->clk); + +err_pll_cmnlc1: + clk_disable_unprepare(sp->pll_cmnlc); + + return 0; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->pll_cmnlc1); + clk_disable_unprepare(sp->pll_cmnlc); + clk_disable_unprepare(sp->clk); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -961,7 +1013,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_pll_mux; - ret = clk_prepare_enable(sp->clk); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_pll_mux; @@ -1038,7 +1090,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->clk); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_pll_mux: cdns_sierra_pll_mux_unregister(sp, dn); @@ -1059,6 +1111,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. From patchwork Thu Dec 24 11:16:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA84FC433DB for ; Thu, 24 Dec 2020 11:21:00 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63D8C207A5 for ; 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Thu, 24 Dec 2020 05:17:37 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:37 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:37 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGI116630; Thu, 24 Dec 2020 05:17:33 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Date: Thu, 24 Dec 2020 16:46:24 +0530 Message-ID: <20201224111627.32590-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061739_956796_6E6674F4 X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DT nodes for clocks within Sierra SERDES. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 ++++++++++++++++++++-- 1 file changed, 120 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2d526ea44a85..9d1edce31829 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -400,8 +400,36 @@ #size-cells = <0>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes0_refrcv: refrcv { + clocks = <&wiz0_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_refrcv1: refrcv1 { + clocks = <&wiz0_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_pll_cmnlc: pll_cmnlc { + clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&wiz0_pll0_refclk>; + }; + + serdes0_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc1>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + }; }; }; @@ -457,8 +485,36 @@ #size-cells = <0>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes1_refrcv: refrcv { + clocks = <&wiz1_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_refrcv1: refrcv1 { + clocks = <&wiz1_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_pll_cmnlc: pll_cmnlc { + clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&wiz1_pll0_refclk>; + }; + + serdes1_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc1>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + }; }; }; @@ -514,8 +570,36 @@ #size-cells = <0>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes2_refrcv: refrcv { + clocks = <&wiz2_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_refrcv1: refrcv1 { + clocks = <&wiz2_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_pll_cmnlc: pll_cmnlc { + clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&wiz2_pll0_refclk>; + }; + + serdes2_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc1>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + }; }; }; @@ -571,8 +655,36 @@ #size-cells = <0>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&serdes3_pll_cmnlc>, <&serdes3_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes3_refrcv: refrcv { + clocks = <&wiz3_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_refrcv1: refrcv1 { + clocks = <&wiz3_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_pll_cmnlc: pll_cmnlc { + clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc>; + assigned-clock-parents = <&wiz3_pll0_refclk>; + }; + + serdes3_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc1>; + assigned-clock-parents = <&wiz3_pll1_refclk>; + }; }; }; From patchwork Thu Dec 24 11:16:25 2020 Content-Type: text/plain; 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Thu, 24 Dec 2020 05:17:42 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:42 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:42 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGJ116630; Thu, 24 Dec 2020 05:17:38 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 13/15] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Date: Thu, 24 Dec 2020 16:46:25 +0530 Message-ID: <20201224111627.32590-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061744_425407_243EF125 X-CRM114-Status: GOOD ( 12.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Rename the external refclk inputs to the SERDES from dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1 respectively. Also move the external refclk DT nodes outside the cbass_main DT node. Since in j721e common processor board, only the cmn_refclk1 is connected to 100MHz clock, fix the clock frequency. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 4 ++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++++++++++--------- 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 60764366e22b..86f7ab511ee8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -635,6 +635,10 @@ status = "disabled"; }; +&cmn_refclk1 { + clock-frequency = <100000000>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 9d1edce31829..20cb390d33b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -8,6 +8,20 @@ #include #include +/ { + cmn_refclk: cmn-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cmn_refclk1: cmn-refclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -336,24 +350,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; - dummy_cmn_refclk: dummy-cmn-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - dummy_cmn_refclk1: dummy-cmn-refclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; @@ -362,21 +364,21 @@ ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; @@ -438,7 +440,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; @@ -447,21 +449,21 @@ ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; @@ -523,7 +525,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; @@ -532,21 +534,21 @@ ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; @@ -608,7 +610,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; @@ -617,21 +619,21 @@ ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; From patchwork Thu Dec 24 11:16:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C82BC433E0 for ; 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Thu, 24 Dec 2020 05:17:43 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 14/15] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Date: Thu, 24 Dec 2020 16:46:26 +0530 Message-ID: <20201224111627.32590-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061749_050252_DC0BF3BD X-CRM114-Status: GOOD ( 11.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use external clock for all the SERDES used by PCIe controller. This will make the same clock used by the local SERDES as well as the clock provided to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 86f7ab511ee8..788126daf91c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -639,6 +639,51 @@ clock-frequency = <100000000>; }; +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes0_pll_cmnlc { + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&serdes0_refrcv1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes1_pll_cmnlc { + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&serdes1_refrcv1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes2_pll_cmnlc { + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&serdes2_refrcv1>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; From patchwork Thu Dec 24 11:16:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11989475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 820F5C433E0 for ; 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Thu, 24 Dec 2020 05:17:47 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 15/15] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Date: Thu, 24 Dec 2020 16:46:27 +0530 Message-ID: <20201224111627.32590-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061753_591257_D964C128 X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") and commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") added PHY DT nodes with node name as "link" However nodes with #phy-cells should be named 'phy' as discussed in [1]. Re-name subnodes of serdes in J721E to 'phy'. [1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 788126daf91c..13ae0d89caf2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -358,7 +358,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -685,7 +685,7 @@ }; &serdes0 { - serdes0_pcie_link: link@0 { + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -695,7 +695,7 @@ }; &serdes1 { - serdes1_pcie_link: link@0 { + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -705,7 +705,7 @@ }; &serdes2 { - serdes2_pcie_link: link@0 { + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>;