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Thu, 24 Dec 2020 17:20:57 -0800 (PST) From: Peter Geis To: Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Jaroslav Kysela , Takashi Iwai , Sameer Pujar , Mohan Kumar Subject: [PATCH 1/2] clk: tegra30: Add hda clock default rates to clock driver Date: Fri, 25 Dec 2020 01:20:25 +0000 Message-Id: <20201225012025.507803-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201225012025.507803-1-pgwipeout@gmail.com> References: <20201225012025.507803-1-pgwipeout@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Ion Agorria , Peter Geis , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Current implementation defaults the hda clocks to clk_m. This causes hda to run too slow to operate correctly. Fix this by defaulting to pll_p and setting the frequency to the correct rate. This matches upstream t124 and downstream t30. Signed-off-by: Peter Geis Tested-by: Ion Agorria Acked-by: Jon Hunter --- drivers/clk/tegra/clk-tegra30.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..9cf249c344d9 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1256,6 +1256,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, }; From patchwork Fri Dec 25 01:20:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 11989789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DB09C433E0 for ; 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Thu, 24 Dec 2020 17:20:59 -0800 (PST) Received: from rockpro64.hsd1.md.comcast.net ([2601:153:900:7730::20]) by smtp.gmail.com with ESMTPSA id x47sm17583505qtb.86.2020.12.24.17.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Dec 2020 17:20:59 -0800 (PST) From: Peter Geis To: Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Jaroslav Kysela , Takashi Iwai , Sameer Pujar , Mohan Kumar Subject: [PATCH 2/2] ALSA: hda/tegra: fix tegra-hda on tegra30 soc Date: Fri, 25 Dec 2020 01:20:26 +0000 Message-Id: <20201225012025.507803-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201225012025.507803-1-pgwipeout@gmail.com> References: <20201225012025.507803-1-pgwipeout@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Ion Agorria , Peter Geis , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Currently hda on tegra30 fails to open a stream with an input/output error. This is similar to the issue referenced in [1]. For example: speaker-test -Dhw:0,3 -c 2 speaker-test 1.2.2 Playback device is hw:0,3 Stream parameters are 48000Hz, S16_LE, 2 channels Using 16 octaves of pink noise Rate set to 48000Hz (requested 48000Hz) Buffer size range from 64 to 16384 Period size range from 32 to 8192 Using max buffer size 16384 Periods = 4 was set period_size = 4096 was set buffer_size = 16384 0 - Front Left Write error: -5,Input/output error xrun_recovery failed: -5,Input/output error Transfer failed: Input/output error [1] states "Due to a legacy HW design problem", implying the issue applies to all previous tegra-hda devices. The tegra-hda device was introduced in tegra30 but only utilized in tegra124 until now. For this reason it is unknown when this issue first manifested. Applying the fix in [1] universally resolves this issue on tegra30. Tested on the Ouya game console and the tf201 tablet. [1] 60019d8c650d ("ALSA: hda/tegra: workaround playback failure on Tegra194") Signed-off-by: Peter Geis Tested-by: Ion Agorria Reviewed-by: Jon Hunter --- sound/pci/hda/hda_tegra.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index 70164d1428d4..f8d61e677a09 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -388,8 +388,7 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) * in powers of 2, next available ratio is 16 which can be * used as a limiting factor here. */ - if (of_device_is_compatible(np, "nvidia,tegra194-hda")) - chip->bus.core.sdo_limit = 16; + chip->bus.core.sdo_limit = 16; /* codec detection */ if (!bus->codec_mask) {