From patchwork Mon Dec 28 02:59:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qing Zhang X-Patchwork-Id: 11990817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4796C4332B for ; Mon, 28 Dec 2020 03:00:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A805B221F0 for ; Mon, 28 Dec 2020 03:00:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726477AbgL1DAe (ORCPT ); Sun, 27 Dec 2020 22:00:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]:38130 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726337AbgL1DAe (ORCPT ); Sun, 27 Dec 2020 22:00:34 -0500 Received: from linux.localdomain (unknown [113.200.148.30]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxHzYdSulfznIGAA--.9S2; Mon, 28 Dec 2020 10:59:42 +0800 (CST) From: Qing Zhang To: Mark Brown , Rob Herring , ThomasBogendoerfer Cc: linux-spi@vger.kernel.org, Huacai Chen , Jiaxun Yang , yangtiezhu@loongson.cn, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/4] spi: LS7A: Add Loongson LS7A SPI controller driver support Date: Mon, 28 Dec 2020 10:59:38 +0800 Message-Id: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> X-Mailer: git-send-email 2.1.0 X-CM-TRANSID: AQAAf9DxHzYdSulfznIGAA--.9S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Zw1xJrWUJF1DGry3CryxAFb_yoWDWFWrpa 18W3yrta18JFyrArZrJF4UWFy5Xw4Sq34fX3y3t348KFyYqF4DWF1FqryfArZxJFWxuFyU XFnF9rWYgF45ZaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9Y14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F 4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02 628vn2kIc2xKxwCY02Avz4vE14v_Gr1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7 v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF 1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIx AIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWrJr0_WFyU JwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCT nIWIevJa73UjIFyTuYvjfU5CztUUUUU X-CM-SenderInfo: x2kd0wptlqwqxorr0wxvrqhubq/ Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The SPI controller has the following characteristics: - Full-duplex synchronous serial data transmission - Support up to 4 variable length byte transmission - Main mode support - Mode failure generates an error flag and issues an interrupt request - Double buffer receiver - Serial clock with programmable polarity and phase - SPI can be controlled in wait mode - Support boot from SPI Use mtd_debug tool to earse/write/read /dev/mtd0 on development. eg: [root@linux mtd-utils-1.0.0]# mtd_debug erase /dev/mtd0 0x20000 0x40000 Erased 262144 bytes from address 0x00020000 in flash [root@linux mtd-utils-1.0.0]# mtd_debug write /dev/mtd0 0x20000 13 1.img Copied 13 bytes from 1.img to address 0x00020000 in flash [root@linux mtd-utils-1.0.0]# mtd_debug read /dev/mtd0 0x20000 13 2.img Copied 13 bytes from address 0x00020000 in flash to 2.img [root@linux mtd-utils-1.0.0]# cmp -l 1.img 2.img Signed-off-by: Qing Zhang --- v2: - keep Kconfig and Makefile sorted - make the entire comment a C++ one so things look more intentional - Fix unclear indentation - make conditional statements to improve legibility - Don't use static inline - the core handle message queue - Add a new binding document - Fix probe part mixed pdev and PCI v3: - expose set_cs to the core and let it handle things - replace transfer_one_message to transfer_one - replace spi_alloc_master to devm_spi_alloc_master - split out into prepare/unprepare_message - releases pci regions before unregister master v4: - names used in the manual - rename ls7a_spi_do_transfer to ls7a_spi_setup_transfer - change read the spcr and sper outside of this function - mode configuration moved to prepare instead - remove redundancy code about unprepare/prepare_message - used 0x4 instead of 0x1,WFEMPTY instead of RFEMPTY v5: - remove unnecessary blank lines v6: - keep blank line before the last "return xxx" --- drivers/spi/Kconfig | 7 ++ drivers/spi/Makefile | 1 + drivers/spi/spi-ls7a.c | 282 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 290 insertions(+) create mode 100644 drivers/spi/spi-ls7a.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index aadaea0..af7c0d4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -413,6 +413,13 @@ config SPI_LP8841_RTC Say N here unless you plan to run the kernel on an ICP DAS LP-8x4x industrial computer. +config SPI_LS7A + tristate "Loongson LS7A SPI Controller Support" + depends on CPU_LOONGSON64 || COMPILE_TEST + help + This drivers supports the Loongson LS7A SPI controller in master + SPI mode. + config SPI_MPC52xx tristate "Freescale MPC52xx SPI (non-PSC) controller support" depends on PPC_MPC52xx diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 6fea582..d015cf2 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o obj-$(CONFIG_SPI_JCORE) += spi-jcore.o obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o +obj-$(CONFIG_SPI_LS7A) += spi-ls7a.o obj-$(CONFIG_SPI_MESON_SPICC) += spi-meson-spicc.o obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o diff --git a/drivers/spi/spi-ls7a.c b/drivers/spi/spi-ls7a.c new file mode 100644 index 0000000..8592b85 --- /dev/null +++ b/drivers/spi/spi-ls7a.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Loongson LS7A SPI Controller driver +// +// Copyright (C) 2020 Loongson Technology Corporation Limited. +// + +#include +#include +#include + +/* define spi register */ +#define SPCR 0x00 +#define SPSR 0x01 +#define FIFO 0x02 +#define SPER 0x03 +#define SFC_PARAM 0x04 +#define SFC_SOFTCS 0x05 +#define SFC_TIMING 0x06 + +struct ls7a_spi { + struct spi_master *master; + void __iomem *base; + unsigned int hz; + unsigned int mode; +}; + +static void ls7a_spi_write_reg(struct ls7a_spi *spi, + unsigned char reg, + unsigned char data) +{ + writeb(data, spi->base + reg); +} + +static char ls7a_spi_read_reg(struct ls7a_spi *spi, unsigned char reg) +{ + return readb(spi->base + reg); +} + +static int ls7a_spi_prepare_message(struct spi_master *master, + struct spi_message *msg) +{ + struct ls7a_spi *ls7a_spi; + struct spi_device *spi = msg->spi; + unsigned char val; + + ls7a_spi = spi_master_get_devdata(master); + + if (ls7a_spi->mode != spi->mode) { + val = ls7a_spi_read_reg(ls7a_spi, SPCR); + val &= ~0xc; + if (spi->mode & SPI_CPOL) + val |= 8; + if (spi->mode & SPI_CPHA) + val |= 4; + ls7a_spi_write_reg(ls7a_spi, SPCR, val); + val = ls7a_spi_read_reg(ls7a_spi, SPER); + ls7a_spi_write_reg(ls7a_spi, SPER, val); + ls7a_spi->mode = spi->mode; + } + + return 0; +} + +static void ls7a_spi_set_cs(struct spi_device *spi, bool enable) +{ + struct ls7a_spi *ls7a_spi; + int cs; + + ls7a_spi = spi_master_get_devdata(spi->master); + + cs = ls7a_spi_read_reg(ls7a_spi, SFC_SOFTCS) & ~(0x11 << spi->chip_select); + + if (!!(spi->mode & SPI_CS_HIGH) == enable) + ls7a_spi_write_reg(ls7a_spi, SFC_SOFTCS, (0x1 << spi->chip_select) | cs); + else + ls7a_spi_write_reg(ls7a_spi, SFC_SOFTCS, (0x11 << spi->chip_select) | cs); +} + +static int ls7a_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + unsigned int hz; + unsigned int div, div_tmp; + unsigned int bit; + unsigned long clk; + unsigned char val; + unsigned char spcr, sper; + const char rdiv[12] = {0, 1, 4, 2, 3, 5, 6, 7, 8, 9, 10, 11}; + struct ls7a_spi *ls7a_spi; + + ls7a_spi = spi_master_get_devdata(spi->master); + + if (t) { + hz = t->speed_hz; + if (!hz) + hz = spi->max_speed_hz; + } else { + hz = spi->max_speed_hz; + } + + if (hz & (ls7a_spi->hz != hz)) { + clk = 100000000; + + div = DIV_ROUND_UP(clk, hz); + if (div < 2) + div = 2; + if (div > 4096) + div = 4096; + + bit = fls(div) - 1; + if ((1 << bit) == div) + bit--; + div_tmp = rdiv[bit]; + + dev_dbg(&spi->dev, "clk = %ld hz = %d div_tmp = %d bit = %d\n", + clk, hz, div_tmp, bit); + + ls7a_spi->hz = hz; + spcr = div_tmp & 3; + sper = (div_tmp >> 2) & 3; + + val = ls7a_spi_read_reg(ls7a_spi, SPCR); + ls7a_spi_write_reg(ls7a_spi, SPCR, (val & ~3) | spcr); + val = ls7a_spi_read_reg(ls7a_spi, SPER); + ls7a_spi_write_reg(ls7a_spi, SPER, (val & ~3) | sper); + } + + return 0; +} + +static int ls7a_spi_setup(struct spi_device *spi) +{ + return ls7a_spi_setup_transfer(spi, NULL); +} + +static int ls7a_spi_write_read_8bit(struct spi_device *spi, + const u8 **tx_buf, u8 **rx_buf, + unsigned int num) +{ + struct ls7a_spi *ls7a_spi; + + ls7a_spi = spi_master_get_devdata(spi->master); + + if (tx_buf && *tx_buf) { + ls7a_spi_write_reg(ls7a_spi, FIFO, *((*tx_buf)++)); + + while ((ls7a_spi_read_reg(ls7a_spi, SPSR) & 0x4) == 1) + ; + } else { + ls7a_spi_write_reg(ls7a_spi, FIFO, 0); + + while ((ls7a_spi_read_reg(ls7a_spi, SPSR) & 0x1) == 1) + ; + } + + if (rx_buf && *rx_buf) + *(*rx_buf)++ = ls7a_spi_read_reg(ls7a_spi, FIFO); + else + ls7a_spi_read_reg(ls7a_spi, FIFO); + + return 1; +} + +static unsigned int ls7a_spi_write_read(struct spi_device *spi, + struct spi_transfer *xfer) +{ + unsigned int count; + const u8 *tx = xfer->tx_buf; + u8 *rx = xfer->rx_buf; + + count = xfer->len; + + do { + if (ls7a_spi_write_read_8bit(spi, &tx, &rx, count) < 0) + goto out; + count--; + } while (count); + +out: + return xfer->len - count; +} + +static int ls7a_spi_transfer_one(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *t) +{ + int status = 0; + + status = ls7a_spi_setup_transfer(spi, t); + if (status < 0) + return status; + + if (t->len) + ls7a_spi_write_read(spi, t); + + return status; +} + +static int ls7a_spi_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct spi_master *master; + struct ls7a_spi *spi; + int ret; + + master = devm_spi_alloc_master(&pdev->dev, sizeof(*spi)); + if (!master) + return -ENOMEM; + + spi = spi_master_get_devdata(master); + ret = pcim_enable_device(pdev); + if (ret) + goto err_free_master; + + ret = pci_request_regions(pdev, "ls7a-spi"); + if (ret) + goto err_free_master; + + spi->base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); + if (!spi->base) { + ret = -EINVAL; + goto err_free_master; + } + ls7a_spi_write_reg(spi, SPCR, 0x51); + ls7a_spi_write_reg(spi, SPER, 0x00); + ls7a_spi_write_reg(spi, SFC_TIMING, 0x01); + ls7a_spi_write_reg(spi, SFC_PARAM, 0x40); + spi->mode = 0; + + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + master->set_cs = ls7a_spi_set_cs; + master->prepare_message = ls7a_spi_prepare_message; + master->setup = ls7a_spi_setup; + master->transfer_one = ls7a_spi_transfer_one; + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->num_chipselect = 4; + master->dev.of_node = pdev->dev.of_node; + + spi->master = master; + + pci_set_drvdata(pdev, master); + + ret = spi_register_master(master); + if (ret) + goto err_free_master; + + return 0; + +err_free_master: + pci_release_regions(pdev); + return ret; +} + +static void ls7a_spi_pci_remove(struct pci_dev *pdev) +{ + struct spi_master *master = pci_get_drvdata(pdev); + + spi_unregister_master(master); + pci_release_regions(pdev); +} + +static const struct pci_device_id ls7a_spi_pci_id_table[] = { + { PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x7a0b) }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, ls7a_spi_pci_id_table); + +static struct pci_driver ls7a_spi_pci_driver = { + .name = "ls7a-spi", + .id_table = ls7a_spi_pci_id_table, + .probe = ls7a_spi_pci_probe, + .remove = ls7a_spi_pci_remove, +}; + +module_pci_driver(ls7a_spi_pci_driver); + +MODULE_AUTHOR("Juxin Gao "); +MODULE_AUTHOR("Qing Zhang "); +MODULE_DESCRIPTION("Loongson LS7A SPI controller driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Dec 28 02:59:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qing Zhang X-Patchwork-Id: 11990815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1398EC43331 for ; Mon, 28 Dec 2020 03:00:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D229D2076B for ; Mon, 28 Dec 2020 03:00:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726371AbgL1DAd (ORCPT ); Sun, 27 Dec 2020 22:00:33 -0500 Received: from mail.loongson.cn ([114.242.206.163]:38128 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726333AbgL1DAd (ORCPT ); Sun, 27 Dec 2020 22:00:33 -0500 Received: from linux.localdomain (unknown [113.200.148.30]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxHzYdSulfznIGAA--.9S3; Mon, 28 Dec 2020 10:59:43 +0800 (CST) From: Qing Zhang To: Mark Brown , Rob Herring , ThomasBogendoerfer Cc: linux-spi@vger.kernel.org, Huacai Chen , Jiaxun Yang , yangtiezhu@loongson.cn, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/4] spi: ls7a: Add YAML schemas Date: Mon, 28 Dec 2020 10:59:39 +0800 Message-Id: <1609124381-9107-2-git-send-email-zhangqing@loongson.cn> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> References: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> X-CM-TRANSID: AQAAf9DxHzYdSulfznIGAA--.9S3 X-Coremail-Antispam: 1UD129KBjvJXoW7CF4rWw13tFy3Xr47tr1kZrb_yoW8WrW3pF 47C3sxta1IgF1xC393ta48C3W5Xr95C3W3tFZrtw17Kas8Ka90vw43Kwn8Z3W7JF48AFyx XFZ2gr4rKF10yw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPK14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxd M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkIecxEwVAFwVW8JwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8 JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1V AFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xII jxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4 A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU 0xZFpf9x0JU3hL5UUUUU= X-CM-SenderInfo: x2kd0wptlqwqxorr0wxvrqhubq/ Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Switch the DT binding to a YAML schema to enable the DT validation. Reviewed-by: Huacai Chen Signed-off-by: Qing Zhang --- v4: - fix warnings/errors about running 'make dt_binding_check' v5: - remove num-chipelects v6: - No changes --- .../devicetree/bindings/spi/loongson,spi-ls7a.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml diff --git a/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml b/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml new file mode 100644 index 0000000..b90b28b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/loongson,spi-ls7a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A PCH SPI Controller + +maintainers: + - Qing Zhang + +description: | + This controller can be found in Loongson-3 systems with LS7A PCH. + +properties: + compatible: + const: loongson,ls7a-spi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pci { + #address-cells = <3>; + #size-cells = <2>; + + spi@16,0 { + compatible = "pci0014,7a0b.0", + "pci0014,7a0b", + "pciclass088000", + "pciclass0800"; + + reg = <0xb000 0x0 0x0 0x0 0x0>; + }; + }; + +... From patchwork Mon Dec 28 02:59:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qing Zhang X-Patchwork-Id: 11990819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68365C43332 for ; Mon, 28 Dec 2020 03:00:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F29E20715 for ; Mon, 28 Dec 2020 03:00:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726518AbgL1DAk (ORCPT ); Sun, 27 Dec 2020 22:00:40 -0500 Received: from mail.loongson.cn ([114.242.206.163]:38132 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726289AbgL1DAd (ORCPT ); Sun, 27 Dec 2020 22:00:33 -0500 Received: from linux.localdomain (unknown [113.200.148.30]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxHzYdSulfznIGAA--.9S4; Mon, 28 Dec 2020 10:59:44 +0800 (CST) From: Qing Zhang To: Mark Brown , Rob Herring , ThomasBogendoerfer Cc: linux-spi@vger.kernel.org, Huacai Chen , Jiaxun Yang , yangtiezhu@loongson.cn, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/4] MIPS: Loongson64: DTS: Add SPI support to LS7A Date: Mon, 28 Dec 2020 10:59:40 +0800 Message-Id: <1609124381-9107-3-git-send-email-zhangqing@loongson.cn> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> References: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> X-CM-TRANSID: AQAAf9DxHzYdSulfznIGAA--.9S4 X-Coremail-Antispam: 1UD129KBjvdXoWrtFW3WF17Jw15urW3JFW7XFb_yoWfArc_G3 Wxtw4fGrWrJFy7Z3ykZr4DCFW7urW8u3s5CFn7Xrn8WasYyrnxJFW8C3yDZw1UurWYvrsY yrZYqF4UCr17KjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbykFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUXwA2048vs2IY02 0Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc2xSY4AK67AK6r4UMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4U MI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67 AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0 cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z2 80aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI 43ZEXa7VUUk9NDUUUUU== X-CM-SenderInfo: x2kd0wptlqwqxorr0wxvrqhubq/ Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add spi support. Reviewed-by: Huacai Chen Signed-off-by: Qing Zhang --- v2: - Add spi about pci device DT v3: - Remove spiflash node v4: - Remove useless compatible v5: - Remove num-chipselects v6: - No changes --- arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi index f99a7a1..dba717d 100644 --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -405,6 +405,15 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>; }; + + spi@16,0 { + compatible = "pci0014,7a0b.0", + "pci0014,7a0b", + "pciclass088000", + "pciclass0880"; + + reg = <0xb000 0x0 0x0 0x0 0x0>; + }; }; isa { From patchwork Mon Dec 28 02:59:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qing Zhang X-Patchwork-Id: 11990821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E104C43219 for ; Mon, 28 Dec 2020 03:00:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 683DE22B2A for ; Mon, 28 Dec 2020 03:00:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726507AbgL1DAk (ORCPT ); Sun, 27 Dec 2020 22:00:40 -0500 Received: from mail.loongson.cn ([114.242.206.163]:38126 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726316AbgL1DAd (ORCPT ); Sun, 27 Dec 2020 22:00:33 -0500 Received: from linux.localdomain (unknown [113.200.148.30]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxHzYdSulfznIGAA--.9S5; Mon, 28 Dec 2020 10:59:45 +0800 (CST) From: Qing Zhang To: Mark Brown , Rob Herring , ThomasBogendoerfer Cc: linux-spi@vger.kernel.org, Huacai Chen , Jiaxun Yang , yangtiezhu@loongson.cn, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/4] MIPS: Loongson: Enable Loongson LS7A SPI in loongson3_defconfig Date: Mon, 28 Dec 2020 10:59:41 +0800 Message-Id: <1609124381-9107-4-git-send-email-zhangqing@loongson.cn> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> References: <1609124381-9107-1-git-send-email-zhangqing@loongson.cn> X-CM-TRANSID: AQAAf9DxHzYdSulfznIGAA--.9S5 X-Coremail-Antispam: 1UD129KBjvdXoWrKw4UJFW3tw4DJry3tF48tFb_yoWfGwc_Ga y7Kw18Wr48JrW8u3yxXw4rW3yDC3WUuFn5CF17try3Xa4a9rnxtFyqyrWxGw15WasI9rW3 ZaykJa429F1IqjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbykFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUWwA2048vs2IY02 0Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc2xSY4AK67AK6r4UMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4U MI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67 AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0 cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z2 80aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI 43ZEXa7VUbOtxDUUUUU== X-CM-SenderInfo: x2kd0wptlqwqxorr0wxvrqhubq/ Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This is now supported, enable for Loongson systems. Reviewed-by: Huacai Chen Signed-off-by: Qing Zhang --- v2: - Modify CONFIG_SPI_LOONGSON to CONFIG_SPI_LS7A v3: - No changes v4: - No changes v5: - No changes v6: - No changes --- arch/mips/configs/loongson3_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 38a817e..28784cb 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -271,6 +271,9 @@ CONFIG_HW_RANDOM=y CONFIG_RAW_DRIVER=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_PIIX4=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_LS7A=y CONFIG_GPIO_LOONGSON=y CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM93=m