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Tue, 29 Dec 2020 13:17:31 -0800 (PST) From: Cristian Ciocaltea To: Manivannan Sadhasivam , Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH v3 01/13] arm: dts: owl-s500: Add Clock Management Unit Date: Tue, 29 Dec 2020 23:17:16 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161733_989050_FFB0D7C9 X-CRM114-Status: GOOD ( 12.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Clock Management Unit for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 1dbe4e8b38ac..5d5ad9db549b 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2016-2017 Andreas Färber */ +#include #include #include @@ -70,6 +71,12 @@ hosc: hosc { #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -169,6 +176,13 @@ uart6: serial@b012c000 { status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Tue Dec 29 21:17:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E646DC433E0 for ; Tue, 29 Dec 2020 21:19:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AAB3321D1B for ; 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Tue, 29 Dec 2020 13:17:33 -0800 (PST) From: Cristian Ciocaltea To: Manivannan Sadhasivam , Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH v3 02/13] arm: dts: owl-s500: Set CMU clocks for UARTs Date: Tue, 29 Dec 2020 23:17:17 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161736_089990_761E356B X-CRM114-Status: GOOD ( 12.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set Clock Management Unit clocks for the UART nodes of Actions Semi S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by from Mani - Removed the dummy 'uart2_clk' and 'uart3_clk' nodes from all owl-s500 DTS, per Mani's review arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 ------- arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 ------- arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 7 ------- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 ------- arch/arm/boot/dts/owl-s500-sparky.dts | 7 ------- arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++ 6 files changed, 7 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts index 7c96c59b610d..c2b02895910c 100644 --- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &timer { &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts index e610d49395d2..7ae34a23e320 100644 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -18,15 +18,8 @@ aliases { chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts index c92f8bdcb331..1585e33f703b 100644 --- a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts +++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts @@ -21,15 +21,8 @@ aliases { chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index a2087e617cb2..800edf5d2d12 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; - - uart2_clk: uart2-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &twd_timer { @@ -43,5 +37,4 @@ &timer { &uart2 { status = "okay"; - clocks = <&uart2_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts index c665ce8b88b4..9d8f7336bec0 100644 --- a/arch/arm/boot/dts/owl-s500-sparky.dts +++ b/arch/arm/boot/dts/owl-s500-sparky.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; /* 1 or 2 GiB */ }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &timer { &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5d5ad9db549b..ac3d04c75dd5 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -131,6 +131,7 @@ uart0: serial@b0120000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -138,6 +139,7 @@ uart1: serial@b0122000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -145,6 +147,7 @@ uart2: serial@b0124000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -152,6 +155,7 @@ uart3: serial@b0126000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -159,6 +163,7 @@ uart4: serial@b0128000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -166,6 +171,7 @@ uart5: serial@b012a000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -173,6 +179,7 @@ uart6: serial@b012c000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; From patchwork Tue Dec 29 21:17:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97C05C433DB for ; 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Tue, 29 Dec 2020 13:17:36 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:35 -0800 (PST) From: Cristian Ciocaltea To: Manivannan Sadhasivam , Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH v3 03/13] arm: dts: owl-s500: Add Reset controller Date: Tue, 29 Dec 2020 23:17:18 +0200 Message-Id: <4da1db3425321525bc97022370d8a6a149bca091.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161737_511119_7C32C0DE X-CRM114-Status: GOOD ( 13.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add reset controller property and bindings header for the Actions Semi S500 SoC DTS. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index ac3d04c75dd5..a57ce7d6d745 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "actions,s500"; @@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 { reg = <0xb0160000 0x8000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; timer: timer@b0168000 { From patchwork Tue Dec 29 21:17:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71860C4332B for ; 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Tue, 29 Dec 2020 13:17:37 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:37 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , Vinod Koul , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH v3 04/13] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC Date: Tue, 29 Dec 2020 23:17:19 +0200 Message-Id: <2bd23ef5dad5dd613006c20d714b1be3c4d38e7a.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161739_169230_EE3A8037 X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new compatible string corresponding to the DMA controller found in the S500 variant of the Actions Semi Owl SoCs family. Additionally, order the entries alphabetically. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- Changes in v3: - Added Reviewed-by tags from Mani and Rob - Ordered the entries per Mani's suggestion Documentation/devicetree/bindings/dma/owl-dma.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml index 256d62af2c64..93b4847554fb 100644 --- a/Documentation/devicetree/bindings/dma/owl-dma.yaml +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml @@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller description: | The OWL DMA is a general-purpose direct memory access controller capable of - supporting 10 and 12 independent DMA channels for S700 and S900 SoCs - respectively. + supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12 + independent DMA channels for the S500 and S900 SoC variants. maintainers: - Manivannan Sadhasivam @@ -20,8 +20,9 @@ allOf: properties: compatible: enum: - - actions,s900-dma + - actions,s500-dma - actions,s700-dma + - actions,s900-dma reg: maxItems: 1 From patchwork Tue Dec 29 21:17:20 2020 Content-Type: text/plain; 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Tue, 29 Dec 2020 13:17:38 -0800 (PST) From: Cristian Ciocaltea To: Vinod Koul , Dan Williams , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Rob Herring Subject: [PATCH v3 05/13] dmaengine: owl: Add compatible for the Actions Semi S500 DMA controller Date: Tue, 29 Dec 2020 23:17:20 +0200 Message-Id: <88dc9dc064fd4c71f7ad46f172b05b09b9777e42.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161740_647947_DF28BCE7 X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dmaengine@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The DMA controller present on the Actions Semi S500 SoC is compatible with the S900 variant, so add it to the list of devices supported by the Actions Semi Owl DMA driver. Additionally, order the entries alphabetically. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani - Ordered the entries to be consistent with the related dt-bindings drivers/dma/owl-dma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c index 9fede32641e9..25cbd363e513 100644 --- a/drivers/dma/owl-dma.c +++ b/drivers/dma/owl-dma.c @@ -1080,8 +1080,9 @@ static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec, } static const struct of_device_id owl_dma_match[] = { - { .compatible = "actions,s900-dma", .data = (void *)S900_DMA,}, + { .compatible = "actions,s500-dma", .data = (void *)S900_DMA,}, { .compatible = "actions,s700-dma", .data = (void *)S700_DMA,}, + { .compatible = "actions,s900-dma", .data = (void *)S900_DMA,}, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, owl_dma_match); From patchwork Tue Dec 29 21:17:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA129C433DB for ; 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Tue, 29 Dec 2020 13:17:40 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:40 -0800 (PST) From: Cristian Ciocaltea To: =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Rob Herring , Vinod Koul , Dan Williams Subject: [PATCH v3 06/13] arm: dts: owl-s500: Add DMA controller Date: Tue, 29 Dec 2020 23:17:21 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161742_676918_025330DD X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DMA controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index a57ce7d6d745..449e9807c4ec 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -207,5 +207,19 @@ sps: power-controller@b01b0100 { reg = <0xb01b0100 0x100>; #power-domain-cells = <1>; }; + + dma: dma-controller@b0260000 { + compatible = "actions,s500-dma"; + reg = <0xb0260000 0xd00>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&cmu CLK_DMAC>; + power-domains = <&sps S500_PD_DMA>; + }; }; }; From patchwork Tue Dec 29 21:17:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 625A2C433E0 for ; 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Tue, 29 Dec 2020 13:17:42 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:41 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH v3 07/13] arm: dts: owl-s500: Add pinctrl & GPIO support Date: Tue, 29 Dec 2020 23:17:22 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161743_163947_89D76A9D X-CRM114-Status: GOOD ( 13.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add pinctrl node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 449e9807c4ec..b16172615db0 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -208,6 +209,25 @@ sps: power-controller@b01b0100 { #power-domain-cells = <1>; }; + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, /* GPIO */ + <0xb01b0040 0x10>, /* Multiplexing Control */ + <0xb01b0060 0x18>, /* PAD Control */ + <0xb01b0080 0xc>; /* PAD Drive Capacity */ + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* GPIOA */ + , /* GPIOB */ + , /* GPIOC */ + , /* GPIOD */ + ; /* GPIOE */ + }; + dma: dma-controller@b0260000 { compatible = "actions,s500-dma"; reg = <0xb0260000 0xd00>; From patchwork Tue Dec 29 21:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E135BC433E0 for ; Tue, 29 Dec 2020 21:21:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 90A1A20727 for ; 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Tue, 29 Dec 2020 13:17:42 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Ulf Hansson Subject: [PATCH v3 08/13] arm: dts: owl-s500: Add MMC support Date: Tue, 29 Dec 2020 23:17:23 +0200 Message-Id: <94e75de6c982c842feffcf63c285b55b8c5fea02.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161744_607021_69FE74F8 X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add MMC controller nodes for Actions Semi S500 SoC, in order to facilitate access to SD/EMMC/SDIO cards. Signed-off-by: Cristian Ciocaltea Reviewed-by: Ulf Hansson Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by tags from Ulf and Mani arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index b16172615db0..7af7c9e1119d 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -241,5 +241,38 @@ dma: dma-controller@b0260000 { clocks = <&cmu CLK_DMAC>; power-domains = <&sps S500_PD_DMA>; }; + + mmc0: mmc@b0230000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0230000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD0>; + resets = <&cmu RESET_SD0>; + dmas = <&dma 2>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc1: mmc@b0234000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0234000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD1>; + resets = <&cmu RESET_SD1>; + dmas = <&dma 3>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc2: mmc@b0238000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0238000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD2>; + resets = <&cmu RESET_SD2>; + dmas = <&dma 4>; + dma-names = "mmc"; + status = "disabled"; + }; }; }; From patchwork Tue Dec 29 21:17:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A599C433DB for ; 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Tue, 29 Dec 2020 13:17:44 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:44 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH v3 09/13] arm: dts: owl-s500: Add I2C support Date: Tue, 29 Dec 2020 23:17:24 +0200 Message-Id: <2813c65915eda155da637bdc649872a75ce240bc.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161746_278659_8B0DE1F2 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, Wolfram Sang , linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add I2C controller nodes for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 7af7c9e1119d..55f8b8c2e149 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -193,6 +193,46 @@ cmu: clock-controller@b0160000 { #reset-cells = <1>; }; + i2c0: i2c@b0170000 { + compatible = "actions,s500-i2c"; + reg = <0xb0170000 0x4000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b0174000 { + compatible = "actions,s500-i2c"; + reg = <0xb0174000 0x4000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b0178000 { + compatible = "actions,s500-i2c"; + reg = <0xb0178000 0x4000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b017c000 { + compatible = "actions,s500-i2c"; + reg = <0xb017c000 0x4000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Tue Dec 29 21:17:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C33CC433E0 for ; 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Tue, 29 Dec 2020 13:17:46 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:45 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH v3 10/13] arm: dts: owl-s500: Add SIRQ controller Date: Tue, 29 Dec 2020 23:17:25 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161747_166740_46250DF0 X-CRM114-Status: GOOD ( 12.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add SIRQ controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Tested-by: Matheus Castello --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 55f8b8c2e149..cd635f222d26 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -233,6 +233,16 @@ i2c3: i2c@b017c000 { status = "disabled"; }; + sirq: interrupt-controller@b01b0200 { + compatible = "actions,s500-sirq"; + reg = <0xb01b0200 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* SIRQ0 */ + , /* SIRQ1 */ + ; /* SIRQ2 */ + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Tue Dec 29 21:17:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A37BC433DB for ; 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Tue, 29 Dec 2020 13:17:47 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:46 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH v3 11/13] arm: dts: owl-s500-roseapplepi: Add uSD support Date: Tue, 29 Dec 2020 23:17:26 +0200 Message-Id: <47ee9695e89198ec2fbc4ab6188f1d0ad0424b2f.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161748_863259_2B552EDA X-CRM114-Status: GOOD ( 13.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add uSD support for RoseapplePi SBC using a fixed regulator as a temporary solution until PMIC support becomes available. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - None arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index 800edf5d2d12..fe9ae3619422 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -14,6 +14,7 @@ / { model = "Roseapple Pi"; aliases { + mmc0 = &mmc0; serial2 = &uart2; }; @@ -25,6 +26,55 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; + + /* Fixed regulator used in the absence of PMIC */ + sd_vcc: sd-vcc { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.1V"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; +}; + +&pinctrl { + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias0-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + + bias1-pinconf { + pins = "sd0_clk"; + bias-pull-down; + }; + }; +}; + +/* uSD */ +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + no-sdio; + no-mmc; + no-1-8-v; + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <&sd_vcc>; + vqmmc-supply = <&sd_vcc>; }; &twd_timer { From patchwork Tue Dec 29 21:17:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11992643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A469AC433E0 for ; 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Tue, 29 Dec 2020 13:17:48 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:48 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH v3 12/13] arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration Date: Tue, 29 Dec 2020 23:17:27 +0200 Message-Id: <99b1f6772064a6fafdc0fd857bc22ff9976241eb.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_161750_215278_6DFB2A7D X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC. For the moment enable only I2C0, which is used by the ATC2603C PMIC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index fe9ae3619422..ff91561ca99c 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -37,7 +37,51 @@ sd_vcc: sd-vcc { }; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + &pinctrl { + i2c0_pins: i2c0-pins { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2-pins { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; + mmc0_pins: mmc0-pins { pinmux { groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",