From patchwork Thu Dec 31 06:28:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenming Lu X-Patchwork-Id: 11993859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04E95C433DB for ; Thu, 31 Dec 2020 06:30:43 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AD8E5207A3 for ; Thu, 31 Dec 2020 06:30:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AD8E5207A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=3OXX/8EXMWgZgSUATGLDpgtO48bDGaVhu6nbNEpi6BI=; b=PwNkJH3pjOpQNW2/SWQSUoUjW8 XCSr4mcSDiW8plbAItlOBHEptD0yGpwon0rnLBkRkfHed4YiRgy5E/e2zOmBvjcyov/EIlJwNjDPc vm7LgkK+jmk9FfzLvAcccBTqTlKJy1b0UNCuYBAHAmXBMck/ioNQMA3f7vWcgTz1QhxLlDnpEDx/l T+iif0OgCqKXJpzYgDARvWSei3EBUSU9mlGQPWmuhFEhokP6Gx4s64F4GbjvEacmn1YRyuXKExW1M Ao7f+et6pfqfAr7jCypilfjRtZJj3GTox4MCTwdaahNKl0JUWN0pWjUynv+tkPYtf/YsBFWJLxU/p tySyhLRg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kurSR-0002vb-4j; Thu, 31 Dec 2020 06:29:11 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kurSL-0002v0-Oz for linux-arm-kernel@lists.infradead.org; Thu, 31 Dec 2020 06:29:07 +0000 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4D5yrK4GHWzkyWn; Thu, 31 Dec 2020 14:27:45 +0800 (CST) Received: from DESKTOP-7FEPK9S.china.huawei.com (10.174.184.196) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.498.0; Thu, 31 Dec 2020 14:28:38 +0800 From: Shenming Lu To: Marc Zyngier , Will Deacon , Eric Auger , , , Subject: [PATCH RFC] KVM: arm64: vgic: Decouple the check of the EnableLPIs bit from the ITS LPI translation Date: Thu, 31 Dec 2020 14:28:13 +0800 Message-ID: <20201231062813.714-1-lushenming@huawei.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.184.196] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201231_012906_909131_0B36DD82 X-CRM114-Status: GOOD ( 12.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yuzenghui@huawei.com, wanghaibin.wang@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the EnableLPIs bit is set to 0, any ITS LPI requests in the Redistributor would be ignored. And this check is independent from the ITS LPI translation. So it might be better to move the check of the EnableLPIs bit out of the LPI resolving, and also add it to the path that uses the translation cache. Besides it seems that by this the invalidating of the translation cache caused by the LPI disabling is unnecessary. Not sure if I have missed something... Thanks. Signed-off-by: Shenming Lu --- arch/arm64/kvm/vgic/vgic-its.c | 9 +++++---- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 +--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c index 40cbaca81333..f53446bc154e 100644 --- a/arch/arm64/kvm/vgic/vgic-its.c +++ b/arch/arm64/kvm/vgic/vgic-its.c @@ -683,9 +683,6 @@ int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its, if (!vcpu) return E_ITS_INT_UNMAPPED_INTERRUPT; - if (!vcpu->arch.vgic_cpu.lpis_enabled) - return -EBUSY; - vgic_its_cache_translation(kvm, its, devid, eventid, ite->irq); *irq = ite->irq; @@ -738,6 +735,9 @@ static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its, if (err) return err; + if (!irq->target_vcpu->arch.vgic_cpu.lpis_enabled) + return -EBUSY; + if (irq->hw) return irq_set_irqchip_state(irq->host_irq, IRQCHIP_STATE_PENDING, true); @@ -757,7 +757,8 @@ int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi) db = (u64)msi->address_hi << 32 | msi->address_lo; irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data); - if (!irq) + + if (!irq || !irq->target_vcpu->arch.vgic_cpu.lpis_enabled) return -EWOULDBLOCK; raw_spin_lock_irqsave(&irq->irq_lock, flags); diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index 15a6c98ee92f..7b0749f7660d 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -242,10 +242,8 @@ static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS; - if (was_enabled && !vgic_cpu->lpis_enabled) { + if (was_enabled && !vgic_cpu->lpis_enabled) vgic_flush_pending_lpis(vcpu); - vgic_its_invalidate_cache(vcpu->kvm); - } if (!was_enabled && vgic_cpu->lpis_enabled) vgic_enable_lpis(vcpu);