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Thu, 7 Jan 2021 15:30:10 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Anvesh Salveru , Shradha Todi , Kishon Vijay Abraham I , Vinod Koul Subject: [PATCH v7 1/5] phy: core: add phy_property_present method Date: Thu, 7 Jan 2021 20:58:39 +0530 Message-Id: <1610033323-10560-2-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG+845247S6jSN3matWuat0rLbEbpK2iwrYYSggo06WEy3tXkp RbOb5rxCTtDETKV0paJZ07QyLZWsMNdlptYIo+yCpXOTzC7zJP33e573+Z4XXj4SF/wihORR RSyjVsiixVxH4la7p/vqGF9b5BrtWxd64loeTn8vqMLonvdZXHrggwnRxtvFXPpJSSeXzrAU cemh/Hcc+mGdlC67aeHR2e3JtKmWRzcNdOHb+ZKmokGepF6fwZXkNOiRpNNkwCRj9aIQTpjj 5sNM9NF4Ru2z9aDjkbqcEUJ1yfn4VJ8RT0VmSoscSKDWgzbrC0+LHEkB1Ywg+7QVsWIUwfkf +QQrrAiqM59xZ570VQ79S91BUDlWjbHiLAaTny3InuJSXnBqXIvb2ZkKg0LDOY49hFN1GHQM 9RL2gRPlD+kGG8fOBLUCOobP/GWS5FMBYEpXs9tE0Pc0Y7rHgQoEa0ENh/W/8qChScryTjC0 ZuIsO8GnzgYey0IYzk37x0rQ9bwn7PVAHYerWSmsvQ1anxdP2zjlCbW3fVh7Mege1WB2xqk5 kD05hLE+HxpLZng5WKZaCJYXQkmHkcO2S2DSupK9SCGC8mYdlodERf83lCKkRwsZlSYmitFs UK1VMAneGlmMJk4R5X1IGVOPpr+IV1AjGjR/825DGInaEJC42JlPd1giBfzDshOJjFoZqY6L ZjRtyIUkxAv4jWvMkQIqShbLyBlGxahnphjpIEzFyht0L5fN3pQuLbt+R+ZWE++3N2U0oTtk t0P5Ba/MpUHbcubFeyRUKG2/sCSiJTFvZJ28h4MH9cu/Dy5qLt4iWtI+Eeo07Po7XOh25l1G ph+ySWuKfPZLZ3nICxTiN2PiuxWd47ETVKItKzf5cSnT3SsLGHfedyo4SY+3eq4qbZlvsEbc 4+3aM35fY7oYtkAkffBDHre7qjl3oto1VhVkRStDK68Eq8KrQvTutf5pFXlTL0KPDacMmpls 11dJHiURP1/7B3d/PBvRf/lAvW7OKJlsrKanjO1LAoXhlK8uII28gd34EG809859q3yREOgN Gwa6dpRtPHQ+3OWkYH+pmNAcka31wtUa2R+J+8oYkQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrALMWRmVeSWpSXmKPExsWy7bCSvC6L5vd4g5WLLCx+rJ7AbPFx2kom iwtPe9gs7jy/wWhxedccNouz846zWXR+mcVm8WTKI1aLoxuDLRZt/cJu0Xu41uLGenaLnXdO MDvweuycdZfdY9OqTjaPvi2rGD2O39jO5PF5k1wAaxSXTUpqTmZZapG+XQJXxsa+9ywF80Uq /t68zNzA+ECgi5GTQ0LAROLmiieMXYxcHEICuxklzm+YywSRkJT4fHEdlC0ssfLfc3aIoiYm ia3b1jOCJNgEtCQav3Yxg9giAjES6//dZAWxmQV2M0lcb1EFsYUFnCTat38Hi7MIqEoce9kM ZHNw8Aq4StxoL4KYLydx81wn2BhOATeJb9PWgZUIAZU8/BQygZFvASPDKkbJ1ILi3PTcYsMC w7zUcr3ixNzi0rx0veT83E2M4EDV0tzBuH3VB71DjEwcjIcYJTiYlUR4LY59iRfiTUmsrEot yo8vKs1JLT7EKM3BoiTOe6HrZLyQQHpiSWp2ampBahFMlomDU6qBaUvxx3MlvxZr8KdsKu5x Cv30Q2DhbJ9HDg9eGr5pK5sell+cceViAsOyX8nTrlR2V01Z94nF/iFD1B/dgst/f0+3tEvl dfrz72AtE4/8/VOno2R/Bs/KTLNbv29eYkvO50XTXs+wEOFo6LHMPnJLiM+sjscgxV58wf6k UHOXa4EMui8+bcpKfMotEbJ8UUHD4mO2p40zP5Xv9Xc/9Ksu66hT41vFui2nbyxy2m52ZN1H yeUr7s2aWf/y3ps9R7kEruhPneKgsfLL0wd+GxY+5C38XnFrr617s7I0S3hNDe+8859il771 CFhlIsR00mdLZbCaRWLhrZy86StXq/s8tog4b+PVapQ72/AG347L25RYijMSDbWYi4oTAb6G PmvDAgAA X-CMS-MailID: 20210107153013epcas5p27700f30e341d7f1fb457035a690490c6 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153013epcas5p27700f30e341d7f1fb457035a690490c6 References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pankaj Dubey In some platforms, we need information of phy properties in the controller drivers. This patch adds a new phy_property_present() method which can be used to check if some property exists in PHY or not. In case of DesignWare PCIe controller, we need to write into controller register to specify about ZRX-DC compliance property of the PHY, which reduces the power consumption during lower power states. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Kishon Vijay Abraham I Cc: Vinod Koul --- drivers/phy/phy-core.c | 20 ++++++++++++++++++++ include/linux/phy/phy.h | 6 ++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 71cb108..e4ecd41 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -420,6 +420,26 @@ int phy_calibrate(struct phy *phy) EXPORT_SYMBOL_GPL(phy_calibrate); /** + * phy_property_present() - checks if the property is present in PHY + * @phy: the phy returned by phy_get() + * @property: name of the property to check + * + * Used to check if the given property is present in PHY. + * Searches for the given property in the phy device tree + * node. + * + * Returns: true if property exists, false otherwise + */ +bool phy_property_present(struct phy *phy, const char *property) +{ + if (!phy) + return false; + + return of_property_read_bool(phy->dev.of_node, property); +} +EXPORT_SYMBOL_GPL(phy_property_present); + +/** * phy_configure() - Changes the phy parameters * @phy: the phy returned by phy_get() * @opts: New configuration to apply diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index e435bdb..cdecb07 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -225,6 +225,7 @@ static inline enum phy_mode phy_get_mode(struct phy *phy) } int phy_reset(struct phy *phy); int phy_calibrate(struct phy *phy); +bool phy_property_present(struct phy *phy, const char *property); static inline int phy_get_bus_width(struct phy *phy) { return phy->attrs.bus_width; @@ -363,6 +364,11 @@ static inline int phy_calibrate(struct phy *phy) return -ENOSYS; } +static inline bool phy_property_present(struct phy *phy, const char *property) +{ + return false; +} + static inline int phy_configure(struct phy *phy, union phy_configure_opts *opts) { From patchwork Thu Jan 7 15:28:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 12004393 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CE73C43332 for ; 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Thu, 7 Jan 2021 15:30:30 +0000 (GMT) X-AuditID: b6c32a4b-eb7ff700000184ac-ed-5ff73274ddb0 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id E4.2A.08745.61927FF5; Fri, 8 Jan 2021 00:30:30 +0900 (KST) Received: from ubuntu.sa.corp.samsungelectronics.net (unknown [107.108.83.125]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20210107153028epsmtip2971fe2872a2a5a799371e17e823cbcd0~X-N98qClA1958119581epsmtip2b; Thu, 7 Jan 2021 15:30:28 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Anvesh Salveru , Shradha Todi , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas Subject: [PATCH v7 2/5] PCI: dwc: add support to handle ZRX-DC Compliant PHYs Date: Thu, 7 Jan 2021 20:58:40 +0530 Message-Id: <1610033323-10560-3-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBKsWRmVeSWpSXmKPExsWy7bCmhm6J0fd4gz2HTSx+rJ7AbLGkKcNi 190OdouP01YyWaz4MpPd4s7zG4wWl3fNYbM4O+84m0Xnl1lsFm9+v2C3eDLlEavF0Y3BFou2 fmG3+L9nB7tF7+Faixvr2R0EPNbMW8PosXPWXXaPBZtKPTat6mTz6NuyitFjy/7PjB6fN8kF sEdx2aSk5mSWpRbp2yVwZSw9285SsFek4sme20wNjIcFuxg5OSQETCSWzFnE2MXIxSEksJtR Yu73pVDOJ0aJxi9fmSCcz4wSZ/5+Z4RpubvpDjNEYhdQ4tEvVginhUlixaJrTCBVbAJaEo1f u5hBbBGBKImZ21vBipgFtjFLTNs+lRUkISzgL7Hl7zUWEJtFQFXiVetLMJtXwFXi1d0b7BDr 5CRunusEG8Qp4Cbxbdo6sEESAlM5JBbvPgJ1k4vEm19/mSFsYYlXx7dANUtJfH63lw3CzpeY euEp0AIOILtCYnlPHUTYXuLAlTlgYWYBTYn1u/QhwrISU0+tA/uFWYBPovf3EyaIOK/Ejnkw trLEl797WCBsSYl5xy6zQtgeEp0/Z0KDbiajxL+miywTGOVmIaxYwMi4ilEytaA4Nz212LTA OC+1XK84Mbe4NC9dLzk/dxMjOPFoee9gfPTgg94hRiYOxkOMEhzMSiK8Fse+xAvxpiRWVqUW 5ccXleakFh9ilOZgURLn3WHwIF5IID2xJDU7NbUgtQgmy8TBKdXA9OxrR7nNi9+LeZuei2w4 /vqgytm/bCkOWU7KXtfXTnpfGR38zmR1d2030/o675m7y/bteZJwZkbyxk7vYyWXKytd3kvb 1JzbHpZ8fW/FjrIvM5z4rL/9/JG72mV2XWBv8XzJJXWuS3n17W6cOdf317Hoo7SC6FGef0e2 MH0XaTFXebz8lZnF/Rlnw/M2ZpcdueBf/pZz9sJZX7fPZl/6TseJ+dS+bIe5xnMsP79tan2l uiw+t3ND+9qm5GoTQ/1Tuu3TmcvCZkxbwqLuLOXTwFV4rjr3Cff/nFUqDgsfM8XKzzA7c2D+ t3mHi6+/vq5326fuq0bzvK6ze33iP+xxS31wyvGl+B+N2NiMxRFtlUosxRmJhlrMRcWJANbm fRWrAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJLMWRmVeSWpSXmKPExsWy7bCSvK6Y5vd4g5YpxhY/Vk9gtljSlGGx 624Hu8XHaSuZLFZ8mclucef5DUaLy7vmsFmcnXeczaLzyyw2ize/X7BbPJnyiNXi6MZgi0Vb v7Bb/N+zg92i93CtxY317A4CHmvmrWH02DnrLrvHgk2lHptWdbJ59G1ZxeixZf9nRo/Pm+QC 2KO4bFJSczLLUov07RK4MpaebWcp2CtS8WTPbaYGxsOCXYycHBICJhJ3N91h7mLk4hAS2MEo cWhmLztEQlLi88V1TBC2sMTKf8/ZIYqamCS2/2phA0mwCWhJNH7tYgaxRQRiJNb/u8kKUsQs cIhZ4vatKWBFwgK+En8nfGUEsVkEVCVetb5kAbF5BVwlXt29AbVNTuLmuU6wQZwCbhLfpq0D GsQBtM1V4uGnkAmMfAsYGVYxSqYWFOem5xYbFhjlpZbrFSfmFpfmpesl5+duYgSHtpbWDsY9 qz7oHWJk4mA8xCjBwawkwmtx7Eu8EG9KYmVValF+fFFpTmrxIUZpDhYlcd4LXSfjhQTSE0tS s1NTC1KLYLJMHJxSDUy+Z9fJMrttTqmf3bzGM/SjY0pd9ZrrHstW2znGMPUcSZQOcNqhoHb3 +zTN5RWBTX5+9UbTerVPXL22/OvLHwtFZp1L3/J3v57z9z1nz6m0z2A2ixTSsnOb0rPbQfrf qsKf23bnVZtfeP0reDqL0V22QrWc3S1pzVu690/fLbBo0bnazMmeK63UCz7p2PHKRB8oeuT/ S5WdebFBGcfBk5/WnErbybJ1m8Ka8soEj66j81V/Pdo7be8S1/SHDOFSO7+ta7hRyFpxssW1 SCv94JYVn3hsXqTHPT3+Xc7w+X+Hwx71Ex0ys6V23H/Zv754R1Jl5IkbTfJ3w/oyLJdYtkv0 1Qkoi/237s/eZSPq4q/EUpyRaKjFXFScCAB1M7GW3AIAAA== X-CMS-MailID: 20210107153030epcas5p14b0967c4d8d9804a2d084981af445c58 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153030epcas5p14b0967c4d8d9804a2d084981af445c58 References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pankaj Dubey Many platforms use DesignWare controller but the PHY can be different in different platforms. If the PHY is compliant is to ZRX-DC specification it helps in low power consumption during power states. If current data rate is 8.0 GT/s or higher and PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states. DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY. Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable to specify this property to the controller. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Rob Herring Cc: Bjorn Helgaas --- drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 645fa18..74590c7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -722,4 +722,10 @@ void dw_pcie_setup(struct dw_pcie *pci) PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + + if (pci->phy_zrxdc_compliant) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0207840..8b905a2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -74,6 +74,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0) + #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) @@ -273,6 +276,7 @@ struct dw_pcie { u8 n_fts[2]; bool iatu_unroll_enabled: 1; bool io_cfg_atu_shared: 1; + bool phy_zrxdc_compliant; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Thu Jan 7 15:28:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 12004395 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 978C1C43219 for ; Thu, 7 Jan 2021 16:11:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FF6E235FF for ; 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Thu, 7 Jan 2021 15:30:49 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Shradha Todi , Anvesh Salveru , Rob Herring , Kishon Vijay Abraham I , Vidya Sagar Subject: [PATCH v7 3/5] dt-bindings: PHY: P2U: Add binding for ZRX-DC PHY property Date: Thu, 7 Jan 2021 20:58:41 +0530 Message-Id: <1610033323-10560-4-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkleLIzCtJLcpLzFFi42LZdlhTXbfK6Hu8QftCNosfqycwW3yctpLJ 4sLTHjaLO89vMFpc3jWHzeLsvONsFp1fZrFZPJnyiNXi6MZgi0Vbv7BbtO49wm7Re7jW4sZ6 dotr23kd+Dx2zrrL7rFpVSebR2/zOzaPvi2rGD2O39jO5PF5k1wAWxSXTUpqTmZZapG+XQJX xoPpm5gLOrgr/mx5y9zAuIOzi5GTQ0LARGL9yk1MXYxcHEICuxklnn09xQKSEBL4xChx4ow1 ROIzo8S05x3MMB3vfr1jg0jsYpSYdLebFcJpYZJ4NOEaI0gVm4CWROPXLrAOEYEoiZnbW8GK mAWuMkl8ObkFLCEsECKxcckbJhCbRUBVomNDCzuIzSvgKjGr6QsrxDo5iZvnOsHqOQXcJL5N Wwc2SEKgkUPi27dvbBBFLhI3e1YwQtjCEq+Ob2GHsKUkXva3Qdn5ElMvPAV6jgPIrpBY3lMH EbaXOHBlDliYWUBTYv0ufYiwrMTUU+vATmMW4JPo/f2ECSLOK7FjHoytLPHl7x4WCFtSYt6x y1Ane0jMmHiYBRIoMxkltl5bzT6BUW4WwooFjIyrGCVTC4pz01OLTQuM8lLL9YoTc4tL89L1 kvNzNzGCU4uW1w7Ghw8+6B1iZOJgPMQowcGsJMJrcexLvBBvSmJlVWpRfnxRaU5q8SFGaQ4W JXHeHQYP4oUE0hNLUrNTUwtSi2CyTBycUg1MouWO3ZMcRQ4duBrQKnBz38pvClPu2WqbBMfF 5Aq8fsYtGSpw+smd3PeC9l8f3v/+bYf9bbuNro4Nwk9ediq8Tme4cbD4gUrJTIVljzzO+b5v t7knp//IUPH1PQ4+126fPIFX0+tOGc3vlyto52UR5bC5+G7DXkn2oE/Ln7HNWGKmeuCGdoOu TOcnjQ0v6sJjlj8RizPfYqafXRMb/CXX4EHWhU22Dg/3nni6xcrSvqZWdn4p/xLBW3MXmX5l dtnvtoJ3RZpgycfVS8LdxCRnS62paSnVWpvEoWe9fuGlRVIX9vBdTDugqD6vtzyl41Dk3x1N /7PPTOzyeDW/csu2N9Pn86zZuPLl5LC5d0s0lViKMxINtZiLihMB5TcdsJwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsWy7bCSvK625vd4g2t/DSx+rJ7AbPFx2kom iwtPe9gs7jy/wWhxedccNouz846zWXR+mcVm8WTKI1aLoxuDLRZt/cJu0br3CLtF7+Faixvr 2S2ubed14PPYOesuu8emVZ1sHr3N79g8+rasYvQ4fmM7k8fnTXIBbFFcNimpOZllqUX6dglc GQ+mb2Iu6OCu+LPlLXMD4w7OLkZODgkBE4l3v96xdTFycQgJ7GCUuPvkMSNEQlLi88V1TBC2 sMTKf8/ZIYqamCQW/TkEVsQmoCXR+LWLGcQWEYiRWP/vJitIEbPAQyaJld8PgxUJCwRJnO2+ zw5iswioSnRsaAGzeQVcJWY1fWGF2CAncfNcJ9ggTgE3iW/T1gHFOYC2uUo8/BQygZFvASPD KkbJ1ILi3PTcYsMCo7zUcr3ixNzi0rx0veT83E2M4PDV0trBuGfVB71DjEwcjIcYJTiYlUR4 LY59iRfiTUmsrEotyo8vKs1JLT7EKM3BoiTOe6HrZLyQQHpiSWp2ampBahFMlomDU6qBac5H /nSPYJW10ZyrNVdaO+4Tni9SyrQx9MqppqU278oq+x+99vhWYcJ5MGzeH+Wj80IcF7xe/DjA x0wr8qGmyLmo9MSMVuYdVaLxO2TsSrZrHjr9efv+voAz7u8mcj676Vs2xVZ04oQ7S7driU8p MfnJu4HbsFnm/ZTXvHmzJkQtSprAcONI5wndeeEix9LeVV/W/Ppjbb780ZcLIi8yTphyr0fS +su/R2tFTzZt+jZj8vbXD1dsZDFq07l1ca7uLpYlwhun+JQ/+fn4Ps+fm2nvrGZznm/yki38 qXUzf3X01/PbK12f1pdeFfmSGiPx45yPca9Q5Zk+Ie134Zff/711umvzS5aEO+w/t6/L9Puj xFKckWioxVxUnAgARFvAg84CAAA= X-CMS-MailID: 20210107153051epcas5p4f54210f89f8b8d2e18be016521657be0 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153051epcas5p4f54210f89f8b8d2e18be016521657be0 References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for ZRX-DC compliant PHYs. If PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states which increases power consumption. Platforms with ZRX-DC compliant PHY can use "phy-zrxdc-compliant" property in PCIe PHY DT node. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Rob Herring Cc: Kishon Vijay Abraham I Cc: Vidya Sagar --- Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt index d23ff90..73f2fa0 100644 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt @@ -15,6 +15,10 @@ Required properties: Required properties for PHY port node: - #phy-cells: Defined by generic PHY bindings. Must be 0. +Optional properties for other PHY features: +- phy-zrxdc-compliant: This property is needed if phy complies with the + ZRX-DC specification. + Refer to phy/phy-bindings.txt for the generic PHY binding properties. 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Thu, 7 Jan 2021 15:31:03 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Anvesh Salveru , Shradha Todi , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Vidya Sagar , Jonathan Hunter Subject: [PATCH v7 4/5] PCI: tegra: Remove platform driver support for ZRX-DC compliant PHY Date: Thu, 7 Jan 2021 20:58:42 +0530 Message-Id: <1610033323-10560-5-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIKsWRmVeSWpSXmKPExsWy7bCmlm6d0fd4g2tf1S2a/29ntfixegKz xZKmDIuP01YyWbTMWsRicef5DUaLy7vmsFmcnXeczaLzyyw2ize/X7BbPJnyiNXi6MZgi0Vb v7Bb9B6utbixnt3i2nZeBwGPNfPWMHrsnHWX3WPBplKP3uZ3bB59W1YxenzeJBfAFsVlk5Ka k1mWWqRvl8CVcW7dUsaCl+IVHVd2sTcwrhTpYuTkkBAwkVi0+jFTFyMXh5DAbkaJD21rWSCc T4wSv29/YQSpEhL4xiix+Gk1TMelR0vYIYr2Mkrs3n+IEcJpYZLon3eICaSKTUBLovFrFzOI LSIQJTFzeysrSBGzwAZmif8LvrGDJIQFYiVeHjoGVsQioCrx+udSsDivgKtE57k7zBDr5CRu nusEszkF3CS+TVsHNkhCoJdD4tOnnSwQRS4SPRe7oRqEJV4d38IOYUtJvOxvg7LzJaZeeApU zwFkV0gs76mDCNtLHLgyByzMLKApsX6XPkRYVmLqqXVgvzAL8En0/n7CBBHnldgxD8ZWlvjy dw/UBZIS845dZoWwPSQ2nLzFCgmUmYwSz64vYJnAKDcLYcUCRsZVjJKpBcW56anFpgWGeanl esWJucWleel6yfm5mxjBqUbLcwfj3Qcf9A4xMnEwHmKU4GBWEuG1OPYlXog3JbGyKrUoP76o NCe1+BCjNAeLkjjvDoMH8UIC6YklqdmpqQWpRTBZJg5OqQampSmrdrw9mSC2MPjbopsRWg5u f9hOVzbd/eX6xlj+fdlEue3eK/ON/jZtPCFou+5QS13D5jeTM550Pt/B9CCQU/brhUU8Jxb3 T79Rs+FF5R6rE2fmaF/QWfd0gruiyWb7Ky/mfW7IOq6/bOpRm75PUZeXBszILjv2UvbnkrW3 1j18JPCt8B9PtYDV9pgnif0R1Rc3H+U2KH/10kLFwGT+dJHTZ/tfF7YrqeQ8WCBqfsfj1UTO 5TXSKf4N93xDft21aujtummyVD7yZE8W58V4Ts1Jxc93Rx2KuK+0pcfmtL4P1zvR0hdbd3Ev eebz+03ejIVC+Rmn+96lpehfrzXbHPcrcCUv08fcqX+mHIkreafEUpyRaKjFXFScCABxU65U pAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsWy7bCSvK6l5vd4gwMXJSya/29ntfixegKz xZKmDIuP01YyWbTMWsRicef5DUaLy7vmsFmcnXeczaLzyyw2ize/X7BbPJnyiNXi6MZgi0Vb v7Bb9B6utbixnt3i2nZeBwGPNfPWMHrsnHWX3WPBplKP3uZ3bB59W1YxenzeJBfAFsVlk5Ka k1mWWqRvl8CVcW7dUsaCl+IVHVd2sTcwrhTpYuTkkBAwkbj0aAl7FyMXh5DAbkaJNR8/M0Ek JCU+X1wHZQtLrPz3nB3EFhJoYpKY8sABxGYT0JJo/NrFDGKLCMRIrP93kxVkELPAPmaJqZNX MIIkhAWiJebcWwJWxCKgKvH651KwQbwCrhKd5+4wQyyQk7h5rhPM5hRwk/g2bR3QIA6gZa4S Dz+FTGDkW8DIsIpRMrWgODc9t9iwwDAvtVyvODG3uDQvXS85P3cTIziYtTR3MG5f9UHvECMT B+MhRgkOZiURXotjX+KFeFMSK6tSi/Lji0pzUosPMUpzsCiJ817oOhkvJJCeWJKanZpakFoE k2Xi4JRqYCq0vRG1eeeBM6fWp0lm6/l3XSoKzHhql5r75Ei32cnZDFGNRua3v07R8Lw2Y13v st/SdpvK6v5d5F0ivIO764pvwkVT2Ul8/u9tRbdJP3e5LaS5vuPOAam4t4rMya8eVzLOzpBY xj/7WF5Kce4np0mvTU896Xw1YcnLim2sdnO8dtlpilx0jwp6K/vyUPaVk1cfOnTsCvdjE0lb 2/n6Sf/cnhc93fnnlkWuvylxJVhGQoaV98/3Dc7fefefv2fXuWPX60vbAqZZCz9Sfnpuc4dV mK4+14LGf4Z7ApfeOpP/5QzLeg4NrvBQH++TpixzJTY2tZUdqxFQU7VW2HM49H+VxUHrwGKb 3LuSJ59c+KrEUpyRaKjFXFScCAB0HqZM1QIAAA== X-CMS-MailID: 20210107153105epcas5p49ca103794f62faa48c5bedcfc8b4a287 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153105epcas5p49ca103794f62faa48c5bedcfc8b4a287 References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pankaj Dubey As part of dw_pcie_setup(), PHYs which are compliant to ZRX-DC specification are already handled based on "phy-zrxdc-compliant" property in PCIe PHY DT node. So, instead of handling ZRX-DC compliant settings in each platform driver, remove this driver specific code. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Lorenzo Pieralisi Cc: Andrew Murray Cc: Bjorn Helgaas Cc: Vidya Sagar Cc: Jonathan Hunter Reported-by: kernel test robot --- drivers/pci/controller/dwc/pcie-tegra194.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 6fa216e..50e85e5 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -194,7 +194,6 @@ #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) #define GEN3_RELATED_OFF 0x890 -#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) @@ -899,10 +898,6 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp) disable_aspm_l12(pcie); } - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - if (pcie->update_fc_fixup) { val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; @@ -1752,10 +1747,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) disable_aspm_l12(pcie); } - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); @@ -1958,6 +1949,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) { const struct tegra_pcie_dw_of_data *data; struct device *dev = &pdev->dev; + unsigned int phy_zrxdc_count; struct resource *atu_dma_res; struct tegra_pcie_dw *pcie; struct pcie_port *pp; @@ -2066,8 +2058,15 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) dev_err(dev, "Failed to get PHY: %d\n", ret); return ret; } + if (phy_property_present(phys[i], "phy-zrxdc-compliant")) + phy_zrxdc_count++; } + if ((pcie->phy_count) && (pcie->phy_count == phy_zrxdc_count)) + pci->phy_zrxdc_compliant = true; + else + pci->phy_zrxdc_compliant = false; + pcie->phys = phys; atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, From patchwork Thu Jan 7 15:28:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 12004397 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58C3CC433E6 for ; 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Thu, 7 Jan 2021 15:31:16 +0000 (GMT) X-AuditID: b6c32a49-8bfff70000013d42-96-5ff732836832 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id AC.04.13470.44927FF5; Fri, 8 Jan 2021 00:31:16 +0900 (KST) Received: from ubuntu.sa.corp.samsungelectronics.net (unknown [107.108.83.125]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20210107153114epsmtip225d77c13628f28c9d28f6a71d0fbe820~X-OojB6b02044620446epsmtip2e; Thu, 7 Jan 2021 15:31:14 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Cc: pankaj.dubey@samsung.com, sriram.dash@samsung.com, niyas.ahmed@samsung.com, p.rajanbabu@samsung.com, l.mehra@samsung.com, hari.tv@samsung.com, Shradha Todi , Rob Herring , Thierry Reding , Jonathan Hunter , Vidya Sagar Subject: [PATCH v7 5/5] arm64: tegra: Add support for ZRX DC PHY property Date: Thu, 7 Jan 2021 20:58:43 +0530 Message-Id: <1610033323-10560-6-git-send-email-shradha.t@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmleLIzCtJLcpLzFFi42LZdlhTU7fZ6Hu8wf/9ohYfp61ksmiZtYjF 4s7zG4wWl3fNYbM4O+84m0Xnl1lsFk+mPGK1OLox2GLR1i/sFq17j7Bb9B6utbixnt3i5655 LBbXtvM68HnsnHWX3WPTqk42j97md2wefVtWMXp83iQXwBrFZZOSmpNZllqkb5fAldH8bAZT wWeZivsX/7E0ME4W7WLk5JAQMJHYufIAYxcjF4eQwG5GiRmdE9ghnE+MErvPbWaFcL4xSsxe +hbI4QBrebPbECK+l1Gi891dFginhUniz/cbzCBz2QS0JBq/doHZIgJREjO3t4JNYha4yiSx e9Y2dpCEsICnxOup18CmsgioSiz/6wwS5hVwlXje28sOcZ+cxM1znWBzOAXcJL5NWwc2R0Lg J7vE2lu32SCKXCR6JuxkhrCFJV4d3wLVLCXx+d1eqJp8iakXnrJAfFAhsbynDiJsL3Hgyhyw MLOApsT6XfoQYVmJqafWMYHYzAJ8Er2/nzBBxHkldsyDsZUlvvzdwwJhS0rMO3aZFcL2kLj+ fw8zJExmMkrM2raGfQKj3CyEFQsYGVcxSqYWFOempxabFhjmpZbrFSfmFpfmpesl5+duYgSn Ey3PHYx3H3zQO8TIxMF4iFGCg1lJhNfi2Jd4Id6UxMqq1KL8+KLSnNTiQ4zSHCxK4rw7DB7E CwmkJ5akZqemFqQWwWSZODilGpg4vdiVHCfKGL2W17IufvKt+Vvr4aYTu++xvK91exwqtiV5 cvLV28VNT3W+Cuio2t0sCTH7pr5pY3hIb0mdvluJWP5W3qmsdi/8nRtWNgptNa5/trRc6GyE 9e75Oye1T9IN/iy1S231Tg6zXQ0pf/98nPavOrsxL1EiU81Jp7vnpLiuu2Bm6K4TdXMz3wjP v7vlpMv1XRwNm9csl/3MdGxB0K+Fj5K4LrNldtWf0LTt3cwR+TpyRfvWMus383fNtl5u4Cpr dHfq1Wj/mK/C5YW8AW+rhDPnJZdPVbs6IfYsY2f+3/Lwrc/npLk/c3qRZrJtcXNv1jY3z9J6 52BJnmDxYom/E3pDGSTua33drcRSnJFoqMVcVJwIAEVehaeWAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMLMWRmVeSWpSXmKPExsWy7bCSvK6L5vd4g019whYfp61ksmiZtYjF 4s7zG4wWl3fNYbM4O+84m0Xnl1lsFk+mPGK1OLox2GLR1i/sFq17j7Bb9B6utbixnt3i5655 LBbXtvM68HnsnHWX3WPTqk42j97md2wefVtWMXp83iQXwBrFZZOSmpNZllqkb5fAldH8bAZT wWeZivsX/7E0ME4W7WLk4JAQMJF4s9uwi5GLQ0hgN6PEymuL2boYOYHikhKfL65jgrCFJVb+ e84OUdTEJLH77mlWkASbgJZE49cuZhBbRCBGYv2/m2BxZoGHTBKLN2qA2MICnhKvp15jBVnG IqAqsfyvM0iYV8BV4nlvLzvEfDmJm+c6wcZwCrhJfJu2DqxcCKjm4aeQCYx8CxgZVjFKphYU 56bnFhsWGOallusVJ+YWl+al6yXn525iBIerluYOxu2rPugdYmTiYDzEKMHBrCTCa3HsS7wQ b0piZVVqUX58UWlOavEhRmkOFiVx3gtdJ+OFBNITS1KzU1MLUotgskwcnFINTGa3YuZ/K66+ HrI9/dZLTkObJsGVxpuE+VbmVkX/becUuHI9QsndvzG/RWfZJK9PfTtyIrYpbjo4b0GK77lo 1SAmLvZpEqG9DJ+UJC7ZnJK3nlHj+3tK7s2iid37/XnsXzmx/9XYdf/vxU0tla+59be8nOJx i73JatK8VSy2W6f9Ug9J+beBKyV9fcbujk+S6zhuT/PryV90/Z2akJHulNVym/5vEbhivete 6sO9szlP3fTz2fdq7Z8n/26df9v26tpNsyiW7H3LatbnOalafSo//fUb6185h2N7N+ZJPtC4 uWLiOruObz8adt2S8HoSxpRiPn/O/6zLXeZHr0WyXtuY3P3h+Y1KnXYN042KnsFKLMUZiYZa zEXFiQBjRz7exgIAAA== X-CMS-MailID: 20210107153116epcas5p3510286e503e690537d5b2eb7486fa7ab X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210107153116epcas5p3510286e503e690537d5b2eb7486fa7ab References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DesignWare controller driver provides the support to handle the PHYs which are compliant to ZRX-DC specification based on "phy-zrxdc-compliant" DT property. So, add "phy-zrxdc-compliant" property in tegra PCIe PHY DT nodes. Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Cc: Rob Herring Cc: Thierry Reding Cc: Jonathan Hunter Cc: Vidya Sagar To: devicetree@vger.kernel.org To: linux-tegra@vger.kernel.org --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 25f36d6..9d91006 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1006,6 +1006,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_1: phy@3e20000 { @@ -1014,6 +1015,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_2: phy@3e30000 { @@ -1022,6 +1024,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_3: phy@3e40000 { @@ -1030,6 +1033,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_4: phy@3e50000 { @@ -1038,6 +1042,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_5: phy@3e60000 { @@ -1046,6 +1051,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_6: phy@3e70000 { @@ -1054,6 +1060,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_7: phy@3e80000 { @@ -1062,6 +1069,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_8: phy@3e90000 { @@ -1070,6 +1078,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_9: phy@3ea0000 { @@ -1078,6 +1087,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_0: phy@3eb0000 { @@ -1086,6 +1096,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_1: phy@3ec0000 { @@ -1094,6 +1105,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_2: phy@3ed0000 { @@ -1102,6 +1114,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_3: phy@3ee0000 { @@ -1110,6 +1123,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_4: phy@3ef0000 { @@ -1118,6 +1132,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_5: phy@3f00000 { @@ -1126,6 +1141,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_6: phy@3f10000 { @@ -1134,6 +1150,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_nvhs_7: phy@3f20000 { @@ -1142,6 +1159,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_10: phy@3f30000 { @@ -1150,6 +1168,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; p2u_hsio_11: phy@3f40000 { @@ -1158,6 +1177,7 @@ reg-names = "ctl"; #phy-cells = <0>; + phy-zrxdc-compliant; }; hsp_aon: hsp@c150000 {