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client-ip=40.67.248.234; helo=nebula.arm.com; From: Wei Chen To: , , , CC: , , , Subject: [PATCH v2 1/2] xen/arm: Correct the coding style of get_cycles Date: Fri, 8 Jan 2021 14:21:25 +0800 Message-ID: <20210108062126.2335873-1-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f6f6a9ff-4185-4dc9-1060-08d8b39dab1f X-MS-TrafficTypeDiagnostic: VI1PR08MB4493:|VI1PR08MB3789: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:5797;OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 07N2DioM4Snj/j1Yn4beYP6plBRq+2xUED4BgO2IIZYY70PjMkrq3+N3AM8f6qMTtxJcIDL+LPhfunMw5QixuFolPEZ73YGvliSrydqAo2U7ZlbyJ3IgMeJFXAhrlIbGZhnI3NWUY8OcZkFPXhrcl/k3InlKFguVlvIuQNnaTSC+QaxenTXzJsTWs+jG+91H5A3PAHdgb4XT28EcoqVnTARXauxYsLaXvI4Eqx9KOl/q/NruFjTCmPMurZwqDLB3/CPwXroxHb8wZsnaft1isEwDzVmryvI18qMmQGDmLJ0RR2U+qNTUmuWWi6wgs3n0M6WEmkDLLrLsVU22zYZtLsiASrKvHWiP/MN1kBlMTWPn5BoyUJbmWgpqyi6pi9wnJJPmeri7YS/RQ/VPO2mrxmY20UGupZBWIhwVKBcz3tNW4QPHpaeuRoDivu92HXK3xt5H/Cn/J1f3AxwmHNp8+8L6ODcXUBKM2nuujMhukppBDEwqdUbhmeYlRdEOkoQs X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(136003)(396003)(346002)(376002)(39860400002)(46966006)(5660300002)(36756003)(86362001)(7696005)(47076005)(110136005)(54906003)(4326008)(316002)(82740400003)(83380400001)(2616005)(82310400003)(8676002)(34020700004)(70206006)(70586007)(426003)(478600001)(26005)(44832011)(2906002)(186003)(6666004)(336012)(81166007)(1076003)(356005)(8936002);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2021 06:21:43.5032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6f6a9ff-4185-4dc9-1060-08d8b39dab1f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3789 It seems the arm inline function get_cycles has used 8 spaces for line indent since 2012. This patch correct them to 4 spaces and remove extra space between function name and bracket. Signed-off-by: Wei Chen Acked-by: Julien Grall --- xen/include/asm-arm/time.h | 40 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index 1b2c13614b..5c4529ebb5 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -11,29 +11,29 @@ typedef uint64_t cycles_t; -static inline cycles_t get_cycles (void) +static inline cycles_t get_cycles(void) { - isb(); + isb(); + /* + * ARM_WORKAROUND_858921: Cortex-A73 (all versions) counter read + * can return a wrong value when the counter crosses a 32bit boundary. + */ + if ( !check_workaround_858921() ) + return READ_SYSREG64(CNTPCT_EL0); + else + { /* - * ARM_WORKAROUND_858921: Cortex-A73 (all versions) counter read - * can return a wrong value when the counter crosses a 32bit boundary. + * A recommended workaround for erratum 858921 is to: + * 1- Read twice CNTPCT. + * 2- Compare bit[32] of the two read values. + * - If bit[32] is different, keep the old value. + * - If bit[32] is the same, keep the new value. */ - if ( !check_workaround_858921() ) - return READ_SYSREG64(CNTPCT_EL0); - else - { - /* - * A recommended workaround for erratum 858921 is to: - * 1- Read twice CNTPCT. - * 2- Compare bit[32] of the two read values. - * - If bit[32] is different, keep the old value. - * - If bit[32] is the same, keep the new value. - */ - cycles_t old, new; - old = READ_SYSREG64(CNTPCT_EL0); - new = READ_SYSREG64(CNTPCT_EL0); - return (((old ^ new) >> 32) & 1) ? old : new; - } + cycles_t old, new; + old = READ_SYSREG64(CNTPCT_EL0); + new = READ_SYSREG64(CNTPCT_EL0); + return (((old ^ new) >> 32) & 1) ? old : new; + } } /* List of timer's IRQ */ From patchwork Fri Jan 8 06:21:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 12005845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36EF6C433DB for ; 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client-ip=40.67.248.234; helo=nebula.arm.com; From: Wei Chen To: , , , CC: , , , Subject: [PATCH v2 2/2] xen/arm: Add defensive barrier in get_cycles for Arm64 Date: Fri, 8 Jan 2021 14:21:26 +0800 Message-ID: <20210108062126.2335873-2-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108062126.2335873-1-wei.chen@arm.com> References: <20210108062126.2335873-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3e040b95-5e46-4933-8aee-08d8b39dacb6 X-MS-TrafficTypeDiagnostic: DBBPR08MB5978:|PR2PR08MB4667: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:10000;OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: FyyXIkxoT4sFLrNywUnA5kiJO5z8nGDO4iMZipMwNEe4cnKmfHuV05iLW+hy65EGJt6TIqWaSVdiGpnwcxB5mCJGY3Y+Woxhz4wwHDnmhn3LvzlMTkjtzwHRrA0VLEZ4AmUQgeHy+7Bbdp9rueg6aSPs0LN+23AwSWhwmAGXSnAJExW1N/2+RmgL/KrtmoGOhMKAY1Z/+LXRoxuZdZqKWOJJblo0HqgRBbndEN55Si7aMIV66c/oUo/lrTMG9m6LTDXDJrtNgtF9qSIgu8ted6jc1W8Y2uJcSRB/AT54zNOMmufIHWJruaPYMgrRDW+6kv+mzCmzA1IC3Mt/DlG4HwPYqZfmqE9Qw7sZL3XNaWUD1w7kOJDzKBCd6ipqbTo5n5t9p81qz7f1jGMd59nlQiClMw2lch3oVs27ELIUJ8aySFt6MZpLkCmubn9V2Yv4Mu+FdsEmMnKg5iWkvHfUFmifytyNFF8w+HbFVsgHVMoLS1uLQhIXrbY+iz5y3Ea/FRagc6UgugR1UzLY4TIYu1qcZ42Di9YXSoUtIYB6S8ViczXjzJ2chMSOzd801TttvlOQnRudAtlsnWFdhjLyFqwCipTCO3VAuy98vZ178BE= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(346002)(376002)(136003)(396003)(39860400002)(46966006)(316002)(110136005)(356005)(478600001)(6666004)(2616005)(36756003)(336012)(426003)(2906002)(1076003)(8936002)(44832011)(8676002)(86362001)(70586007)(70206006)(83380400001)(966005)(7696005)(82740400003)(4326008)(47076005)(186003)(54906003)(81166007)(5660300002)(34020700004)(26005)(82310400003)(87944003);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2021 06:21:46.1197 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e040b95-5e46-4933-8aee-08d8b39dacb6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT041.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR2PR08MB4667 Per the discussion [1] on the mailing list, we'd better to have a barrier after reading CNTPCT in get_cycles. If there is not any barrier there. When get_cycles being used in some seqlock critical context in the future, the seqlock can be speculated potentially. We import Linux commit 75a19a0202db21638a1c2b424afb867e1f9a2376: arm64: arch_timer: Ensure counter register reads occur with seqlock held When executing clock_gettime(), either in the vDSO or via a system call, we need to ensure that the read of the counter register occurs within the seqlock reader critical section. This ensures that updates to the clocksource parameters (e.g. the multiplier) are consistent with the counter value and therefore avoids the situation where time appears to go backwards across multiple reads. Extend the vDSO logic so that the seqlock critical section covers the read of the counter register as well as accesses to the data page. Since reads of the counter system registers are not ordered by memory barrier instructions, introduce dependency ordering from the counter read to a subsequent memory access so that the seqlock memory barriers apply to the counter access in both the vDSO and the system call paths. Cc: Cc: Marc Zyngier Tested-by: Vincenzo Frascino Link: https://lore.kernel.org/linux-arm-kernel/alpine.DEB.2.21.1902081950260.1662@nanos.tec.linutronix.de/ Reported-by: Thomas Gleixner Signed-off-by: Will Deacon While we are not aware of such use in Xen, it would be best to add the barrier to avoid any suprise. In order to reduce the impact of new barrier, we perfer to use enforce order instead of ISB [2]. Currently, enforce order is not applied to arm32 as this is not done in Linux at the date of this patch. If this is done in Linux it will need to be also done in Xen. [1] https://lists.xenproject.org/archives/html/xen-devel/2020-12/msg00181.html [2] https://lkml.org/lkml/2020/3/13/645 Signed-off-by: Wei Chen Reviewed-by: Julien Grall --- v1 -> v2: 1. Update commit message to refer Linux commit. 2. Change u64 to uint64_t --- xen/include/asm-arm/time.h | 43 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index 5c4529ebb5..6b8fd839dd 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -11,9 +11,26 @@ typedef uint64_t cycles_t; -static inline cycles_t get_cycles(void) +/* + * Ensure that reads of the counter are treated the same as memory reads + * for the purposes of ordering by subsequent memory barriers. + */ +#if defined(CONFIG_ARM_64) +#define read_cntpct_enforce_ordering(val) do { \ + uint64_t tmp, _val = (val); \ + \ + asm volatile( \ + "eor %0, %1, %1\n" \ + "add %0, sp, %0\n" \ + "ldr xzr, [%0]" \ + : "=r" (tmp) : "r" (_val)); \ +} while (0) +#else +#define read_cntpct_enforce_ordering(val) do {} while (0) +#endif + +static inline cycles_t read_cntpct_stable(void) { - isb(); /* * ARM_WORKAROUND_858921: Cortex-A73 (all versions) counter read * can return a wrong value when the counter crosses a 32bit boundary. @@ -36,6 +53,28 @@ static inline cycles_t get_cycles(void) } } +static inline cycles_t get_cycles(void) +{ + cycles_t cnt; + + isb(); + cnt = read_cntpct_stable(); + + /* + * If there is not any barrier here. When get_cycles being used in + * some seqlock critical context in the future, the seqlock can be + * speculated potentially. + * + * To prevent seqlock from being speculated silently, we add a barrier + * here defensively. Normally, we just need an ISB here is enough, but + * considering the minimum performance cost. We prefer to use enforce + * order here. + */ + read_cntpct_enforce_ordering(cnt); + + return cnt; +} + /* List of timer's IRQ */ enum timer_ppi {