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client-ip=40.67.248.234; helo=nebula.arm.com; From: Wei Chen To: , , , CC: , , , Subject: [PATCH v2] xen/arm: Using unsigned long for arm64 MPIDR mask Date: Fri, 8 Jan 2021 14:29:53 +0800 Message-ID: <20210108062953.2335932-1-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 24a770b4-8a4f-41f1-d1e8-08d8b39edecd X-MS-TrafficTypeDiagnostic: DB9PR08MB6331:|AM0PR08MB3987: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:3044;OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: niW4UJRmMyarIW+3oiswZvl0gj/StBPE9G/nGMKgcSmpNZcEMmuFzvTdJJhxpPekHi6KaqPccJ95Cy2Vrufkbzu/AdVnpIxM/PZa3Wxs7jyZWvbsa3a2DYcck+y//4q5kVZbwp7j+8Ad75Ygq45ThM+cLfOJrHRTZK3bVKDJ4fXIqm+Qg/VowkzdKFSU/xqAQcF3iMEoL9l54KgScK3j3C17T3NYesEJaLwsX/AMQbQPbsZCBc38FYy2a2DsgQxKcUilBsjSVzLNwy+y3Orr8ZI0U5ShTofA//XWLqcgzpT1JE3u3LC2qs25scdW5Z8VmSH3dakDHBrd/0i3Un01cmqPVWEI+j9RIaUZF+na/76J6hIWGwsnlR23X7NMk9CJH3y3nyet+qBejiLl92R3O2+UhPGUrN4IL6UFtmUsic6dj78c2ABh2bqggBbmDC/CF6Q+uv64orWFHwdt3aE2MH+E12QWCtXuWVWjkMONjS+J4teBXZRjjYa3QT5swc+s X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(39860400002)(396003)(346002)(136003)(376002)(46966006)(8676002)(6666004)(2616005)(86362001)(7696005)(26005)(44832011)(70206006)(478600001)(70586007)(82740400003)(34020700004)(336012)(316002)(8936002)(82310400003)(54906003)(81166007)(4326008)(36756003)(110136005)(426003)(1076003)(2906002)(47076005)(356005)(5660300002)(186003)(83380400001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2021 06:30:19.6560 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24a770b4-8a4f-41f1-d1e8-08d8b39edecd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB3987 Currently, Xen is using UINT32 for MPIDR mask to retrieve affinity[0,1,2,3] values for MPIDR_EL1 register. The value of MPIDR_EL1 is 64-bit unsigned long. The 32-bit unsinged integer will do unsigned extend while doing some operations with 64-bit unsigned integer. This can lead to unexpected result in some use cases. For example, in gicv3_send_sgi_list of GICv3 driver: uint64_t cluster_id = cpu_logical_map(cpu) & ~MPIDR_AFF0_MASK; When MPIDR_AFF0_MASK is 0xFFU, compiler output: f7c: 92785c16 and x22, x0, #0xffffff00 When MPIDR_AFF0_MASK is 0xFFUL, compiler output: f88: 9278dc75 and x21, x3, #0xffffffffffffff00 If cpu_logical_map(cpu) = 0x100000000UL and MPIDR_AFF0_MASK is 0xFFU, the cluster_id returns 0. But the expected value should be 0x100000000. So, in this patch, we force aarch64 to use unsigned long as MPIDR mask to avoid such unexpected results. Signed-off-by: Wei Chen Reviewed-by: Julien Grall Reviewed-by: Bertrand Marquis --- v1 -> v2: 1. Remove inaccurate descriptions 2. Update example description --- xen/include/asm-arm/processor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 87c8136022..5c1768cdec 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -75,11 +75,11 @@ /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30) -#define MPIDR_UP (_AC(1,U) << _MPIDR_UP) +#define MPIDR_UP (_AC(1,UL) << _MPIDR_UP) #define _MPIDR_SMP (31) -#define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP) +#define MPIDR_SMP (_AC(1,UL) << _MPIDR_SMP) #define MPIDR_AFF0_SHIFT (0) -#define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT) +#define MPIDR_AFF0_MASK (_AC(0xff,UL) << MPIDR_AFF0_SHIFT) #ifdef CONFIG_ARM_64 #define MPIDR_HWID_MASK _AC(0xff00ffffff,UL) #else