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Mon, 11 Jan 2021 22:33:15 -0500 (EST) From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/intc: Add Loongson Inter Processor Interrupt controller Date: Tue, 12 Jan 2021 11:32:52 +0800 Message-Id: <20210112033253.138140-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210112033253.138140-1-jiaxun.yang@flygoat.com> References: <20210112033253.138140-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Received-SPF: permerror client-ip=66.111.4.224; envelope-from=jiaxun.yang@flygoat.com; helo=new2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Loongson IPI controller is a MMIO based simple level triggered interrupt controller. It will trigger IRQ to it's upstream processor when set register is written. It also has 8 32bit mailboxes to pass boot information to secondary processor. Signed-off-by: Jiaxun Yang --- hw/intc/Kconfig | 3 + hw/intc/loongson_ipi.c | 146 +++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + include/hw/intc/loongson_ipi.h | 20 +++++ 4 files changed, 170 insertions(+) create mode 100644 hw/intc/loongson_ipi.c create mode 100644 include/hw/intc/loongson_ipi.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index c18d11142a..0e15102662 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -59,6 +59,9 @@ config RX_ICU config LOONGSON_LIOINTC bool +config LOONGSON_IPI + bool + config SIFIVE_CLINT bool diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c new file mode 100644 index 0000000000..7246f05f9e --- /dev/null +++ b/hw/intc/loongson_ipi.c @@ -0,0 +1,146 @@ +/* + * QEMU Loongson Inter Processor Interrupt Controller + * + * Copyright (c) 2020-2021 Jiaxun Yang + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/module.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/intc/loongson_ipi.h" + +#define R_ISR 0 +#define R_IEN 1 +#define R_SET 2 +#define R_CLR 3 +/* No register between 0x10~0x20 */ +#define R_MBOX0 8 +#define NUM_MBOX 8 +#define R_END 16 + +struct loongson_ipi { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq parent_irq; + + uint32_t isr; + uint32_t ien; + uint32_t mbox[NUM_MBOX]; +}; + +static uint64_t +ipi_read(void *opaque, hwaddr addr, unsigned int size) +{ + struct loongson_ipi *p = opaque; + uint64_t r = 0; + + addr >>= 2; + switch (addr) { + case R_ISR: + r = p->isr; + break; + case R_IEN: + r = p->ien; + break; + case R_MBOX0 ... (R_END - 1): + r = p->mbox[addr - R_MBOX0]; + break; + default: + break; + } + + qemu_log_mask(CPU_LOG_INT, + "%s: size=%d, addr=%"HWADDR_PRIx", val=%"PRIx64"\n", + __func__, size, addr, r); + + return r; +} + +static void +ipi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + struct loongson_ipi *p = opaque; + uint32_t value = val64; + + addr >>= 2; + switch (addr) { + case R_ISR: + /* Do nothing */ + break; + case R_IEN: + p->ien = value; + break; + case R_SET: + p->isr |= value; + break; + case R_CLR: + p->isr &= ~value; + break; + case R_MBOX0 ... (R_END - 1): + p->mbox[addr - R_MBOX0] = value; + break; + default: + break; + } + p->isr &= p->ien; + + qemu_log_mask(CPU_LOG_INT, + "%s: size=%d, addr=%"HWADDR_PRIx", val=%"PRIx32"\n", + __func__, size, addr, value); + + qemu_set_irq(p->parent_irq, !!p->isr); +} + +static const MemoryRegionOps pic_ops = { + .read = ipi_read, + .write = ipi_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void loongson_ipi_init(Object *obj) +{ + struct loongson_ipi *p = LOONGSON_IPI(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); + + memory_region_init_io(&p->mmio, obj, &pic_ops, p, "loongson.ipi", + R_END * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); +} + +static const TypeInfo loongson_ipi_info = { + .name = TYPE_LOONGSON_IPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(struct loongson_ipi), + .instance_init = loongson_ipi_init, +}; + +static void loongson_ipi_register_types(void) +{ + type_register_static(&loongson_ipi_info); +} + +type_init(loongson_ipi_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 53cba11569..5257c5fb94 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -36,6 +36,7 @@ specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c')) specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h new file mode 100644 index 0000000000..a535c467bf --- /dev/null +++ b/include/hw/intc/loongson_ipi.h @@ -0,0 +1,20 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2020-2021 Jiaxun Yang + * + */ + +#ifndef LOONGSON_IPI_H +#define LOONGSON_IPI_H + +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_LOONGSON_IPI "loongson.ipi" +#define LOONGSON_IPI(obj) OBJECT_CHECK(struct loongson_ipi, (obj), TYPE_LOONGSON_IPI) + +#endif /* LOONGSON_IPI_H */ From patchwork Tue Jan 12 03:32:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 12012313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38F66C433DB for ; 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Mon, 11 Jan 2021 22:33:19 -0500 (EST) From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/mips/loongson3_virt: Add TCG SMP support Date: Tue, 12 Jan 2021 11:32:53 +0800 Message-Id: <20210112033253.138140-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210112033253.138140-1-jiaxun.yang@flygoat.com> References: <20210112033253.138140-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Received-SPF: permerror client-ip=66.111.4.224; envelope-from=jiaxun.yang@flygoat.com; helo=new2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" loongson3_virt has KVM SMP support in kenrel. This patch adds TCG SMP support by enable IPI controller for machine. Note that TCG SMP can only support up to 4 CPUs as we didn't implement multi-node support. Signed-off-by: Jiaxun Yang --- hw/mips/Kconfig | 1 + hw/mips/loongson3_bootp.h | 1 + hw/mips/loongson3_virt.c | 20 +++++++++++++++++++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index aadd436bf4..4fb0cc49e8 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -39,6 +39,7 @@ config LOONGSON3V select SERIAL select GOLDFISH_RTC select LOONGSON_LIOINTC + select LOONGSON_IPI if TCG select PCI_DEVICES select PCI_EXPRESS_GENERIC_BRIDGE select MSI_NONBROKEN diff --git a/hw/mips/loongson3_bootp.h b/hw/mips/loongson3_bootp.h index 09f8480abf..4756aa44f6 100644 --- a/hw/mips/loongson3_bootp.h +++ b/hw/mips/loongson3_bootp.h @@ -210,6 +210,7 @@ enum { VIRT_PCIE_ECAM, VIRT_BIOS_ROM, VIRT_UART, + VIRT_IPIS, VIRT_LIOINTC, VIRT_PCIE_MMIO, VIRT_HIGHMEM diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index d4a82fa536..0684a035b0 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -35,6 +35,7 @@ #include "hw/boards.h" #include "hw/char/serial.h" #include "hw/intc/loongson_liointc.h" +#include "hw/intc/loongson_ipi.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/mips/fw_cfg.h" @@ -59,6 +60,7 @@ #define PM_CNTL_MODE 0x10 +#define LOONGSON_TCG_MAX_VCPUS 4 #define LOONGSON_MAX_VCPUS 16 /* @@ -71,6 +73,7 @@ #define UART_IRQ 0 #define RTC_IRQ 1 #define PCIE_IRQ_BASE 2 +#define IPI_REG_SPACE 0x100 const struct MemmapEntry virt_memmap[] = { [VIRT_LOWMEM] = { 0x00000000, 0x10000000 }, @@ -81,6 +84,7 @@ const struct MemmapEntry virt_memmap[] = { [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 }, [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 }, [VIRT_UART] = { 0x1fe001e0, 0x8 }, + [VIRT_IPIS] = { 0x3ff01000, 0x400 }, [VIRT_LIOINTC] = { 0x3ff01400, 0x64 }, [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */ @@ -495,6 +499,10 @@ static void mips_loongson3_virt_init(MachineState *machine) error_report("Loongson-3/TCG needs cpu type Loongson-3A1000"); exit(1); } + if (machine->smp.cpus > LOONGSON_TCG_MAX_VCPUS) { + error_report("Loongson-3/TCG supports up to 4 CPUs"); + exit(1); + } } else { if (!machine->cpu_type) { machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000"); @@ -545,7 +553,17 @@ static void mips_loongson3_virt_init(MachineState *machine) qemu_register_reset(main_cpu_reset, cpu); if (i >= 4) { - continue; /* Only node-0 can be connected to LIOINTC */ + continue; /* Only node-0 can be connected to LIOINTC and IPI */ + } + + if (!kvm_enabled()) { + /* IPI is handled by kernel for KVM */ + DeviceState *ipi; + ipi = qdev_new(TYPE_LOONGSON_IPI); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(ipi), 0, + virt_memmap[VIRT_IPIS].base + IPI_REG_SPACE * i); + sysbus_connect_irq(SYS_BUS_DEVICE(ipi), 0, cpu->env.irq[6]); } for (ip = 0; ip < 4 ; ip++) {