From patchwork Sat Nov 10 21:02:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 10677429 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 681D015A6 for ; Sat, 10 Nov 2018 21:02:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5883C2C40A for ; Sat, 10 Nov 2018 21:02:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D33C2C410; Sat, 10 Nov 2018 21:02:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=BAYES_00,DKIM_ADSP_ALL, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DB5882C40A for ; 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Received: from rere.qmqm.pl ([91.227.64.183]) by merlin.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gLaOo-0008Pl-RS for linux-arm-kernel@lists.infradead.org; Sat, 10 Nov 2018 21:02:35 +0000 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 42sqFH0pGMzSL; Sat, 10 Nov 2018 22:01:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1541883683; bh=0EVKyGgqyMdhKmcjfkXV4TTARorA61c/lj+NDszHBqc=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=AnhvO/nT9Zkc95KHULdvrHD6ryd4/zPEnJsiSLAIVJhuNCFBtYrgaZJD+LWyYhFeo INeBlPnBpKfIVNi44AuiG+xuek4gWMqy8Lv0AK+t155m2ddg9bdmZEwTor8DsT59oQ hJn3llf9+tRkdSUXX6Dj4YD5jru8VXmdIiwwZ45OsYmrjGd6YC8S6XMRs0011lJKIY 2PbuluPSqh+57BQ/IGXY1qzP+nYc2bAlQZ1XAuAgJhHl7hArAnHADut+xM7fq4owor oXPymteBOzPK5VHI8P6yf5qZ04IHMPR1dIa5Hv5gVEK/NHRAlrNLJ/Q+E2qP0uqjn2 5cnVxmbjvu7qQ== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.2 at mail Date: Sat, 10 Nov 2018 22:02:22 +0100 Message-Id: In-Reply-To: References: From: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH 1/3] ARM: cache-l2x0: share l2x0_base with PMU code MIME-Version: 1.0 To: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181110_160235_236217_6C467F37 X-CRM114-Status: GOOD ( 15.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Mark Rutland , Dmitry Osipenko , Russell King Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Avoid l2x0_base duplication with PMU driver by sharing it and using l2x0_name as the 'enabled' flag instead. Since l2x0_name is not used for anything else, mark it as __initdata. This will also be needed for cache maintenance with Trusted Foundations firmware. Signed-off-by: Michał Mirosław --- arch/arm/include/asm/hardware/cache-l2x0.h | 6 ++++-- arch/arm/mm/cache-l2x0-pmu.c | 9 +++------ arch/arm/mm/cache-l2x0.c | 6 +++--- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 736292b42fca..665eb0758417 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -167,11 +167,11 @@ static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) #endif #ifdef CONFIG_CACHE_L2X0_PMU -void l2x0_pmu_register(void __iomem *base, u32 part); +void l2x0_pmu_register(u32 part); void l2x0_pmu_suspend(void); void l2x0_pmu_resume(void); #else -static inline void l2x0_pmu_register(void __iomem *base, u32 part) {} +static inline void l2x0_pmu_register(u32 part) {} static inline void l2x0_pmu_suspend(void) {} static inline void l2x0_pmu_resume(void) {} #endif @@ -193,6 +193,8 @@ struct l2x0_regs { unsigned long aux2_ctrl; }; +extern void __iomem *l2x0_base; +extern u32 l2x0_way_mask; /* Bitmask of active ways */ extern struct l2x0_regs l2x0_saved_regs; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index afe5b4c7b164..6be335ae4e2f 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -29,11 +29,10 @@ #define PMU_NR_COUNTERS 2 -static void __iomem *l2x0_base; static struct pmu *l2x0_pmu; static cpumask_t pmu_cpu; -static const char *l2x0_name; +static const char *__initdata l2x0_name = NULL; static ktime_t l2x0_pmu_poll_period; static struct hrtimer l2x0_pmu_hrtimer; @@ -491,7 +490,7 @@ void l2x0_pmu_resume(void) l2x0_pmu_enable(l2x0_pmu); } -void __init l2x0_pmu_register(void __iomem *base, u32 part) +void __init l2x0_pmu_register(u32 part) { /* * Determine whether we support the PMU, and choose the name for sysfs. @@ -516,15 +515,13 @@ void __init l2x0_pmu_register(void __iomem *base, u32 part) default: return; } - - l2x0_base = base; } static __init int l2x0_pmu_init(void) { int ret; - if (!l2x0_base) + if (!l2x0_name) return 0; l2x0_pmu = kzalloc(sizeof(*l2x0_pmu), GFP_KERNEL); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ea1e70ff4568..2b6a023fea3f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -48,13 +48,13 @@ struct l2c_init_data { #define CACHE_LINE_SIZE 32 -static void __iomem *l2x0_base; static const struct l2c_init_data *l2x0_data; static DEFINE_RAW_SPINLOCK(l2x0_lock); -static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; +void __iomem *l2x0_base; +u32 l2x0_way_mask; /* Bitmask of active ways */ struct l2x0_regs l2x0_saved_regs; static bool l2x0_bresp_disable; @@ -900,7 +900,7 @@ static int __init __l2c_init(const struct l2c_init_data *data, pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", data->type, cache_id, aux); - l2x0_pmu_register(l2x0_base, cache_id); + l2x0_pmu_register(cache_id); return 0; } From patchwork Sat Nov 10 21:02:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 10677431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0BD5109C for ; Sat, 10 Nov 2018 21:03:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D00762C40A for ; Sat, 10 Nov 2018 21:03:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C42782C40E; Sat, 10 Nov 2018 21:03:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=BAYES_00,DKIM_ADSP_ALL, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 586F92C413 for ; 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Received: from rere.qmqm.pl ([91.227.64.183]) by merlin.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gLaOo-0008Pm-RU for linux-arm-kernel@lists.infradead.org; Sat, 10 Nov 2018 21:02:36 +0000 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 42sqFH3B3NzSP; Sat, 10 Nov 2018 22:01:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1541883683; bh=WebcDRCIJFy5WNQCoErpH9NzmoM8uF/zKeqyHpZVuS0=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=dApjIhB0R97WKHMbSWxvDhrJMFYwTPFkPegYxrcI9UiL5Tkeb8Nd7G8F0c8n4wbK3 ahgQAgB7lYgwr8MgNB+SCHRxqUHPQT/6qPKFzVPTBeRH3AAm8YWGgwapCAuEMpmYWC +h+uC7oQFu1ohA3KLlouxtmLSonik6UP/pnDUEmaG6ja40j8U7rMfriIYfbHvpTSmH i+Mi5ItyAlvYsRrxUcKqIDOw83n3Xe9Sw+NTPzaoXxShiu2VEdrc5uKpDuQ4YlJ+sn qAlbsMwfOg/bCynkbCxuCeCk427PeVu+fCMjmfetn9vYsHz82WfpaK2H0yR1vE4T3l aIebc5kB5gHag== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.2 at mail Date: Sat, 10 Nov 2018 22:02:22 +0100 Message-Id: <7124870dfcabaea33ca3d7623714887f65654646.1541882833.git.mirq-linux@rere.qmqm.pl> In-Reply-To: References: From: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH 2/3] ARM: trusted_foundations: enable L2x0 cache via firmware_ops MIME-Version: 1.0 To: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181110_160235_238107_BF217C68 X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Mark Rutland , Dmitry Osipenko , Russell King Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Use firmware_ops to provide hook for cache initialization through Trusted Foundations firmware, as some writes need Secure mode. Avoid l2x0_base conflict (duplication) with PMU driver by sharing l2x0_name and using l2x0_name as the enable flag there. Signed-off-by: Michał Mirosław --- arch/arm/firmware/trusted_foundations.c | 46 +++++++++++++++++++++++++ arch/arm/mm/cache-l2x0.c | 8 +++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 689e6565abfc..135068119453 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -17,11 +17,19 @@ #include #include #include +#include #include +#include +#include #include +#define TF_CACHE_MAINT 0xfffff100 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CACHE_INIT 1 +#define TF_CACHE_FLUSH 2 +#define TF_CACHE_REENABLE 4 + #define TF_CPU_PM 0xfffffffc #define TF_CPU_PM_S3 0xffffffe3 #define TF_CPU_PM_S2 0xffffffe6 @@ -67,9 +75,47 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_write_sec(unsigned long val, unsigned reg) +{ + unsigned long cur = readl_relaxed(l2x0_base + reg); + + pr_warn("TF: ignoring write_sec[0x%x]: 0x%08lx -> 0x%08lx\n", reg, cur, val); +} + +static void tf_disable_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_FLUSH, l2x0_way_mask); +} + +static void tf_resume_cache(void) +{ + unsigned long aux_val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_REENABLE, aux_val); +} + +static void tf_configure_cache(const struct l2x0_regs *regs) +{ + outer_cache.disable = tf_disable_cache; + outer_cache.resume = tf_resume_cache; +} + +static int tf_init_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_INIT, 0); + + outer_cache.write_sec = tf_write_sec; + outer_cache.configure = tf_configure_cache; + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2b6a023fea3f..f1268e9b35f0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "cache-tauros3.h" #include "cache-aurora-l2.h" @@ -37,6 +38,7 @@ struct l2c_init_data { const char *type; unsigned way_size_0; unsigned num_lock; + void (*init)(void __iomem *, u32 *, u32 *); void (*of_parse)(const struct device_node *, u32 *, u32 *); void (*enable)(void __iomem *, unsigned); void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); @@ -1760,6 +1762,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) u32 cache_id; u32 cache_level = 2; bool nosync = false; + int err; np = of_find_matching_node(NULL, l2x0_ids); if (!np) @@ -1792,6 +1795,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) nosync = of_property_read_bool(np, "arm,outer-sync-disable"); + /* Call firmware init */ + err = call_firmware_op(l2x0_init); + if (err && err != -ENOSYS) + return err; + /* Read back current (default) hardware configuration */ if (data->save) data->save(l2x0_base); From patchwork Sat Nov 10 21:02:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 10677427 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B22115A6 for ; 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Signed-off-by: Michał Mirosław --- arch/arm/firmware/trusted_foundations.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 135068119453..e59f44fcda35 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -30,6 +30,8 @@ #define TF_CACHE_FLUSH 2 #define TF_CACHE_REENABLE 4 +#define TF_GET_PROTOCOL_VERSION 0xfffffffb + #define TF_CPU_PM 0xfffffffc #define TF_CPU_PM_S3 0xffffffe3 #define TF_CPU_PM_S2 0xffffffe6 @@ -39,7 +41,7 @@ static unsigned long cpu_boot_addr; -static void tf_generic_smc(u32 type, u32 arg1, u32 arg2) +static u64 tf_generic_smc(u32 type, u32 arg1, u32 arg2) { register u32 r0 asm("r0") = type; register u32 r1 asm("r1") = arg1; @@ -55,9 +57,10 @@ static void tf_generic_smc(u32 type, u32 arg1, u32 arg2) "mov r4, #0\n\t" "smc #0\n\t" "ldmfd sp!, {r4 - r11}\n\t" - : - : "r" (r0), "r" (r1), "r" (r2) + : "+r" (r0), "+r" (r1) + : "r" (r2) : "memory", "r3", "r12", "lr"); + return ((u64)r1 << 32) | r0; } static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) @@ -110,6 +113,11 @@ static int tf_init_cache(void) } #endif /* CONFIG_CACHE_L2X0 */ +static u32 tf_get_protocol_version(void) +{ + return tf_generic_smc(TF_GET_PROTOCOL_VERSION, 0, 0) >> 48; +} + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, @@ -120,6 +128,12 @@ static const struct firmware_ops trusted_foundations_ops = { void register_trusted_foundations(struct trusted_foundations_platform_data *pd) { + unsigned int protocol = tf_get_protocol_version(); + + pr_info("TF: version %u.%u, protocol %u.%u\n", + pd->version_major, pd->version_minor, + protocol >> 8, protocol & 0xFF); + /* * we are not using version information for now since currently * supported SMCs are compatible with all TF releases @@ -145,5 +159,6 @@ void of_register_trusted_foundations(void) &pdata.version_minor); if (err != 0) panic("Trusted Foundation: missing version-minor property\n"); + register_trusted_foundations(&pdata); }