From patchwork Wed Jan 13 15:49:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12017203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF7E6C433E6 for ; Wed, 13 Jan 2021 15:50:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C505233FC for ; Wed, 13 Jan 2021 15:50:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726289AbhAMPuW (ORCPT ); Wed, 13 Jan 2021 10:50:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726110AbhAMPuW (ORCPT ); Wed, 13 Jan 2021 10:50:22 -0500 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C094CC06179F for ; Wed, 13 Jan 2021 07:49:41 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id f11so3063052ljm.8 for ; Wed, 13 Jan 2021 07:49:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=PRDeZ1RptrSpXSi/4MBnSFXHwVd7YllXBCGpSjrYsoEPi/7Y1o9rDiEcBGOnaad3qC inJ3BCtZLUH94jaYcI0DwaTN1abnmDWIBB+9wOAEGUVmY5WEj2ULLeje5SMF6daEqnfx K69thpcdN0DgbUsNVt5m+f29xH6SnIpZBveAl544A6TSoF5W9wGE3yCY2sFZlK5WZpv9 dxkej9kNmX+E697tHWE5KFAHqdhXeOyRikkKysU5/ZzgcUdOYLGVkP2INN0A1oHr8KSn EDMT5A7+O5X8wCqviYkPE8VF1T/poNqnh3I9XVZ05CHV0wLObAGkRwYaqsYQR3dI1/Is 9l7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=rkYvR3Tf65JyBD2vppWqy8jFguph9JvPQya6DpDdyDBirtbZqfUbIEobmrJ1IOR2N8 DCuy5EygwA7/AunHeXnVfG7aO2HKP7ZBOG+qt8YlDYqU6+0f8qMjwhlQaLHa62fZ6fmh /p9YW8FEWhvvj8nsl/RyOwBZJGLL7jPKL8IFBSOfLLpr8EDiy/iyuKEmw/Nl9bczREy9 TfQiXV1FW8Y6nrEl2/kp5NEqrk/ZWTbwP/eGacA8zWUtnn2txiTwCiTMU6rpeK4mvTaB DNrJabpcgMMeSXIycUQrGWeAtySSorXFloDyqgMWtrhCJBcfkHBzXifJwfE+GmHm2o3/ xDJg== X-Gm-Message-State: AOAM5325ukSHsj7iJ0cNDj3ZCnYGT+Lhb8wHVc43330x1MmznrxHVsnf qt+zKHv1KJU3prFkZrns55DKjw== X-Google-Smtp-Source: ABdhPJxcVYwr2caK/01FCNGWFwz/g53wUnVkIt8xCwISMJNVjJ7LFmOi0/4yN6qAq49u6sQTsMEHyQ== X-Received: by 2002:a2e:b4a7:: with SMTP id q7mr1203647ljm.391.1610552980264; Wed, 13 Jan 2021 07:49:40 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.228.189]) by smtp.gmail.com with ESMTPSA id g13sm246828lfb.43.2021.01.13.07.49.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 07:49:39 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org Subject: [PATCH v4 1/2] dt-bindings: pci: qcom: Document ddrss_sf_tbu clock for sm8250 Date: Wed, 13 Jan 2021 18:49:34 +0300 Message-Id: <20210113154935.3972869-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210113154935.3972869-1-dmitry.baryshkov@linaro.org> References: <20210113154935.3972869-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Document this requirement in devicetree bindings. Signed-off-by: Dmitry Baryshkov Fixes: 458168247ccc ("dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC") --- .../devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..0da458a051b6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -132,8 +132,20 @@ - "master_bus" AXI Master clock - "slave_bus" AXI Slave clock --clock-names: - Usage: required for sdm845 and sm8250 +- clock-names: + Usage: required for sdm845 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "pipe" PIPE clock + +- clock-names: + Usage: required for sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -142,6 +154,7 @@ - "bus_slave" Slave AXI clock - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock - "pipe" PIPE clock - resets: From patchwork Wed Jan 13 15:49:35 2021 Content-Type: text/plain; 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Wed, 13 Jan 2021 07:49:40 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org Subject: [PATCH v4 2/2] PCI: qcom: add support for ddrss_sf_tbu clock Date: Wed, 13 Jan 2021 18:49:35 +0300 Message-Id: <20210113154935.3972869-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210113154935.3972869-1-dmitry.baryshkov@linaro.org> References: <20210113154935.3972869-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index affa2713bf80..e2140aba220a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,10 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 7 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; + int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1133,6 +1135,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + bool has_sf_tbu = of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250"); int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1152,8 +1155,14 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; + if (has_sf_tbu) { + res->clks[6].id = "ddrss_sf_tbu"; + res->num_clks = 7; + } else { + res->num_clks = 6; + } - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) return ret; @@ -1175,7 +1184,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1227,7 +1236,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return 0; err_disable_clocks: - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); err_disable_regulators: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1238,7 +1247,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); }