From patchwork Fri Jan 15 11:23:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q3J5c3RhbCBHdW8gKOmDreaZtik=?= X-Patchwork-Id: 12022301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACDFDC433E0 for ; Fri, 15 Jan 2021 11:30:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 684C1221F7 for ; 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Fri, 15 Jan 2021 03:30:08 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 15 Jan 2021 03:23:37 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 15 Jan 2021 19:23:35 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 15 Jan 2021 19:23:34 +0800 From: Crystal Guo To: , , , Subject: [v7,1/2] dt-binding: reset-controller: mediatek: add YAML schemas Date: Fri, 15 Jan 2021 19:23:30 +0800 Message-ID: <20210115112331.27434-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210115112331.27434-1-crystal.guo@mediatek.com> References: <20210115112331.27434-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210115_063010_439315_CEC58A89 X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, s-anna@ti.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, Yidi.Lin@mediatek.com, Yingjoe.Chen@mediatek.com, stanley.chu@mediatek.com, ikjn@chromium.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add a YAML documentation for Mediatek, which uses ti reset-controller driver directly. The TI reset controller provides a common reset management, and is suitable for Mediatek SoCs. Signed-off-by: Crystal Guo --- .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml new file mode 100644 index 000000000000..85d241cdb0ea --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Reset Controller + +maintainers: + - Crystal Guo + +description: + The bindings describe the reset-controller for Mediatek SoCs, + which is based on TI reset controller. For more detail, please + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +properties: + compatible: + const: mediatek,syscon-reset + + '#reset-cells': + const: 1 + + ti,reset-bits: + description: > + Contains the reset control register information, please refer to + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +required: + - compatible + - '#reset-cells' + - ti,reset-bits + +additionalProperties: false + +examples: + - | + #include + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "mediatek,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; From patchwork Fri Jan 15 11:23:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q3J5c3RhbCBHdW8gKOmDreaZtik=?= X-Patchwork-Id: 12022303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BB06C433DB for ; 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Fri, 15 Jan 2021 19:23:35 +0800 From: Crystal Guo To: , , , Subject: [v7,2/2] reset-controller: ti: introduce an integrated reset handler Date: Fri, 15 Jan 2021 19:23:31 +0800 Message-ID: <20210115112331.27434-3-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210115112331.27434-1-crystal.guo@mediatek.com> References: <20210115112331.27434-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5E853876C392C9C9401EA3500EE0D371DA375EFC9FD4FBEBB67153AC2FA3F1082000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210115_063010_452616_7ADA53F6 X-CRM114-Status: GOOD ( 13.93 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, s-anna@ti.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, Yidi.Lin@mediatek.com, Yingjoe.Chen@mediatek.com, stanley.chu@mediatek.com, ikjn@chromium.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Introduce ti_syscon_reset() to integrate assert and deassert together. If some modules need do serialized assert and deassert operations to reset itself, reset_control_reset can be called for convenience. Such as reset-qcom-aoss.c, it integrates assert and deassert together by 'reset' method. MTK Socs also need this method to perform reset. Signed-off-by: Crystal Guo --- drivers/reset/reset-ti-syscon.c | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index 218370faf37b..a30cb17362a4 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -15,15 +15,24 @@ * GNU General Public License for more details. */ +#include #include #include #include +#include #include #include #include #include +#define MTK_SYSCON_RESET_FLAG BIT(0) +#define MT_RESET_DURATION 10 + +struct mediatek_reset_data { + unsigned int flag; +}; + /** * struct ti_syscon_reset_control - reset control structure * @assert_offset: reset assert control register offset from syscon base @@ -56,6 +65,7 @@ struct ti_syscon_reset_data { struct regmap *regmap; struct ti_syscon_reset_control *controls; unsigned int nr_controls; + const struct mediatek_reset_data *reset_data; }; #define to_ti_syscon_reset_data(rcdev) \ @@ -158,9 +168,32 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, !(control->flags & STATUS_SET); } +static int mtk_syscon_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + int ret; + + ret = ti_syscon_reset_assert(rcdev, id); + if (ret) + return ret; + usleep_range(MT_RESET_DURATION, MT_RESET_DURATION * 2); + + return ti_syscon_reset_deassert(rcdev, id); +} + +static int ti_syscon_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev); + + if (data->reset_data && data->reset_data->flag & MTK_SYSCON_RESET_FLAG) + return mtk_syscon_reset(rcdev, id); + else + return -ENOTSUPP; +} + static const struct reset_control_ops ti_syscon_reset_ops = { .assert = ti_syscon_reset_assert, .deassert = ti_syscon_reset_deassert, + .reset = ti_syscon_reset, .status = ti_syscon_reset_status, }; @@ -182,6 +215,7 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + data->reset_data = of_device_get_match_data(&pdev->dev); list = of_get_property(np, "ti,reset-bits", &size); if (!list || (size / sizeof(*list)) % 7 != 0) { dev_err(dev, "invalid DT reset description\n"); @@ -217,8 +251,13 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) return devm_reset_controller_register(dev, &data->rcdev); } +static const struct mediatek_reset_data mtk_reset_data = { + .flag = MTK_SYSCON_RESET_FLAG, +}; + static const struct of_device_id ti_syscon_reset_of_match[] = { { .compatible = "ti,syscon-reset", }, + { .compatible = "mediatek,syscon-reset", .data = &mtk_reset_data}, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match);