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Sun, 17 Jan 2021 18:49:18 -0800 Envelope-to: git@xilinx.com, michal.simek@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=39926 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1KbV-0001PD-1j; Sun, 17 Jan 2021 18:49:17 -0800 From: Nava kishore Manne To: , , , , , , , CC: , , Nava kishore Manne Subject: [PATCH 1/3] drivers: firmware: Add Pdi load API support Date: Mon, 18 Jan 2021 08:13:16 +0530 Message-ID: <20210118024318.9530-1-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a7bb548-df3e-4bc5-4637-08d8bb5baa34 X-MS-TrafficTypeDiagnostic: CH2PR02MB6614: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1824; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 02:49:24.4106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a7bb548-df3e-4bc5-4637-08d8bb5baa34 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT029.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6614 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds load pdi api support to enable pdi/partial loading from linux. Programmable Device Image (PDI) is combination of headers, images and bitstream files to be loaded. Partial PDI is partial set of image/ images to be loaded. Signed-off-by: Nava kishore Manne --- drivers/firmware/xilinx/zynqmp.c | 17 +++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 9 +++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 7eb9958662dd..a466225b9f9e 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -897,6 +897,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, } EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement); +/** + * zynqmp_pm_load_pdi - Load and process pdi + * @src: Source device where PDI is located + * @address: Pdi src address + * + * This function provides support to load pdi from linux + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_load_pdi(const u32 src, const u64 address) +{ + return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src, + lower_32_bits(address), + upper_32_bits(address), 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi); + /** * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using * AES-GCM core. diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 2a0da841c942..87114ee645b1 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -52,6 +52,9 @@ #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U +/* Loader commands */ +#define PM_LOAD_PDI 0x701 + /* * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration @@ -354,6 +357,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_set_boot_health_status(u32 value); +int zynqmp_pm_load_pdi(const u32 src, const u64 address); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -538,6 +542,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value) { return -ENODEV; } + +static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Mon Jan 18 02:43:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12026259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F224C43381 for ; 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Sun, 17 Jan 2021 18:49:21 -0800 From: Nava kishore Manne To: , , , , , , , CC: , , "Appana Durga Kedareswara rao" , Nava kishore Manne Subject: [PATCH 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager Date: Mon, 18 Jan 2021 08:13:17 +0530 Message-ID: <20210118024318.9530-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210118024318.9530-1-nava.manne@xilinx.com> References: <20210118024318.9530-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1552cab0-9ec4-4a4c-796f-08d8bb5bb2a3 X-MS-TrafficTypeDiagnostic: DM6PR02MB6348: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2449; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ExyduI4f8xrC42gzwdtWs01uYXGz/GIx8j22SoQOAIhrc+cMjwO7CUjRD0Glt5PD4pQLUjmFrFlMULyJv6zJFQqGKfVk9Ot8eBICWxXy9A17aDrmUK/T99O9hZ7/oNhk4VdfSpAMtwMGJwpT/mgKpgW8qZeG6PF0W+lp8FX7XsHZrW6x5wnuijGx5wScgLO8+fvQLn4eQxmaNKTV8Kzkvr2CTKTiZ5i3GCNzlkyONEivXbQXmwmfuNwO1ZFt/2mhUNVwGghJzg9rF05EwMkZ1cBBfvyPjNOBCOI0SnPkT08GTIzAtioWuYACeEUzsobZ3uueqE/s1duGLBJTYHm0d/Ek9tuRoB9Ndigq4qIpItZfh4ejyKnf6qon8VFxPnTFvNzfBdiyTbfxv7JQLSWXpCyp0v/hCC1uWZ3f3Xf9VVBNMzAf9c5B40wwUAKLFYE6IE0XfNaneeoG4t8nwFsNSsN0/TcZy6/k5Npgj8RcCMIjlQam5lBM3p8/Zr3ZceFuQR04vUV8x0H4tWCPytkbR0xbxiLsd1zFwqFx+lvaIaghNntAtysV181UCbL2pDSCbxxVCqxWyaJeLE5hA3DtnQ== X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(136003)(376002)(39850400004)(396003)(346002)(46966006)(47076005)(107886003)(82310400003)(8676002)(5660300002)(36756003)(7636003)(316002)(356005)(70206006)(70586007)(26005)(186003)(4326008)(966005)(82740400003)(7696005)(478600001)(1076003)(2616005)(9786002)(54906003)(2906002)(110136005)(8936002)(6666004)(336012)(36906005)(426003)(102446001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 02:49:38.4991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1552cab0-9ec4-4a4c-796f-08d8bb5bb2a3 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT020.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6348 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Appana Durga Kedareswara rao This patch adds binding doc for versal fpga manager driver. Signed-off-by: Nava kishore Manne Signed-off-by: Appana Durga Kedareswara rao --- .../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml new file mode 100644 index 000000000000..cf3aa7917488 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/fpga/xilinx/xlnx,versal-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx versal-fpga driver. + +maintainers: + - Nava kishore Manne + +description: | +Device Tree versal-fpga bindings for the Versal SOC, Controlled +using Versal SoC firmware interface. + +properties: + compatible: + items: + - enum: + - xlnx,versal-fpga + +required: + - compatible + +Required properties: +- compatible: should contain "xlnx,versal-fpga" + +examples: + - | + versal_fpga: fpga { + compatible = "xlnx,versal-fpga"; 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Sun, 17 Jan 2021 18:49:25 -0800 Envelope-to: git@xilinx.com, michal.simek@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=39926 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l1Kbc-0001PD-P4; Sun, 17 Jan 2021 18:49:25 -0800 From: Nava kishore Manne To: , , , , , , , CC: , , Nava kishore Manne , Appana Durga Kedareswara rao Subject: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver Date: Mon, 18 Jan 2021 08:13:18 +0530 Message-ID: <20210118024318.9530-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210118024318.9530-1-nava.manne@xilinx.com> References: <20210118024318.9530-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 514a065c-4f02-463e-b94b-08d8bb5babc1 X-MS-TrafficTypeDiagnostic: DM6PR02MB4522: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2021 02:49:27.0143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 514a065c-4f02-463e-b94b-08d8bb5babc1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT029.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4522 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds driver for versal fpga manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Nava kishore Manne --- drivers/fpga/Kconfig | 8 ++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c | 149 +++++++++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+) create mode 100644 drivers/fpga/versal-fpga.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 5645226ca3ce..9f779c3a6739 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA to configure the programmable logic(PL) through PS on ZynqMP SoC. +config FPGA_MGR_VERSAL_FPGA + tristate "Xilinx Versal FPGA" + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Select this option to enable FPGA manager driver support for + Xilinx Versal SOC. This driver uses the versal soc firmware + interface to load programmable logic(PL) images + on versal soc. endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index d8e21dfc6778..40c9adb6a644 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c new file mode 100644 index 000000000000..2a42aa78b182 --- /dev/null +++ b/drivers/fpga/versal-fpga.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Constant Definitions */ +#define PDI_SOURCE_TYPE 0xF + +/** + * struct versal_fpga_priv - Private data structure + * @dev: Device data structure + * @flags: flags which is used to identify the PL Image type + */ +struct versal_fpga_priv { + struct device *dev; + u32 flags; +}; + +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t size) +{ + struct versal_fpga_priv *priv; + + priv = mgr->priv; + priv->flags = info->flags; + + return 0; +} + +static int versal_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t size) +{ + struct versal_fpga_priv *priv; + dma_addr_t dma_addr = 0; + char *kbuf; + int ret; + + priv = mgr->priv; + + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + memcpy(kbuf, buf, size); + + wmb(); /* ensure all writes are done before initiate FW call */ + + ret = zynqmp_pm_load_pdi(PDI_SOURCE_TYPE, dma_addr); + + dma_free_coherent(priv->dev, size, kbuf, dma_addr); + + return ret; +} + +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + return 0; +} + +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_OPERATING; +} + +static const struct fpga_manager_ops versal_fpga_ops = { + .state = versal_fpga_ops_state, + .write_init = versal_fpga_ops_write_init, + .write = versal_fpga_ops_write, + .write_complete = versal_fpga_ops_write_complete, +}; + +static int versal_fpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct versal_fpga_priv *priv; + struct fpga_manager *mgr; + int err, ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret < 0) { + dev_err(dev, "no usable DMA configuration"); + return ret; + } + + mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager", + &versal_fpga_ops, priv); + if (!mgr) + return -ENOMEM; + + platform_set_drvdata(pdev, mgr); + + err = fpga_mgr_register(mgr); + if (err) { + dev_err(dev, "unable to register FPGA manager"); + fpga_mgr_free(mgr); + return err; + } + + return 0; +} + +static int versal_fpga_remove(struct platform_device *pdev) +{ + struct fpga_manager *mgr = platform_get_drvdata(pdev); + + fpga_mgr_unregister(mgr); + fpga_mgr_free(mgr); + + return 0; +} + +static const struct of_device_id versal_fpga_of_match[] = { + { .compatible = "xlnx,versal-fpga", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, versal_fpga_of_match); + +static struct platform_driver versal_fpga_driver = { + .probe = versal_fpga_probe, + .remove = versal_fpga_remove, + .driver = { + .name = "versal_fpga_manager", + .of_match_table = of_match_ptr(versal_fpga_of_match), + }, +}; + +module_platform_driver(versal_fpga_driver); + +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_AUTHOR("Appana Durga Kedareswara rao "); +MODULE_DESCRIPTION("Xilinx Versal FPGA Manager"); +MODULE_LICENSE("GPL");