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Mon, 18 Jan 2021 00:50:41 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 01/10] dt-bindings: irq: sun6i-r: Split the binding from sun7i-nmi Date: Sun, 17 Jan 2021 23:50:31 -0600 Message-Id: <20210118055040.21910-2-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005048_534021_B487AFAE X-CRM114-Status: GOOD ( 16.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, Samuel Holland , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional functionality compared to the sun7i/sun9i NMI controller. Among other things, it multiplexes access to up to 128 interrupts corresponding to (and in parallel to) the first 128 GIC SPIs. This means the NMI is no longer the lowest-numbered hwirq at this irqchip, since it is SPI 32 or 96 (depending on SoC). hwirq 0 now corresponds to SPI 0, usually UART0. To allow access to all multiplexed IRQs, the R_INTC requires a new binding where the interrupt number matches the GIC interrupt number. Otherwise, interrupts with hwirq numbers below the NMI would not be representable in the device tree. For simplicity, copy the three-cell GIC binding; this disambiguates interrupt 0 in the old binding (the NMI) from interrupt 0 in the new binding (SPI 0) by the number of cells. Because the H6 R_INTC has a different mapping from multiplexed IRQs to top-level register bits, it is no longer compatible with the A31 R_INTC. Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Samuel Holland --- .../allwinner,sun6i-a31-r-intc.yaml | 66 +++++++++++++++++++ .../allwinner,sun7i-a20-sc-nmi.yaml | 10 --- 2 files changed, 66 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml new file mode 100644 index 000000000000..50e607e607c8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + "#interrupt-cells": + const: 3 + description: + The first cell is GIC_SPI (0), the second cell is the IRQ number, and + the third cell is the trigger type as defined in interrupt.txt in this + directory. + + compatible: + oneOf: + - const: allwinner,sun6i-a31-r-intc + - items: + - enum: + - allwinner,sun8i-a83t-r-intc + - allwinner,sun50i-a64-r-intc + - const: allwinner,sun6i-a31-r-intc + - const: allwinner,sun50i-h6-r-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + The GIC interrupt labeled as "External NMI". + + interrupt-controller: true + +required: + - "#interrupt-cells" + - compatible + - reg + - interrupts + - interrupt-controller + +additionalProperties: false + +examples: + - | + #include + + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun50i-a64-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 4fd1e2780026..7fc9ad5ef38c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -22,26 +22,16 @@ properties: compatible: oneOf: - - const: allwinner,sun6i-a31-r-intc - const: allwinner,sun6i-a31-sc-nmi deprecated: true - const: allwinner,sun7i-a20-sc-nmi - - items: - - const: allwinner,sun8i-a83t-r-intc - - const: allwinner,sun6i-a31-r-intc - items: - const: allwinner,sun8i-v3s-nmi - const: allwinner,sun9i-a80-nmi - const: allwinner,sun9i-a80-nmi - - items: - - const: allwinner,sun50i-a64-r-intc - - const: allwinner,sun6i-a31-r-intc - items: - const: allwinner,sun50i-a100-nmi - const: allwinner,sun9i-a80-nmi - - items: - - const: allwinner,sun50i-h6-r-intc - - const: allwinner,sun6i-a31-r-intc reg: maxItems: 1 From patchwork Mon Jan 18 05:50:32 2021 Content-Type: text/plain; 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Mon, 18 Jan 2021 00:50:42 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 02/10] dt-bindings: irq: sun6i-r: Add a compatible for the H3 Date: Sun, 17 Jan 2021 23:50:32 -0600 Message-Id: <20210118055040.21910-3-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005048_533825_50EC20E7 X-CRM114-Status: GOOD ( 10.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, Samuel Holland , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Allwinner H3 SoC contains an R_INTC that is, as far as we know, compatible with the R_INTC present in other sun8i SoCs starting with the A31. Since the R_INTC hardware is undocumented, introduce a new compatible for the R_INTC variant in this SoC, in case there turns out to be some difference. Acked-by: Maxime Ripard Acked-by: Rob Herring Signed-off-by: Samuel Holland --- .../interrupt-controller/allwinner,sun6i-a31-r-intc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml index 50e607e607c8..4db24b8a9ffe 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - allwinner,sun8i-a83t-r-intc + - allwinner,sun8i-h3-r-intc - allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc - const: allwinner,sun50i-h6-r-intc From patchwork Mon Jan 18 05:50:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12026539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2808C433E6 for ; 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Mon, 18 Jan 2021 00:50:42 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 03/10] irqchip/sun6i-r: Use a stacked irqchip driver Date: Sun, 17 Jan 2021 23:50:33 -0600 Message-Id: <20210118055040.21910-4-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005048_537090_532F89EA X-CRM114-Status: GOOD ( 35.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the original sun4i interrupt controller than the sun7i/sun9i NMI controller. It is used for two distinct purposes: - To control the trigger, latch, and mask for the NMI input pin - To provide the interrupt input for the ARISC coprocessor As this interrupt controller is not documented, information about it comes from vendor-provided firmware blobs and from experimentation. Differences from the sun4i interrupt controller appear to be: - It only has one or two registers of each kind (max 32 or 64 IRQs) - Multiplexing logic is added to support additional inputs - There is no FIQ-related logic - There is no interrupt priority logic In order to fulfill its two purposes, this hardware block combines four types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0 pending" output from this chip, if enabled, is then routed to a SPI IRQ input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect the NMI IRQ seen at the GIC. The NMI is followed by a contiguous block of 15 "direct" (my name for them) IRQ inputs that are connected in parallel to both R_INTC and the GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the IRQs seen at the GIC. Following the direct IRQs are the ARISC's copy of banked IRQs for shared peripherals. These are not relevant to Linux. The remaining IRQs are connected to a multiplexer and provide access to the first (up to) 128 SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs. Because of the 1:1 correspondence between R_INTC and GIC inputs, this is a perfect scenario for using a stacked irqchip driver. We want to hook into setting the NMI trigger type, but not actually handle any IRQ here. To allow access to all multiplexed IRQs, this driver requires a new binding where the interrupt number matches the GIC interrupt number. (This moves the NMI from number 0 to 32 or 96, depending on the SoC.) For simplicity, copy the three-cell GIC binding; this disambiguates interrupt 0 in the old binding (the NMI) from interrupt 0 in the new binding (SPI 0) by the number of cells. Since R_INTC is in the always-on power domain, and its output is visible to the power management coprocessor, a stacked irqchip driver provides a simple way to add wakeup support to any of its IRQs. That is the next patch; for now, just the NMI is moved over. This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatible"). Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm/mach-sunxi/Kconfig | 2 + arch/arm64/Kconfig.platforms | 2 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sun6i-r.c | 284 ++++++++++++++++++++++++++++++++ drivers/irqchip/irq-sunxi-nmi.c | 26 +-- 5 files changed, 292 insertions(+), 23 deletions(-) create mode 100644 drivers/irqchip/irq-sun6i-r.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index eeadb1a4dcfe..e5c2fce281cd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -6,6 +6,8 @@ menuconfig ARCH_SUNXI select CLKSRC_MMIO select GENERIC_IRQ_CHIP select GPIOLIB + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS select PINCTRL select PM_OPP select SUN4I_TIMER diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6eecdef538bd..f2aa1518c6f4 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -17,6 +17,8 @@ config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select ARCH_HAS_RESET_CONTROLLER select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS select PINCTRL select RESET_CONTROLLER help diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 0ac93bfaec61..95221e74ee99 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o +obj-$(CONFIG_ARCH_SUNXI) += irq-sun6i-r.o obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c new file mode 100644 index 000000000000..284b56905eb7 --- /dev/null +++ b/drivers/irqchip/irq-sun6i-r.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * The R_INTC in Allwinner A31 and newer SoCs manages several types of + * interrupts, as shown below: + * + * NMI IRQ DIRECT IRQs MUXED IRQs + * bit 0 bits 1-15^ bits 19-31 + * + * +---------+ +---------+ +---------+ +---------+ + * | NMI Pad | | IRQ d | | IRQ m | | IRQ m+7 | + * +---------+ +---------+ +---------+ +---------+ + * | | | | | | | + * | | | | |......| | + * +------V------+ +------------+ | | | +--V------V--+ | + * | Invert/ | | Write 1 to | | | | | AND with | | + * | Edge Detect | | PENDING[0] | | | | | MUX[m/8] | | + * +-------------+ +------------+ | | | +------------+ | + * | | | | | | | + * +--V-------V--+ +--V--+ | +--V--+ | +--V--+ + * | Set Reset| | GIC | | | GIC | | | GIC | + * | Latch | | SPI | | | SPI |... | ...| SPI | + * +-------------+ | N+d | | | m | | | m+7 | + * | | +-----+ | +-----+ | +-----+ + * | | | | + * +-------V-+ +-V----------+ +---------V--+ +--------V--------+ + * | GIC SPI | | AND with | | AND with | | AND with | + * | N (=32) | | ENABLE[0] | | ENABLE[d] | | ENABLE[19+m/8] | + * +---------+ +------------+ +------------+ +-----------------+ + * | | | + * +------V-----+ +------V-----+ +--------V--------+ + * | Read | | Read | | Read | + * | PENDING[0] | | PENDING[d] | | PENDING[19+m/8] | + * +------------+ +------------+ +-----------------+ + * + * ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as + * the MSGBOX. These IRQs do not map to any GIC SPI. + * + * The H6 variant adds two more (banked) direct IRQs and implements the full + * set of 128 mux bits. This requires a second set of top-level registers. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SUN6I_NMI_CTRL (0x0c) +#define SUN6I_IRQ_PENDING(n) (0x10 + 4 * (n)) +#define SUN6I_IRQ_ENABLE(n) (0x40 + 4 * (n)) +#define SUN6I_MUX_ENABLE(n) (0xc0 + 4 * (n)) + +#define SUN6I_NMI_SRC_TYPE_LEVEL_LOW 0 +#define SUN6I_NMI_SRC_TYPE_EDGE_FALLING 1 +#define SUN6I_NMI_SRC_TYPE_LEVEL_HIGH 2 +#define SUN6I_NMI_SRC_TYPE_EDGE_RISING 3 + +#define SUN6I_NMI_BIT BIT(0) + +#define SUN6I_NMI_NEEDS_ACK ((void *)1) + +#define SUN6I_NR_TOP_LEVEL_IRQS 64 +#define SUN6I_NR_DIRECT_IRQS 16 +#define SUN6I_NR_MUX_BITS 128 + +static void __iomem *base; +static irq_hw_number_t nmi_hwirq; + +static void sun6i_r_intc_ack_nmi(void) +{ + writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0)); +} + +static void sun6i_r_intc_nmi_ack(struct irq_data *data) +{ + if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH) + sun6i_r_intc_ack_nmi(); + else + data->chip_data = SUN6I_NMI_NEEDS_ACK; +} + +static void sun6i_r_intc_nmi_eoi(struct irq_data *data) +{ + /* For oneshot IRQs, delay the ack until the IRQ is unmasked. */ + if (data->chip_data == SUN6I_NMI_NEEDS_ACK && !irqd_irq_masked(data)) { + data->chip_data = NULL; + sun6i_r_intc_ack_nmi(); + } + + irq_chip_eoi_parent(data); +} + +static void sun6i_r_intc_nmi_unmask(struct irq_data *data) +{ + if (data->chip_data == SUN6I_NMI_NEEDS_ACK) { + data->chip_data = NULL; + sun6i_r_intc_ack_nmi(); + } + + irq_chip_unmask_parent(data); +} + +static int sun6i_r_intc_nmi_set_type(struct irq_data *data, unsigned int type) +{ + u32 nmi_src_type; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_FALLING; + break; + case IRQ_TYPE_LEVEL_HIGH: + nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_LOW; + break; + default: + return -EINVAL; + } + + writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL); + + /* + * The "External NMI" GIC input connects to a latch inside R_INTC, not + * directly to the pin. So the GIC trigger type does not depend on the + * NMI pin trigger type. + */ + return irq_chip_set_type_parent(data, IRQ_TYPE_LEVEL_HIGH); +} + +static int sun6i_r_intc_nmi_set_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool state) +{ + if (which == IRQCHIP_STATE_PENDING && !state) + sun6i_r_intc_ack_nmi(); + + return irq_chip_set_parent_state(data, which, state); +} + +static struct irq_chip sun6i_r_intc_nmi_chip = { + .name = "sun6i-r-intc", + .irq_ack = sun6i_r_intc_nmi_ack, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = sun6i_r_intc_nmi_unmask, + .irq_eoi = sun6i_r_intc_nmi_eoi, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = sun6i_r_intc_nmi_set_type, + .irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static int sun6i_r_intc_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + /* Accept the old two-cell binding for the NMI only. */ + if (fwspec->param_count == 2 && fwspec->param[0] == 0) { + *hwirq = nmi_hwirq; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + return 0; + } + + /* Otherwise this binding should match the GIC SPI binding. */ + if (fwspec->param_count < 3) + return -EINVAL; + if (fwspec->param[0] != GIC_SPI) + return -EINVAL; + + *hwirq = fwspec->param[1]; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static int sun6i_r_intc_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct irq_fwspec *fwspec = arg; + struct irq_fwspec gic_fwspec; + unsigned long hwirq; + unsigned int type; + int i, ret; + + ret = sun6i_r_intc_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + if (hwirq + nr_irqs > SUN6I_NR_MUX_BITS) + return -EINVAL; + + /* Construct a GIC-compatible fwspec from this fwspec. */ + gic_fwspec = (struct irq_fwspec) { + .fwnode = domain->parent->fwnode, + .param_count = 3, + .param = { GIC_SPI, hwirq, type }, + }; + + ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) { + if (hwirq == nmi_hwirq) { + irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &sun6i_r_intc_nmi_chip, 0); + irq_set_handler(virq, handle_fasteoi_ack_irq); + } else { + /* Only the NMI is currently supported. */ + return -EINVAL; + } + } + + return 0; +} + +static const struct irq_domain_ops sun6i_r_intc_domain_ops = { + .translate = sun6i_r_intc_domain_translate, + .alloc = sun6i_r_intc_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static void sun6i_r_intc_resume(void) +{ + int i; + + /* Only the NMI is relevant during normal operation. */ + writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0)); + for (i = 1; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i) + writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); +} + +static int __init sun6i_r_intc_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *domain, *parent_domain; + struct of_phandle_args nmi_parent; + int ret; + + /* Extract the NMI hwirq number from the OF node. */ + ret = of_irq_parse_one(node, 0, &nmi_parent); + if (ret) + return ret; + if (nmi_parent.args_count < 3 || + nmi_parent.args[0] != GIC_SPI || + nmi_parent.args[2] != IRQ_TYPE_LEVEL_HIGH) + return -EINVAL; + nmi_hwirq = nmi_parent.args[1]; + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%pOF: Failed to obtain parent domain\n", node); + return -ENXIO; + } + + base = of_io_request_and_map(node, 0, NULL); + if (IS_ERR(base)) { + pr_err("%pOF: Failed to map MMIO region\n", node); + return PTR_ERR(base); + } + + domain = irq_domain_add_hierarchy(parent_domain, 0, 0, node, + &sun6i_r_intc_domain_ops, NULL); + if (!domain) { + pr_err("%pOF: Failed to allocate domain\n", node); + iounmap(base); + return -ENOMEM; + } + + sun6i_r_intc_ack_nmi(); + sun6i_r_intc_resume(); + + return 0; +} +IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init); diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index a412b5d5d0fa..9f2bd0c5d289 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -27,18 +27,12 @@ #define SUNXI_NMI_IRQ_BIT BIT(0) -#define SUN6I_R_INTC_CTRL 0x0c -#define SUN6I_R_INTC_PENDING 0x10 -#define SUN6I_R_INTC_ENABLE 0x40 - /* * For deprecated sun6i-a31-sc-nmi compatible. - * Registers are offset by 0x0c. */ -#define SUN6I_R_INTC_NMI_OFFSET 0x0c -#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET) -#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET) -#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET) +#define SUN6I_NMI_CTRL 0x00 +#define SUN6I_NMI_PENDING 0x04 +#define SUN6I_NMI_ENABLE 0x34 #define SUN7I_NMI_CTRL 0x00 #define SUN7I_NMI_PENDING 0x04 @@ -61,12 +55,6 @@ struct sunxi_sc_nmi_reg_offs { u32 enable; }; -static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = { - .ctrl = SUN6I_R_INTC_CTRL, - .pend = SUN6I_R_INTC_PENDING, - .enable = SUN6I_R_INTC_ENABLE, -}; - static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { .ctrl = SUN6I_NMI_CTRL, .pend = SUN6I_NMI_PENDING, @@ -232,14 +220,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node, return ret; } -static int __init sun6i_r_intc_irq_init(struct device_node *node, - struct device_node *parent) -{ - return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs); -} -IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", - sun6i_r_intc_irq_init); - static int __init sun6i_sc_nmi_irq_init(struct device_node *node, struct device_node *parent) { From patchwork Mon Jan 18 05:50:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12026537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5D57C43381 for ; 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Mon, 18 Jan 2021 00:50:43 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 04/10] irqchip/sun6i-r: Add wakeup support Date: Sun, 17 Jan 2021 23:50:34 -0600 Message-Id: <20210118055040.21910-5-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005048_537830_9C62A9BD X-CRM114-Status: GOOD ( 23.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them to the hardware during the syscore phase of suspend and shutdown. Then restore the original set of enabled IRQs (only the NMI) during resume. This serves two purposes. First, it lets power management firmware running on the ARISC coprocessor know which wakeup sources Linux wants to have enabled. That way, it can avoid turning them off when it shuts down the remainder of the clock tree. Second, it preconfigures the coprocessor's interrupt controller, so the firmware's wakeup logic is as simple as waiting for an interrupt to arrive. The suspend/resume logic is not conditional on PM_SLEEP because it is identical to the init/shutdown logic. Wake IRQs may be enabled during shutdown to allow powering the board back on. As an example, see commit a5c5e50cce9d ("Input: gpio-keys - add shutdown callback"). Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- drivers/irqchip/irq-sun6i-r.c | 107 ++++++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c index 284b56905eb7..4cd3e533740b 100644 --- a/drivers/irqchip/irq-sun6i-r.c +++ b/drivers/irqchip/irq-sun6i-r.c @@ -39,6 +39,7 @@ * set of 128 mux bits. This requires a second set of top-level registers. */ +#include #include #include #include @@ -46,6 +47,7 @@ #include #include #include +#include #include @@ -67,8 +69,17 @@ #define SUN6I_NR_DIRECT_IRQS 16 #define SUN6I_NR_MUX_BITS 128 +struct sun6i_r_intc_variant { + u32 first_mux_irq; + u32 nr_mux_irqs; + u32 mux_valid[BITS_TO_U32(SUN6I_NR_MUX_BITS)]; +}; + static void __iomem *base; static irq_hw_number_t nmi_hwirq; +static DECLARE_BITMAP(wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS); +static DECLARE_BITMAP(wake_mux_enabled, SUN6I_NR_MUX_BITS); +static DECLARE_BITMAP(wake_mux_valid, SUN6I_NR_MUX_BITS); static void sun6i_r_intc_ack_nmi(void) { @@ -145,6 +156,21 @@ static int sun6i_r_intc_nmi_set_irqchip_state(struct irq_data *data, return irq_chip_set_parent_state(data, which, state); } +static int sun6i_r_intc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + unsigned long offset_from_nmi = data->hwirq - nmi_hwirq; + + if (offset_from_nmi < SUN6I_NR_DIRECT_IRQS) + assign_bit(offset_from_nmi, wake_irq_enabled, on); + else if (test_bit(data->hwirq, wake_mux_valid)) + assign_bit(data->hwirq, wake_mux_enabled, on); + else + /* Not wakeup capable. */ + return -EPERM; + + return 0; +} + static struct irq_chip sun6i_r_intc_nmi_chip = { .name = "sun6i-r-intc", .irq_ack = sun6i_r_intc_nmi_ack, @@ -154,8 +180,19 @@ static struct irq_chip sun6i_r_intc_nmi_chip = { .irq_set_affinity = irq_chip_set_affinity_parent, .irq_set_type = sun6i_r_intc_nmi_set_type, .irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state, - .flags = IRQCHIP_SET_TYPE_MASKED | - IRQCHIP_SKIP_SET_WAKE, + .irq_set_wake = sun6i_r_intc_irq_set_wake, + .flags = IRQCHIP_SET_TYPE_MASKED, +}; + +static struct irq_chip sun6i_r_intc_wakeup_chip = { + .name = "sun6i-r-intc", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_set_wake = sun6i_r_intc_irq_set_wake, + .flags = IRQCHIP_SET_TYPE_MASKED, }; static int sun6i_r_intc_domain_translate(struct irq_domain *domain, @@ -215,8 +252,8 @@ static int sun6i_r_intc_domain_alloc(struct irq_domain *domain, &sun6i_r_intc_nmi_chip, 0); irq_set_handler(virq, handle_fasteoi_ack_irq); } else { - /* Only the NMI is currently supported. */ - return -EINVAL; + irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &sun6i_r_intc_wakeup_chip, 0); } } @@ -229,6 +266,22 @@ static const struct irq_domain_ops sun6i_r_intc_domain_ops = { .free = irq_domain_free_irqs_common, }; +static int sun6i_r_intc_suspend(void) +{ + u32 buf[BITS_TO_U32(max(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))]; + int i; + + /* Wake IRQs are enabled during system sleep and shutdown. */ + bitmap_to_arr32(buf, wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS); + for (i = 0; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i) + writel_relaxed(buf[i], base + SUN6I_IRQ_ENABLE(i)); + bitmap_to_arr32(buf, wake_mux_enabled, SUN6I_NR_MUX_BITS); + for (i = 0; i < BITS_TO_U32(SUN6I_NR_MUX_BITS); ++i) + writel_relaxed(buf[i], base + SUN6I_MUX_ENABLE(i)); + + return 0; +} + static void sun6i_r_intc_resume(void) { int i; @@ -239,8 +292,20 @@ static void sun6i_r_intc_resume(void) writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); } +static void sun6i_r_intc_shutdown(void) +{ + sun6i_r_intc_suspend(); +} + +static struct syscore_ops sun6i_r_intc_syscore_ops = { + .suspend = sun6i_r_intc_suspend, + .resume = sun6i_r_intc_resume, + .shutdown = sun6i_r_intc_shutdown, +}; + static int __init sun6i_r_intc_init(struct device_node *node, - struct device_node *parent) + struct device_node *parent, + const struct sun6i_r_intc_variant *v) { struct irq_domain *domain, *parent_domain; struct of_phandle_args nmi_parent; @@ -256,6 +321,9 @@ static int __init sun6i_r_intc_init(struct device_node *node, return -EINVAL; nmi_hwirq = nmi_parent.args[1]; + bitmap_set(wake_irq_enabled, v->first_mux_irq, v->nr_mux_irqs); + bitmap_from_arr32(wake_mux_valid, v->mux_valid, SUN6I_NR_MUX_BITS); + parent_domain = irq_find_host(parent); if (!parent_domain) { pr_err("%pOF: Failed to obtain parent domain\n", node); @@ -276,9 +344,36 @@ static int __init sun6i_r_intc_init(struct device_node *node, return -ENOMEM; } + register_syscore_ops(&sun6i_r_intc_syscore_ops); + sun6i_r_intc_ack_nmi(); sun6i_r_intc_resume(); return 0; } -IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init); + +static const struct sun6i_r_intc_variant sun6i_a31_r_intc_variant __initconst = { + .first_mux_irq = 19, + .nr_mux_irqs = 13, + .mux_valid = { 0xffffffff, 0xfff80000, 0xffffffff, 0x0000000f }, +}; + +static int __init sun6i_a31_r_intc_init(struct device_node *node, + struct device_node *parent) +{ + return sun6i_r_intc_init(node, parent, &sun6i_a31_r_intc_variant); +} +IRQCHIP_DECLARE(sun6i_a31_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_a31_r_intc_init); + +static const struct sun6i_r_intc_variant sun50i_h6_r_intc_variant __initconst = { + .first_mux_irq = 21, + .nr_mux_irqs = 16, + .mux_valid = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }, +}; + +static int __init sun50i_h6_r_intc_init(struct device_node *node, + struct device_node *parent) +{ + return sun6i_r_intc_init(node, parent, &sun50i_h6_r_intc_variant); +} +IRQCHIP_DECLARE(sun50i_h6_r_intc, "allwinner,sun50i-h6-r-intc", sun50i_h6_r_intc_init); From patchwork Mon Jan 18 05:50:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12026535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 203B7C433E0 for ; Mon, 18 Jan 2021 05:52:42 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C48B722512 for ; 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Mon, 18 Jan 2021 00:50:43 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 05/10] ARM: dts: sunxi: Rename nmi_intc to r_intc Date: Sun, 17 Jan 2021 23:50:35 -0600 Message-Id: <20210118055040.21910-6-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005050_427161_1D035E1D X-CRM114-Status: GOOD ( 12.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The R_INTC block controls more than just the NMI, and it is a different hardware block than the NMI INTC found in some other Allwinner SoCs, so the label "nmi_intc" is inaccurate. Name it "r_intc" to match the compatible and to match the few references in the vendor documentation. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +- arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +- arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 2 +- arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 2 +- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 2 +- arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 2 +- arch/arm/boot/dts/sun8i-r16-parrot.dts | 2 +- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 73de34ae37fd..486cec6f71e0 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -226,7 +226,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index a645c8f4257c..6aeb5a9696f7 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -115,7 +115,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index 648f24746234..6c6c1bd22bf6 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -115,7 +115,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index f3425a66fc0a..6a733a36d34a 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -1305,7 +1305,7 @@ rtc: rtc@1f00000 { clock-output-names = "osc32k"; }; - nmi_intc: interrupt-controller@1f00c00 { + r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index bc3170a0b8b5..429a165b79b2 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -159,7 +159,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi index 3099491de8c4..7455c0db4a8a 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi @@ -78,7 +78,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index 367006fb280d..0d124a4a7cf2 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -148,7 +148,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; x-powers,drive-vbus-en; diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index 2504e7189c54..cadc45255d7b 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -98,7 +98,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index 7de2abd541c1..6bf3fbdd738f 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -79,7 +79,7 @@ &p2wi { axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; drivevbus-supply = <®_vcc5v0>; x-powers,drive-vbus-en; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index c1362d0f0ff8..a42fac676b31 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -716,7 +716,7 @@ rtc: rtc@1f00000 { #clock-cells = <1>; }; - nmi_intc: interrupt-controller@1f00c00 { + r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index a1953b2872d0..2c8db949f99f 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -98,7 +98,7 @@ &r_rsb { axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; x-powers,drive-vbus-en; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 785798e3a104..f18ae8a1976e 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -164,7 +164,7 @@ &r_rsb { axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; }; diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index e1c75f7fa3ca..09ec68c64535 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -163,7 +163,7 @@ &r_rsb { axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; x-powers,drive-vbus-en; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 4f48eec6b2ef..9cdc2ed84847 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -164,7 +164,7 @@ &r_rsb { axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; drivevbus-supply = <®_vcc5v0>; x-powers,drive-vbus-en; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index b3d8b8f056cd..8175bf307eb1 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -92,7 +92,7 @@ &r_rsb { axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; + interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; drivevbus-supply = <®_vcc5v0>; From patchwork Mon Jan 18 05:50:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12026541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CD69C433DB for ; Mon, 18 Jan 2021 05:52:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1894922512 for ; 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Mon, 18 Jan 2021 00:50:43 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 06/10] ARM: dts: sunxi: Use the new r_intc binding Date: Sun, 17 Jan 2021 23:50:36 -0600 Message-Id: <20210118055040.21910-7-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005050_465434_D817D423 X-CRM114-Status: GOOD ( 11.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The binding of R_INTC was updated to allow specifying interrupts other than the external NMI, since routing those interrupts through the R_INTC driver allows using them for wakeup. Update the device trees to use the new binding. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +- arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +- arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 2 +- arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 2 +- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 2 +- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 4 ++-- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 4 ++-- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 4 ++-- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++-- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 2 +- arch/arm/boot/dts/sun8i-r16-parrot.dts | 2 +- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +- 20 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 486cec6f71e0..236ebfc06192 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -227,7 +227,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 6aeb5a9696f7..2436b13cbce1 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -116,7 +116,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index 6c6c1bd22bf6..ce712bdd8cd0 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -116,7 +116,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 6a733a36d34a..faf85c5f4e1e 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -1308,7 +1308,7 @@ rtc: rtc@1f00000 { r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; reg = <0x01f00c00 0x400>; interrupts = ; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 429a165b79b2..c5c85eb44cc7 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -160,7 +160,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi index 7455c0db4a8a..227ad489731c 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi @@ -79,7 +79,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index 0d124a4a7cf2..abf742c4d47e 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -149,7 +149,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index cadc45255d7b..0b61f5368d44 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -99,7 +99,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index 6bf3fbdd738f..f38d19c6be8c 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -80,7 +80,7 @@ axp22x: pmic@68 { compatible = "x-powers,axp221"; reg = <0x68>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; drivevbus-supply = <®_vcc5v0>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a42fac676b31..a84c90a660ca 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -719,7 +719,7 @@ rtc: rtc@1f00000 { r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; reg = <0x01f00c00 0x400>; interrupts = ; }; diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index 2c8db949f99f..810fada3db00 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -99,7 +99,7 @@ axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index f18ae8a1976e..66fec9a8c777 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -165,7 +165,7 @@ axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 9c006fc18821..c31c97d16024 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -122,7 +122,7 @@ axp81x: pmic@3a3 { compatible = "x-powers,axp818", "x-powers,axp813"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; swin-supply = <®_dcdc1>; }; @@ -142,7 +142,7 @@ ac100_codec: codec { ac100_rtc: rtc { compatible = "x-powers,ac100-rtc"; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; clocks = <&ac100_codec>; #clock-cells = <1>; clock-output-names = "cko1_rtc", diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 431f70234d36..2e8e1134a852 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -203,7 +203,7 @@ axp81x: pmic@3a3 { compatible = "x-powers,axp813"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; fldoin-supply = <®_dcdc5>; swin-supply = <®_dcdc1>; @@ -225,7 +225,7 @@ ac100_codec: codec { ac100_rtc: rtc { compatible = "x-powers,ac100-rtc"; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; clocks = <&ac100_codec>; #clock-cells = <1>; clock-output-names = "cko1_rtc", diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index d8326a5c681d..f15eb782bca3 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -239,7 +239,7 @@ axp81x: pmic@3a3 { compatible = "x-powers,axp818", "x-powers,axp813"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; swin-supply = <®_dcdc1>; x-powers,drive-vbus-en; @@ -260,7 +260,7 @@ ac100_codec: codec { ac100_rtc: rtc { compatible = "x-powers,ac100-rtc"; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; clocks = <&ac100_codec>; #clock-cells = <1>; clock-output-names = "cko1_rtc", diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index bfc9bb277a49..1a146e200cde 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -263,7 +263,7 @@ axp81x: pmic@3a3 { compatible = "x-powers,axp813"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; swin-supply = <®_dcdc1>; x-powers,drive-vbus-en; }; @@ -283,7 +283,7 @@ ac100_codec: codec { ac100_rtc: rtc { compatible = "x-powers,ac100-rtc"; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; clocks = <&ac100_codec>; #clock-cells = <1>; clock-output-names = "cko1_rtc", diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c010b27fdb6a..0fce227f56d4 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1114,7 +1114,7 @@ r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun8i-a83t-r-intc", "allwinner,sun6i-a31-r-intc"; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; reg = <0x01f00c00 0x400>; interrupts = ; }; diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index 09ec68c64535..8e8ecdcd3a83 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -164,7 +164,7 @@ axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 9cdc2ed84847..de4bce5f89a8 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -165,7 +165,7 @@ axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; drivevbus-supply = <®_vcc5v0>; x-powers,drive-vbus-en; }; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 8175bf307eb1..d71ea3637850 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -93,7 +93,7 @@ axp22x: pmic@3a3 { compatible = "x-powers,axp223"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; eldoin-supply = <®_dcdc1>; drivevbus-supply = <®_vcc5v0>; x-powers,drive-vbus-en; From patchwork Mon Jan 18 05:50:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12026531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83A96C433E6 for ; Mon, 18 Jan 2021 05:52:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 47C0B22522 for ; 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Mon, 18 Jan 2021 00:50:44 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 07/10] ARM: dts: sunxi: h3/h5: Add r_intc node Date: Sun, 17 Jan 2021 23:50:37 -0600 Message-Id: <20210118055040.21910-8-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005050_676510_2F705B2E X-CRM114-Status: GOOD ( 11.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The H3 and H5 SoCs have an additional interrupt controller in the RTC power domain that can be used to enable wakeup for certain IRQs. Add a node for it. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 9be13378d4df..4bf25c5b873e 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -859,6 +859,15 @@ rtc: rtc@1f00000 { #clock-cells = <1>; }; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-h3-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; From patchwork Mon Jan 18 05:50:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12026543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42B75C433DB for ; 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Mon, 18 Jan 2021 00:50:44 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 08/10] ARM: dts: sunxi: Move wakeup-capable IRQs to r_intc Date: Sun, 17 Jan 2021 23:50:38 -0600 Message-Id: <20210118055040.21910-9-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005050_675377_A913D79A X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. In addition to the external NMI input, which is already routed through r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++++ arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 ++++ arch/arm/boot/dts/sun8i-a83t.dtsi | 3 +++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +++ 4 files changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index faf85c5f4e1e..50324688c28a 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -611,6 +611,7 @@ ccu: clock@1c20000 { pio: pinctrl@1c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; interrupts = , , , @@ -802,6 +803,7 @@ i2s1: i2s@1c22400 { lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; + interrupt-parent = <&r_intc>; interrupts = ; status = "disabled"; }; @@ -1299,6 +1301,7 @@ rtc: rtc@1f00000 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; + interrupt-parent = <&r_intc>; interrupts = , ; clocks = <&osc32k>; @@ -1383,6 +1386,7 @@ ir: ir@1f02000 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun6i-a31-r-pinctrl"; reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a84c90a660ca..4461d5098b20 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -338,6 +338,7 @@ ccu: clock@1c20000 { pio: pinctrl@1c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; /* interrupts get set in SoC specific dtsi file */ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; @@ -473,6 +474,7 @@ pwm: pwm@1c21400 { lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; + interrupt-parent = <&r_intc>; interrupts = ; status = "disabled"; }; @@ -709,6 +711,7 @@ drc0_out_tcon0: endpoint { rtc: rtc@1f00000 { compatible = "allwinner,sun8i-a23-rtc"; reg = <0x01f00000 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clock-output-names = "osc32k", "osc32k-out"; @@ -805,6 +808,7 @@ r_i2c: i2c@1f02400 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; interrupts = ; clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 0fce227f56d4..2c05e296b3d8 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -708,6 +708,7 @@ ccu: clock@1c20000 { pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; + interrupt-parent = <&r_intc>; interrupts = , , ; @@ -1150,6 +1151,7 @@ r_cir: ir@1f02000 { r_lradc: lradc@1f03c00 { compatible = "allwinner,sun8i-a83t-r-lradc"; reg = <0x01f03c00 0x100>; + interrupt-parent = <&r_intc>; interrupts = ; status = "disabled"; }; @@ -1157,6 +1159,7 @@ r_lradc: lradc@1f03c00 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a83t-r-pinctrl"; reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; interrupts = ; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc16Md512>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4bf25c5b873e..c7428df9469e 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -395,6 +395,7 @@ ccu: clock@1c20000 { pio: pinctrl@1c20800 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; @@ -852,6 +853,7 @@ hdmi_phy: hdmi-phy@1ef0000 { rtc: rtc@1f00000 { /* compatible is in per SoC .dtsi file */ reg = <0x01f00000 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clock-output-names = "osc32k", "osc32k-out", "iosc"; @@ -909,6 +911,7 @@ r_i2c: i2c@1f02400 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; 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Mon, 18 Jan 2021 00:50:45 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 09/10] arm64: dts: allwinner: Use the new r_intc binding Date: Sun, 17 Jan 2021 23:50:39 -0600 Message-Id: <20210118055040.21910-10-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005053_094053_1DE97105 X-CRM114-Status: GOOD ( 11.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The binding of R_INTC was updated to allow specifying interrupts other than the external NMI, since routing those interrupts through the R_INTC driver allows using them for wakeup. Update the device trees to use the new binding. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++-- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 5 ++--- 17 files changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts index c7bd73f35ed8..f17cc89f472d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -173,7 +173,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index e5e840b9fbb4..e45bef292aa3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -191,7 +191,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index e58db8a6cab6..57b64c57781b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -152,7 +152,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index f3f8e177ab61..ec7e2c0e82c1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -185,7 +185,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index 70e31743f0ba..097a5511523a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -192,7 +192,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 329cf276561e..2accb5ddf783 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -139,7 +139,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 7ae16541d14f..34e67f5f8297 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -245,7 +245,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 7f37f9fea0ab..7a38adb7aef9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -289,7 +289,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index 422a8507f674..7ef96f9ff7ae 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -266,7 +266,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; x-powers,drive-vbus-en; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index 3402cec87035..50308077ea8c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -45,7 +45,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index a1864a89fb89..03f733ee44d9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -205,7 +205,7 @@ axp803: pmic@3a3 { compatible = "x-powers,axp803"; reg = <0x3a3>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; wakeup-source; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 57786fc120c3..5bf9d61fab12 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1219,7 +1219,7 @@ r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun50i-a64-r-intc", "allwinner,sun6i-a31-r-intc"; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; reg = <0x01f00c00 0x400>; interrupts = ; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 7c9dbde645b5..5c39f5f3f22c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -157,7 +157,7 @@ axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; reg = <0x36>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 15c9dd8c4479..41aaad43b5d5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -182,7 +182,7 @@ axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; reg = <0x36>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index ebc120a9232f..1ee19f5fc6ab 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -119,7 +119,7 @@ axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; reg = <0x36>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 15ceba027a73..36aee6a3f6f9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -168,7 +168,7 @@ axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; reg = <0x36>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; @@ -281,7 +281,7 @@ pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; #clock-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 77765d4a05ec..15babb635cf7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -927,10 +927,9 @@ r_watchdog: watchdog@7020400 { }; r_intc: interrupt-controller@7021000 { - compatible = "allwinner,sun50i-h6-r-intc", - "allwinner,sun6i-a31-r-intc"; + compatible = "allwinner,sun50i-h6-r-intc"; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; reg = <0x07021000 0x400>; interrupts = ; }; From patchwork Mon Jan 18 05:50:40 2021 Content-Type: text/plain; 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Mon, 18 Jan 2021 00:50:45 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 10/10] arm64: dts: allwinner: Move wakeup-capable IRQs to r_intc Date: Sun, 17 Jan 2021 23:50:40 -0600 Message-Id: <20210118055040.21910-11-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005053_038101_F615FD83 X-CRM114-Status: GOOD ( 11.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. In addition to the external NMI input, which is already routed through r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5bf9d61fab12..5b30e6c1fa05 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -648,6 +648,7 @@ ccu: clock@1c20000 { pio: pinctrl@1c20800 { compatible = "allwinner,sun50i-a64-pinctrl"; reg = <0x01c20800 0x400>; + interrupt-parent = <&r_intc>; interrupts = , , ; @@ -818,6 +819,7 @@ lradc: lradc@1c21800 { compatible = "allwinner,sun50i-a64-lradc", "allwinner,sun8i-a83t-r-lradc"; reg = <0x01c21800 0x400>; + interrupt-parent = <&r_intc>; interrupts = ; status = "disabled"; }; @@ -1208,6 +1210,7 @@ rtc: rtc@1f00000 { compatible = "allwinner,sun50i-a64-rtc", "allwinner,sun8i-h3-rtc"; reg = <0x01f00000 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clock-output-names = "osc32k", "osc32k-out", "iosc"; @@ -1279,6 +1282,7 @@ r_pwm: pwm@1f03800 { r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; + interrupt-parent = <&r_intc>; interrupts = ; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 15babb635cf7..4af06f49daa7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -294,6 +294,7 @@ pwm: pwm@300a000 { pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; + interrupt-parent = <&r_intc>; interrupts = , , , @@ -902,6 +903,7 @@ tcon_tv_out_tcon_top: endpoint@1 { rtc: rtc@7000000 { compatible = "allwinner,sun50i-h6-rtc"; reg = <0x07000000 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clock-output-names = "osc32k", "osc32k-out", "iosc"; @@ -937,6 +939,7 @@ r_intc: interrupt-controller@7021000 { r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h6-r-pinctrl"; reg = <0x07022000 0x400>; + interrupt-parent = <&r_intc>; interrupts = , ; clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;