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As such, add FIQ support to the kernel. Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni --- arch/arm64/include/asm/arch_gicv3.h | 2 +- arch/arm64/include/asm/assembler.h | 8 ++-- arch/arm64/include/asm/daifflags.h | 4 +- arch/arm64/include/asm/irq.h | 4 ++ arch/arm64/include/asm/irqflags.h | 6 +-- arch/arm64/kernel/entry.S | 74 ++++++++++++++++++++++++++--- arch/arm64/kernel/irq.c | 14 ++++++ arch/arm64/kernel/process.c | 2 +- 8 files changed, 97 insertions(+), 17 deletions(-) -- 2.29.2 diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 880b9054d75c..934b9be582d2 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -173,7 +173,7 @@ static inline void gic_pmr_mask_irqs(void) static inline void gic_arch_enable_irqs(void) { - asm volatile ("msr daifclr, #2" : : : "memory"); + asm volatile ("msr daifclr, #3" : : : "memory"); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index bf125c591116..6fe55713dfe0 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -40,9 +40,9 @@ msr daif, \flags .endm - /* IRQ is the lowest priority flag, unconditionally unmask the rest. */ - .macro enable_da_f - msr daifclr, #(8 | 4 | 1) + /* IRQ/FIQ is the lowest priority flag, unconditionally unmask the rest. */ + .macro enable_da + msr daifclr, #(8 | 4) .endm /* @@ -50,7 +50,7 @@ */ .macro save_and_disable_irq, flags mrs \flags, daif - msr daifset, #2 + msr daifset, #3 .endm .macro restore_irq, flags diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h index 1c26d7baa67f..44de96c7fb1a 100644 --- a/arch/arm64/include/asm/daifflags.h +++ b/arch/arm64/include/asm/daifflags.h @@ -13,8 +13,8 @@ #include #define DAIF_PROCCTX 0 -#define DAIF_PROCCTX_NOIRQ PSR_I_BIT -#define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT) +#define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT) +#define DAIF_ERRCTX (PSR_I_BIT | PSR_F_BIT | PSR_A_BIT) #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index b2b0c6405eb0..2d1537d3a245 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -13,5 +13,9 @@ static inline int nr_legacy_irqs(void) return 0; } +int set_handle_fiq(void (*handle_fiq)(struct pt_regs *)); + +extern void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init; + #endif /* !__ASSEMBLER__ */ #endif diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index ff328e5bbb75..26d7f378113e 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -35,7 +35,7 @@ static inline void arch_local_irq_enable(void) } asm volatile(ALTERNATIVE( - "msr daifclr, #2 // arch_local_irq_enable", + "msr daifclr, #3 // arch_local_irq_enable", __msr_s(SYS_ICC_PMR_EL1, "%0"), ARM64_HAS_IRQ_PRIO_MASKING) : @@ -54,7 +54,7 @@ static inline void arch_local_irq_disable(void) } asm volatile(ALTERNATIVE( - "msr daifset, #2 // arch_local_irq_disable", + "msr daifset, #3 // arch_local_irq_disable", __msr_s(SYS_ICC_PMR_EL1, "%0"), ARM64_HAS_IRQ_PRIO_MASKING) : @@ -85,7 +85,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) int res; asm volatile(ALTERNATIVE( - "and %w0, %w1, #" __stringify(PSR_I_BIT), + "and %w0, %w1, #" __stringify(PSR_I_BIT | PSR_F_BIT), "eor %w0, %w1, #" __stringify(GIC_PRIO_IRQON), ARM64_HAS_IRQ_PRIO_MASKING) : "=&r" (res) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index c9bae73f2621..abcca0db0736 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -499,6 +499,14 @@ tsk .req x28 // current thread_info irq_stack_exit .endm + .macro fiq_handler + ldr_l x1, handle_arch_fiq + mov x0, sp + irq_stack_entry + blr x1 + irq_stack_exit + .endm + #ifdef CONFIG_ARM64_PSEUDO_NMI /* * Set res to 0 if irqs were unmasked in interrupted context. @@ -547,18 +555,18 @@ SYM_CODE_START(vectors) kernel_ventry 1, sync // Synchronous EL1h kernel_ventry 1, irq // IRQ EL1h - kernel_ventry 1, fiq_invalid // FIQ EL1h + kernel_ventry 1, fiq // FIQ EL1h kernel_ventry 1, error // Error EL1h kernel_ventry 0, sync // Synchronous 64-bit EL0 kernel_ventry 0, irq // IRQ 64-bit EL0 - kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 + kernel_ventry 0, fiq // FIQ 64-bit EL0 kernel_ventry 0, error // Error 64-bit EL0 #ifdef CONFIG_COMPAT kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 - kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 + kernel_ventry 0, fiq_compat, 32 // FIQ 32-bit EL0 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 #else kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 @@ -661,7 +669,7 @@ SYM_CODE_END(el1_sync) SYM_CODE_START_LOCAL_NOALIGN(el1_irq) kernel_entry 1 gic_prio_irq_setup pmr=x20, tmp=x1 - enable_da_f + enable_da mov x0, sp bl enter_el1_irq_or_nmi @@ -689,6 +697,38 @@ alternative_else_nop_endif kernel_exit 1 SYM_CODE_END(el1_irq) + .align 6 +SYM_CODE_START_LOCAL_NOALIGN(el1_fiq) + kernel_entry 1 + gic_prio_irq_setup pmr=x20, tmp=x1 + enable_da + + mov x0, sp + bl enter_el1_irq_or_nmi + + fiq_handler + +#ifdef CONFIG_PREEMPTION + ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count +alternative_if ARM64_HAS_IRQ_PRIO_MASKING + /* + * DA_F were cleared at start of handling. If anything is set in DAIF, + * we come back from an NMI, so skip preemption + */ + mrs x0, daif + orr x24, x24, x0 +alternative_else_nop_endif + cbnz x24, 1f // preempt count != 0 || NMI return path + bl arm64_preempt_schedule_irq // irq en/disable is done inside +1: +#endif + + mov x0, sp + bl exit_el1_irq_or_nmi + + kernel_exit 1 +SYM_CODE_END(el1_fiq) + /* * EL0 mode handlers. */ @@ -715,6 +755,12 @@ SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) b el0_irq_naked SYM_CODE_END(el0_irq_compat) + .align 6 +SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat) + kernel_entry 0, 32 + b el0_fiq_naked +SYM_CODE_END(el0_fiq_compat) + SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) kernel_entry 0, 32 b el0_error_naked @@ -727,7 +773,7 @@ SYM_CODE_START_LOCAL_NOALIGN(el0_irq) el0_irq_naked: gic_prio_irq_setup pmr=x20, tmp=x0 user_exit_irqoff - enable_da_f + enable_da tbz x22, #55, 1f bl do_el0_irq_bp_hardening @@ -737,6 +783,22 @@ el0_irq_naked: b ret_to_user SYM_CODE_END(el0_irq) + .align 6 +SYM_CODE_START_LOCAL_NOALIGN(el0_fiq) + kernel_entry 0 +el0_fiq_naked: + gic_prio_irq_setup pmr=x20, tmp=x0 + user_exit_irqoff + enable_da + + tbz x22, #55, 1f + bl do_el0_irq_bp_hardening +1: + fiq_handler + + b ret_to_user +SYM_CODE_END(el0_fiq) + SYM_CODE_START_LOCAL(el1_error) kernel_entry 1 mrs x1, esr_el1 @@ -757,7 +819,7 @@ el0_error_naked: mov x0, sp mov x1, x25 bl do_serror - enable_da_f + enable_da b ret_to_user SYM_CODE_END(el0_error) diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c index dfb1feab867d..4d7a9fb41d93 100644 --- a/arch/arm64/kernel/irq.c +++ b/arch/arm64/kernel/irq.c @@ -88,3 +88,17 @@ void __init init_IRQ(void) local_daif_restore(DAIF_PROCCTX_NOIRQ); } } + +/* + * Analogous to the generic handle_arch_irq / set_handle_irq + */ +void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init; + +int __init set_handle_fiq(void (*handle_fiq)(struct pt_regs *)) +{ + if (handle_arch_fiq) + return -EBUSY; + + handle_arch_fiq = handle_fiq; + return 0; +} diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 6616486a58fe..34ec400288d0 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -84,7 +84,7 @@ static void noinstr __cpu_do_idle_irqprio(void) unsigned long daif_bits; daif_bits = read_sysreg(daif); - write_sysreg(daif_bits | PSR_I_BIT, daif); + write_sysreg(daif_bits | PSR_I_BIT | PSR_F_BIT, daif); /* * Unmask PMR before going idle to make sure interrupts can From patchwork Wed Jan 20 13:27:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohamed Mediouni X-Patchwork-Id: 12032339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74479C433E0 for ; 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b=akLBpE10xmN+SQNDTySZETF5P6JMvSSXEEqfrLQ8sbKMcz0aSw6iNRmK/TPMs7+Cr BMD1KfWBWlOcf/0uhYIDqnme+60U+SjD2fTa7zS71kXdWCtzueZ1L23LYAypvFp1YO QqdGA9NwL2upvnFeaZQDj08MTtcCjeVr7uuUexmc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([83.204.192.78]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MIwzA-1lIDwF2YO2-00KTG9; Wed, 20 Jan 2021 14:27:33 +0100 From: Mohamed Mediouni To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 2/7] arm64: kernel: Add a WFI hook. Date: Wed, 20 Jan 2021 14:27:12 +0100 Message-Id: <20210120132717.395873-3-mohamed.mediouni@caramail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120132717.395873-1-mohamed.mediouni@caramail.com> References: <20210120132717.395873-1-mohamed.mediouni@caramail.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:VFpxDb1Pw2xeOZRr7mOJYZKYKFdz9uqWWjqerljkCcZ9LCRlKdN Q5uAw7cv2cLU3r24bGFbFQNqNzTMXIg6nBOdfRDMUyr5RIq0GQVT/xFBaYTO65TMYcvHSBb i839SCKlA6H2az5y/0KNi3nRucCFPMzEe544c0albOKkKGS7nWwImD/LPbJCHj0poBrDyb7 c9bubmzDe876bkTyY9v8Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:lptcHETjPWI=:H8zJtTpVUX88hOd4CmTUwM eXCTnZIzj8MEsPy1fz1MiLFlq1mocVd4sID0CDXoIOzaMK+xDCXO8rBzm5+7tipzqd9TKfXTA ZzDXAuX5AS7v64qWbVMzM2nQM2p2jM0wmLX60hWqNPakY0joMKwRf7hgGjnogY6xcI3293CtU ZrVsQzJv7RoIKRDO2ZIDz+oe7SCj9BDumcmQN+q4mhday4hDjh2MLuU9kTw8uP3oba6vzAYIa vvvmPcA0QzM+9DyPxPSi2QIfHY3xuoCYywME/Xu8Hatubcc+c30T9tYEIYk72HaUIFOHXodPl Bt7qK7FSyg+SedxovJ0bs+wqpQA0s2ecXQFkBTsAptEg0qAgR4UfAniyp7+8oqbjGJr/fxd/0 Q89A7v0CRIAazZqW9KD449VmnGYc8OOwU7TWu4lJOaP+fhXVRPKjXkufjRAeMw8mRx2nirp6c 05X0VcYEmHmP27sfLtgWVWcBprFOxocENJeVgVwazranfdzyu1Vk2O1uMVHIV8ajOK0MD0VtC IMUT+4xinygpxTCV2ACoOQhAm1JWbB600HlZx7CYq76MQnkMwdizmWGmDyiBvJv2MSZkRj4tq 6gFJmURf7sbcsyJiA3SpFg2/9S2nyE1qJFSR6/XbhuD9WfCTlcOpPP1W0pbbKLAgJ8EP1Y4rZ 17s20BB1IO4/Vw0fWx2dYwzGoG3F8GgBBBSfwRyP45AunuDWw1MpcI/T3Pu8s0nfb3Pv7G+Ob d4XFRv5u01iNK/2wXtRPpfQAKBtpp2twxgYR7LCwzA8XAZDlxTGqrhsaPqlXVmbwcu0l6KtQZ tR0MoJG+haX4ui5HGVRnjnPPbAiitF5/TKzDPu/L9QGCL8i0aapSC/knWSI5xA0OAA5HBAGUL 2TbISFds5qsTmJ5rTsok6nxcJ4A3UkL9dXNJcvlng= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_082750_461174_90C8C009 X-CRM114-Status: GOOD ( 15.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, Marc Zyngier , Mohamed Mediouni , Will Deacon , Stan Skowronek Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Stan Skowronek WFI drops register state on Apple Silicon for SMP systems. This hook will be used for a hardware workaround in the Apple CPU start driver. Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni --- arch/arm64/include/asm/cpu_ops.h | 2 ++ arch/arm64/kernel/cpu_ops.c | 6 ++++++ arch/arm64/kernel/process.c | 11 +++++++++-- 3 files changed, 17 insertions(+), 2 deletions(-) -- 2.29.2 diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h index e95c4df83911..4be0fc5bcaf9 100644 --- a/arch/arm64/include/asm/cpu_ops.h +++ b/arch/arm64/include/asm/cpu_ops.h @@ -23,6 +23,7 @@ * @cpu_boot: Boots a cpu into the kernel. * @cpu_postboot: Optionally, perform any post-boot cleanup or necessary * synchronisation. Called from the cpu being booted. + * @cpu_wfi: Optionally, replace calls to WFI in default idle with this. * @cpu_can_disable: Determines whether a CPU can be disabled based on * mechanism-specific information. * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific @@ -43,6 +44,7 @@ struct cpu_operations { int (*cpu_prepare)(unsigned int); int (*cpu_boot)(unsigned int); void (*cpu_postboot)(void); + void (*cpu_wfi)(void); #ifdef CONFIG_HOTPLUG_CPU bool (*cpu_can_disable)(unsigned int cpu); int (*cpu_disable)(unsigned int cpu); diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c index e133011f64b5..6979fc4490b2 100644 --- a/arch/arm64/kernel/cpu_ops.c +++ b/arch/arm64/kernel/cpu_ops.c @@ -19,12 +19,18 @@ extern const struct cpu_operations smp_spin_table_ops; extern const struct cpu_operations acpi_parking_protocol_ops; #endif extern const struct cpu_operations cpu_psci_ops; +#ifdef CONFIG_ARCH_APPLE +extern const struct cpu_operations cpu_apple_start_ops; +#endif static const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init; static const struct cpu_operations *const dt_supported_cpu_ops[] __initconst = { &smp_spin_table_ops, &cpu_psci_ops, +#ifdef CONFIG_ARCH_APPLE + &cpu_apple_start_ops, +#endif NULL, }; diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 34ec400288d0..611c639e20be 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -57,6 +57,7 @@ #include #include #include +#include #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK) #include @@ -74,8 +75,14 @@ void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); static void noinstr __cpu_do_idle(void) { - dsb(sy); - wfi(); + const struct cpu_operations *ops = get_cpu_ops(task_cpu(current)); + + if (ops->cpu_wfi) { + ops->cpu_wfi(); + } else { + dsb(sy); + wfi(); + } } static void noinstr __cpu_do_idle_irqprio(void) From patchwork Wed Jan 20 13:27:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohamed Mediouni X-Patchwork-Id: 12032329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CE50C433E0 for ; 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b=OW+6blaI6lZsvDiIrRkXFfuhKpbCF1mPXlZZnWfPVeKtDA8PgS6JoUgi3XNRp25Xo KaB+oo1ozexSmGo8SRpjlv+tmoNDf3CUmbkB4MlSuwUDL4Vrwubj2jwUDztd0WHAwv fciCabDX/718a98oXRZ48K6t3sZRpRr+7KjnE3BM= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([83.204.192.78]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MZTmO-1lYi5A0kBK-00WWzx; Wed, 20 Jan 2021 14:27:34 +0100 From: Mohamed Mediouni To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors Date: Wed, 20 Jan 2021 14:27:13 +0100 Message-Id: <20210120132717.395873-4-mohamed.mediouni@caramail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120132717.395873-1-mohamed.mediouni@caramail.com> References: <20210120132717.395873-1-mohamed.mediouni@caramail.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:tgRN9ZZSe4I0G1AnOStUrLzlx9ePZFoTVM7kvlMbPu/L2SyFwd2 wVJoN+bOlH6NLGXNiegaSDh5m7jd1xuzbp3eGpZ2y9bfJVLBs/1kd6gq64kAGriYnH1zxgg 3n0lRknK/OWJeYjRcO2YOtv55SssMWh7o26n74OqFUiYwMSD4hjhSwZsx64N8PkVaMnJDge UpFJEdaabuc5buav1mjuA== X-UI-Out-Filterresults: notjunk:1;V03:K0:cvzZywDWErY=:y87grJtHm0+LLMwsB+ZsLA FQaQM0GBgeYTo2zySC2+7rX+N7JR8Z2G4x2vnkC2DGABO5aN44monBSOY5Tz3f0CYbv+KSAHC wgpKeKWhUUlhwce/w3dkuyQ+h2DMTugsn5tg9O8t/wwaoZDQt4S1YL19LON3R8FaGaEebcFA1 T8kD4LQjBvYh45z7HxMh3/N6BQLigNimFrhF/61U6swlP163sHAowwsN+fTOZOLr2zkefb8RZ ZX7ljnLxnniP3RfV9jQLVj2vl4GCcDs89CvWzXAj3iNxCkpinIyio0IZbhh5G3H3VqQ3I5juJ L77usap/mtCJS+Wlss2aBsOEoki9BCxIVpHm5p+0iUfrDAGcnlZyq2UsjgOHFQ+nkCozhBhnG mZztXr1na/R7I/mWIe6tNLbwe5KLb9Cn5cdS103mn+qZsvpTnfURS9YoOAUclJhJ2LvrpBU/+ HK+JgWusLCdqTZorPVgITAjtNSdAL7MsbNLtFYMDnY9DYUsqbN8ug44AuYxqPGRpmJPjowYJ9 lhiwm5Xihcg+xqil4Jk2nmZ8deBhGGzkP6OL2VVvilGS9txan80AVlHjroi0h/4EJ/r6htm29 kWHL/Nhc875N+O59EFm1+lUOhWGaV5iDUfLJzL7iobEH7FCKhNLWZH6qUp2t7IgtfpP3fOauz aZ3XmxivUFASM8urLjVfbgIBOyUihnkFbvlkPLlu9jSYcnp1Bm7/DQe0YLJnhLY1S14SN0wdS 1lFRMqLq3il1sBq4z0aHvoPx0EAHnXspuZqBJe393uCPggl5zKCjOkyQFsW0VmV7x10hAXYm9 esdzlvE7O5P/ZJwV6EM0THsYz5q0qix4VFUfDuTXwVZmT4cFAR+yS2GXYdi0dLWip3gpjd9QX yYIsUxiArBl26aqG5p42QDt/DImVR9J5Amb1E+HOA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_082746_878224_34B1A1B1 X-CRM114-Status: GOOD ( 11.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, Marc Zyngier , Mohamed Mediouni , Will Deacon , Stan Skowronek Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware quirk. On Apple processors, writes using the nGnRE device memory type get dropped in flight, getting to nowhere. Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni --- arch/arm64/mm/proc.S | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.29.2 diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 1f7ee8c8b7b8..06436916f137 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -51,6 +51,25 @@ #define TCR_KASAN_HW_FLAGS 0 #endif +#ifdef CONFIG_ARCH_APPLE + +/* + * Apple cores appear to black-hole writes done with nGnRE. + * We settled on a work-around that uses MAIR vs changing every single user of + * nGnRE across the arm64 code. + */ + +#define MAIR_EL1_SET_APPLE \ + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) | \ + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) + +#endif + /* * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and * changed during __cpu_setup to Normal Tagged if the system supports MTE. @@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup) * Memory region attributes */ mov_q x5, MAIR_EL1_SET +#ifdef CONFIG_ARCH_APPLE + mrs x0, MIDR_EL1 + lsr w0, w0, #24 + mov_q x1, MAIR_EL1_SET_APPLE + cmp x0, #0x61 // 0x61 = Implementer: Apple + csel x5, x1, x5, eq +#endif #ifdef CONFIG_ARM64_MTE mte_tcr .req x20 From patchwork Wed Jan 20 13:27:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohamed Mediouni X-Patchwork-Id: 12032335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C004C433DB for ; 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b=BIiMCr9g0tE4RatQ9OVgxFyZjF2v4CShiQGzn5hf1/O7hHApktgTma+FsDfI8mHyE /III9aoLOim/Nlw0DAPiXUTl9lNROQvOoE59pQqnlu7GSW8BLQA5NMFnwFE31ACWvQ z25Sv0MFw6+o0S+hLRUurdFabJ76AU/2HURFaU+E= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([83.204.192.78]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1Mlf0K-1lkrg42yJe-00iiCT; Wed, 20 Jan 2021 14:27:35 +0100 From: Mohamed Mediouni To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 4/7] irqchip/apple-aic: Add support for Apple AIC Date: Wed, 20 Jan 2021 14:27:14 +0100 Message-Id: <20210120132717.395873-5-mohamed.mediouni@caramail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120132717.395873-1-mohamed.mediouni@caramail.com> References: <20210120132717.395873-1-mohamed.mediouni@caramail.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:dAt+3Oju6AyOpYCx1KbF9d6xREgN4bW/RaqtDY8KJWHcp+dlB1I ajevjfRxVfKyNuBUU9w8vBbRJKqa6zQAQvm05s/3T5b3YMiioxFh3XuOGqfVys/Fbyts17X i2h39hUteozN29mqxglUSd8fvm45OEPvYc3ihvYP0KM8oItea9wd1Rt9emhzEYVKd+ev2j8 +Z4mM3UE5CCot15Ief3Mw== X-UI-Out-Filterresults: notjunk:1;V03:K0:4FjygVFYyas=:4G9dSXtr669HxTIUSxu8QL 6GYhxk5tDxK9pGbdhFa7Qdr4Txb/FeBkHwBvWNYWmnyGGAIoYJ3wJkalmjIjjHhQVV9+piqel kOyEdLx8G9a7nYMw2VdHm6fsWTybxgg3TYdLBBaXkPOLzx8hgZ3e+1V4ZPwSqenOpbL9LdyR/ 3hfl3o88v09QbqQCyrmsSvyrp6+BGemex8HH5+lpayp+iBBz3vtZjPit+nybrEDdUr8AUOPnt AMrxwffUMeiHH7Q/wEtWonbpKqlORCucG3synf/oTUsMgFaFbFM1KPDUbkjPA7lSJtvykvbIf M7ZoRZgk2AhZlCSUmajEqXm10Ws/QiHO7gsBvUtEhReYr/e6aN9n0HiaEKpEsjT/9C/M7kAIO hl8IvsofZdJSB/EWrj8OT7X69/ibhT1HSSroZdbdPXutVjtsYCRSrHTMgBoQbKqQd4Gj6ixZk 5oJpHhRgO2ntpuXXiK8TBqzkrpDXrWbLW9vOXIePz0KbtHWwP0yToEW/EDUZlYIuQ9+sEg1OX 8PByJ2smup/plK2OWt4gq35DKbz4WPGrAJmTmAI2U0uA1cgFwacMeppD5Y95GjbB1TXuEQd+r Kk7Zx6OscT7J2GZN+6zpAiW2RUPeOFXSR3abV1A6vX2atfvOhPNboHWybG3pqjnLu3h6OAZFj nOBwxF3fMSEwZDsWMdGzvCpuNqz2r63qU/WxzYMo8vFPOHRG1ZY1mIAS2zMymQ/cH2HTN40B3 rP3atbxSv4QSbLNDcgKE0TGKRxnAtEWzB/muQQceLBRZXq+VDt5WyShJzAWGtoOSP7yh1gYgD NaSZ+WZiUwjNZh43TT34yWEIVSHE8Uz+1QDP9v9iJyy/IpXu3pWHRlYCBsbC+8FQkEDZco+dI ZDTYyDN1bwGL3m6/TH4G6awopB4VjJmjZk6bKlhSY= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_082746_878892_BC2BCC7E X-CRM114-Status: GOOD ( 21.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, Marc Zyngier , Mohamed Mediouni , Will Deacon , Stan Skowronek Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Stan Skowronek Apple SoCs use the Apple AIC interrupt controller. The Arm architectural timers is wired over FIQ on that hardware. Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni Acked-by: Stan Skowronek --- .../interrupt-controller/apple,aic.yaml | 49 ++++ MAINTAINERS | 6 + drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-apple-aic.c | 211 ++++++++++++++++++ 5 files changed, 273 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml create mode 100644 drivers/irqchip/irq-apple-aic.c -- 2.29.2 diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml new file mode 100644 index 000000000000..e615eaaca869 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Advanced Interrupt Controller (AIC) + +description: + Interrupt controller present on Apple processors. AIC + is used by Apple on their AArch64 SoCs since the Apple A7. + +maintainers: + - Stan Skowronek + +properties: + compatible: + items: + - const: apple,aic + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 3 + + interrupt-controller: true + + fast-ipi: + description: + Fast IPI support. + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + - reg + +additionalProperties: false + +examples: + - | + aic: interrupt-controller@23b100000 { + compatible = "apple,aic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2 0x3b100000 0x0 0x8000>; + fast-ipi; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 00836f6452f0..e609ede99dd4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1218,6 +1218,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor F: Documentation/admin-guide/LSM/apparmor.rst F: security/apparmor/ +APPLE ADVANCED INTERRUPT CONTROLLER DRIVER +M: Stan Skowronek +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: drivers/irqchip/irq-apple-aic.c + APPLE BCM5974 MULTITOUCH DRIVER M: Henrik Rydberg L: linux-input@vger.kernel.org diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 94920a51c628..3aa9e711324b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -56,6 +56,12 @@ config ARM_GIC_V3_ITS_FSL_MC depends on FSL_MC_BUS default ARM_GIC_V3_ITS +config APPLE_AIC + bool + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_IRQ_EFFECTIVE_AFF_MASK + config ARM_NVIC bool select IRQ_DOMAIN_HIERARCHY diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 0ac93bfaec61..2f5a9a0cf40f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o +obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c new file mode 100644 index 000000000000..c601bc4b501a --- /dev/null +++ b/drivers/irqchip/irq-apple-aic.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Apple chip interrupt controller + * + * Copyright (C) 2020 Corellium LLC + * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define REG_ID_REVISION 0x0000 +#define REG_ID_CONFIG 0x0004 +#define REG_GLOBAL_CFG 0x0010 +#define REG_TIME_LO 0x0020 +#define REG_TIME_HI 0x0028 +#define REG_ID_CPUID 0x2000 +#define REG_IRQ_ACK 0x2004 +#define REG_IRQ_ACK_TYPE_MASK (15 << 16) +#define REG_IRQ_ACK_TYPE_NONE (0 << 16) +#define REG_IRQ_ACK_TYPE_IRQ (1 << 16) +#define REG_IRQ_ACK_TYPE_IPI (4 << 16) +#define REG_IRQ_ACK_IPI_OTHER 0x40001 +#define REG_IRQ_ACK_IPI_SELF 0x40002 +#define REG_IRQ_ACK_NUM_MASK (4095) +#define REG_IPI_SET 0x2008 +#define REG_IPI_FLAG_SELF (1 << 31) +#define REG_IPI_FLAG_OTHER (1 << 0) +#define REG_IPI_CLEAR 0x200C +#define REG_IPI_DISABLE 0x2024 +#define REG_IPI_ENABLE 0x2028 +#define REG_IPI_DEFER_SET 0x202C +#define REG_IPI_DEFER_CLEAR 0x2030 +#define REG_TSTAMP_CTRL 0x2040 +#define REG_TSTAMP_LO 0x2048 +#define REG_TSTAMP_HI 0x204C +#define REG_IRQ_AFFINITY(i) (0x3000 + ((i) << 2)) +#define REG_IRQ_DISABLE(i) (0x4100 + (((i) >> 5) << 2)) +#define REG_IRQ_xABLE_MASK(i) (1 << ((i)&31)) +#define REG_IRQ_ENABLE(i) (0x4180 + (((i) >> 5) << 2)) +#define REG_CPU_REGION 0x5000 +#define REG_CPU_LOCAL 0x2000 +#define REG_CPU_SHIFT 7 +#define REG_PERCPU(r, c) \ + ((r) + REG_CPU_REGION - REG_CPU_LOCAL + ((c) << REG_CPU_SHIFT)) + +static struct aic_chip_data { + void __iomem *base; + struct irq_domain *domain; + unsigned int num_irqs; +} aic; + +static void apple_aic_irq_mask(struct irq_data *d) +{ + writel(REG_IRQ_xABLE_MASK(d->hwirq), + aic.base + REG_IRQ_DISABLE(d->hwirq)); +} + +static void apple_aic_irq_unmask(struct irq_data *d) +{ + writel(REG_IRQ_xABLE_MASK(d->hwirq), + aic.base + REG_IRQ_ENABLE(d->hwirq)); +} + +static struct irq_chip apple_aic_irq_chip = { + .name = "apple_aic", + .irq_mask = apple_aic_irq_mask, + .irq_mask_ack = apple_aic_irq_mask, + .irq_unmask = apple_aic_irq_unmask, +}; + +static void apple_aic_fiq_mask(struct irq_data *d) +{ +} + +static void apple_aic_fiq_unmask(struct irq_data *d) +{ +} + +static struct irq_chip apple_aic_irq_chip_fiq = { + .name = "apple_aic_fiq", + .irq_mask = apple_aic_fiq_mask, + .irq_unmask = apple_aic_fiq_unmask, +}; + +static int apple_aic_irq_domain_xlate(struct irq_domain *d, + struct device_node *ctrlr, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (intspec[0]) { /* FIQ */ + if (intspec[1] >= 2) + return -EINVAL; + if (out_hwirq) + *out_hwirq = aic.num_irqs + intspec[1]; + } else { + if (intspec[1] >= aic.num_irqs) + return -EINVAL; + if (out_hwirq) + *out_hwirq = intspec[1]; + } + + if (out_type) + *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; + return 0; +} + +static int apple_aic_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + if (hw >= aic.num_irqs) { + irq_set_percpu_devid(virq); + irq_domain_set_info(d, virq, hw, &apple_aic_irq_chip_fiq, + d->host_data, handle_percpu_devid_irq, NULL, + NULL); + irq_set_status_flags(virq, IRQ_NOAUTOEN); + } else { + irq_domain_set_info(d, virq, hw, &apple_aic_irq_chip, + d->host_data, handle_level_irq, NULL, NULL); + irq_set_probe(virq); + irqd_set_single_target( + irq_desc_get_irq_data(irq_to_desc(virq))); + } + return 0; +} + +static const struct irq_domain_ops apple_aic_irq_domain_ops = { + .xlate = apple_aic_irq_domain_xlate, + .map = apple_aic_irq_domain_map, +}; + +static void __exception_irq_entry apple_aic_handle_irq(struct pt_regs *regs) +{ + uint32_t ack; + unsigned done = 0; + + while (1) { + ack = readl(aic.base + REG_IRQ_ACK); + switch (ack & REG_IRQ_ACK_TYPE_MASK) { + case REG_IRQ_ACK_TYPE_NONE: + done = 1; + break; + case REG_IRQ_ACK_TYPE_IRQ: + handle_domain_irq(aic.domain, + ack & REG_IRQ_ACK_NUM_MASK, regs); + break; + } + if (done) + break; + } +} + +static void __exception_irq_entry apple_aic_handle_fiq(struct pt_regs *regs) +{ + handle_domain_irq(aic.domain, aic.num_irqs, regs); +} + +void apple_aic_cpu_prepare(unsigned int cpu) +{ + unsigned i; + + for (i = 0; i < aic.num_irqs; i++) + writel(readl(aic.base + REG_IRQ_AFFINITY(i)) | (1u << cpu), + aic.base + REG_IRQ_AFFINITY(i)); +} + +static int __init apple_aic_init(struct device_node *node, + struct device_node *interrupt_parent) +{ + unsigned i; + + if (!node) + return -ENODEV; + + aic.base = of_iomap(node, 0); + if (WARN(!aic.base, "unable to map aic registers\n")) + return -EINVAL; + + aic.num_irqs = readl(aic.base + REG_ID_CONFIG) & 0xFFFF; + pr_info("Apple AIC: %d IRQs + 1 FIQ + 1 dummy\n", aic.num_irqs); + + for (i = 0; i < aic.num_irqs; i++) + writel(1, aic.base + REG_IRQ_AFFINITY(i)); + for (i = 0; i < aic.num_irqs; i += 32) + writel(-1u, aic.base + REG_IRQ_DISABLE(i)); + writel((readl(aic.base + REG_GLOBAL_CFG) & ~0xF00000) | 0x700000, + aic.base + REG_GLOBAL_CFG); + + set_handle_irq(apple_aic_handle_irq); + set_handle_fiq(apple_aic_handle_fiq); + + apple_aic_cpu_prepare(0); + + aic.domain = irq_domain_add_linear(node, aic.num_irqs + 2, + &apple_aic_irq_domain_ops, + &apple_aic_irq_chip); + irq_set_default_host(aic.domain); + return 0; +} + +IRQCHIP_DECLARE(apple_aic_irq_chip, "apple,aic", apple_aic_init); From patchwork Wed Jan 20 13:27:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohamed Mediouni X-Patchwork-Id: 12032333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C531C433E0 for ; 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b=HSgjImhnrR1ec3+zvvAOKfNPrVgwaIBl0pWks4bvC/ucqWQrUS8CeBwePu8tgzOAz YkS4eX5GqZqJim7t+/jEjhsgXrHtGRx+gcjirZVHE12N18u+aYZbs9l8iVtH67VMX6 f/9hCN6rPHSvbdLAVh/0AdkJxPJzdlRPTV8JhPmI= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([83.204.192.78]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MIdiZ-1lGlj02bB7-00EaVW; Wed, 20 Jan 2021 14:27:35 +0100 From: Mohamed Mediouni To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 5/7] arm64/Kconfig: Add Apple Silicon SoC platform Date: Wed, 20 Jan 2021 14:27:15 +0100 Message-Id: <20210120132717.395873-6-mohamed.mediouni@caramail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120132717.395873-1-mohamed.mediouni@caramail.com> References: <20210120132717.395873-1-mohamed.mediouni@caramail.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:ig0OHEXnh4oqRZsZcOlPiTax0KhIOrYFEjmGGv5RQOOns/VYDxC CHvwEfHmdO9qKB/qOo/v+oI0Y3vT8puVXPsMd/TqcYYvPNWn7Qn1w73xdosDXnfGgbSEUqc igW9KWId7DcQP/9Birx5c279TcW2T9P53k44G9s0uDnCI+zvIa6bmT+x+1W+Jn0CqMkhLS3 XcxMY2YwVSTIHWfz/SrUg== X-UI-Out-Filterresults: notjunk:1;V03:K0:Wf4+WytWYtE=:RyEY2KxTqw2oDLvRHDWi6c YL/y4oAieJ4+hSL63FwvaCwjXhnx5xD8t44rvaa+TqDvNFNC473O6vFjgnjSOCYZL3831xUNx iklrhw6aeGbmZ6jxStA0+J6zdoY0ZcWreCuDnshK1Tvo0po2wzPNwlpQk9d63VaFSroH+rJhe Ev1zPOaO/OvArSGXUDIxFqOAgoys3ySbNbN07jUPek8XhthADGJrsoaliYYLvs8Z1x8kg13vM zOSdU2LeHjmGwuSVllwLx/aEumMkbxIW7egoslOZsdr4Mbo+CZjex7a1xEQ8PYu4mzUMeFoHg kTEJ1vL6GQxWtEhHJO+On8kTWo9Fw2m1OONTt2fmylTNen7Mdy1J2UEyGM5CW9GHqHMPoZEr0 BqyGhzKWPaTqHQZMhdROKPGQUiEpgBoAm7aw1GX8PhI2NoKYny+BQ0/cOX2lgGQeHwUKn5p/E B9aNX9r9lQdR+4b7/Jd00D2NYOCAoF8Q2P7zNcrkpNK9T3tQA/3fVPxxG6RijLNdnqlJltjKK RyS/G8sWxswanOs7WnrOEym2APlkYUqI/eb3Yqa1Ghd21fA0FCTlOYbTrq2Cj4rkucEWy5igb UG9aguSVUpDGDyD+3ljwvJ5tNpT7/uGos+hi5Z/zMn8dK7sTZb3dLWSb6C3jSe3zQVrzwlP+k GxH+nmJKf31/s6WDrWC/jh26MlHfN0/rxps2EDDIe62CtPjgGhsd0Lcd4Dxt8hCvkFaAbH1HM gs4+lY0tCkG8ycNzywuYeDiZs/5KiRfL1SqqKNKURfALuf8cPkC7BqTz7BtGWXhIxHnK8NZpS +rZKB0eD0ZM6WMxw7T4rYKs9TGMMMT8zFdxYAdx4YC66NSFN0WSZWVleh04MtgZnmN8oc/z79 1ZX5MLbrOgXEKwLS+X4Kzb5LRUY5wIyA1tevKhFr0= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_082749_072629_40015395 X-CRM114-Status: GOOD ( 10.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, Marc Zyngier , Mohamed Mediouni , Will Deacon , Stan Skowronek Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Stan Skowronek Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni --- arch/arm64/Kconfig.platforms | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.29.2 diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6eecdef538bd..cc52519d4f67 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -328,4 +328,11 @@ config ARCH_ZYNQMP help This enables support for Xilinx ZynqMP Family +config ARCH_APPLE + bool "Apple Silicon SoC Family" + select APPLE_AIC + help + This enables support for Apple processors present + on Mac computers. + endmenu From patchwork Wed Jan 20 13:27:16 2021 Content-Type: text/plain; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2DY6-0005Bv-CF; Wed, 20 Jan 2021 13:29:26 +0000 Received: from mout.gmx.net ([212.227.15.18]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2DWW-0004fU-NS for linux-arm-kernel@lists.infradead.org; Wed, 20 Jan 2021 13:27:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1611149256; bh=sS4ZFSv3zmqbPz2KXwVaLWTiVk0irVa/4iHby0s9NZM=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=P0Lc4p7x2k8OBs1gihxpv3hGuxDqXekOzn5JSH8v9ojrSS1Hz6UFvCl3GRwtjE9Pj vzbNmW3ISlJDrIV84TWgm/O+GHcshsr48iEsTrEECuEKa3caG4gbamyWw1Dvwh8W31 pr5TdWB4KsyqJo2dd2Y9d6w3cTVuoId90E/n+xd0= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([83.204.192.78]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MeCtZ-1ldT9L10y7-00bKLo; Wed, 20 Jan 2021 14:27:36 +0100 From: Mohamed Mediouni To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 6/7] arm64: kernel: Apple CPU start driver Date: Wed, 20 Jan 2021 14:27:16 +0100 Message-Id: <20210120132717.395873-7-mohamed.mediouni@caramail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120132717.395873-1-mohamed.mediouni@caramail.com> References: <20210120132717.395873-1-mohamed.mediouni@caramail.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:xUPi8b7530TH/g+V/7aWoHbeFH+rk/x2LFHGA/9Sl1KJwIJfV5C jfGehtCY8csqFOO1zmmup+141aV1J1ZfmujSe95UakvCUnWpUyk9X7zL3CSMlu8v3+5kWus +lso3mXkauwD1DipAU2Bn+b8m2Rs9/8Q3KzsaVKF/ngHPPgiZSWOaacZeWJL5xTDQFDxtvD LWOuwRkHh4EF1R7tTwKCA== X-UI-Out-Filterresults: notjunk:1;V03:K0:StyHDgkrnfA=:UrrLMK6n+pXPxaPuNl+gwY rmwePNL3zKSXviM+fZkqFJquecXruB4brz/eYGVbJQQr63NtrOyk9dxX5XIaNG91uBebyMAbq NjkTcIiar38VywkmL8+M+by4n4uHZDMACB6/DMWB6pdYgQJdr/Iw9jhpLGaoCyl1/QCeUCWKa 3bd65iZtImlSIrrOcH/BoAGzczJgtcpa1eKNlNRpPZay53THTSnl4okIofZFRehOCw1fOga96 zVX8eJSVGzKgAy3gv2jXO81Y125998bLHIV+2hH/ppcncTMeYg6BFGch0v9/2tQOolCd+/0vn p7XkCeCY4sOZrP+bMpHEOGsUrrbgv9PPbUfk/pPMlzdcVoo/Nku9B6A1zWL7q6aupWnVujDQb /KDidwemmFCyjVit1FVhVa0k9Rhd/+0W2zJyaN0XJW9CxQc38EQmqrBGLPtCWFKWPGb+bcywO 5X9pqPVJzZxmEZn6+D5rRBGsXS47qgIe4mmDpwDELj8wg2R9WZnhlQQ3W97rt/R5OD2P71hdP zMYws81fLXAscOLz5U7fP2vj2ds8vUufZbtKIGJ0BPRqSCrDOqjnC4vreXHJAnH4GWlF177WU va6gYIWUTUB5bfgkd2qpOJHVf1D5Rqj9RqcSMhv4OgQdpgYm3eQUHnsodvW/XxunPwNAtxyRQ JF8tEXS6W2MalJRCEyhJzeOFEheZfeJz7fzLVOrWRITua6RwdgxNeblbFdvxKcY9nVmPXVceT C74Lk5dfHA0fMPqI7Wcbl9yGtmzAKIGSaQI334VHeHvKhHANNYibHwzRnok4TgsfLda/ew8Rx Q4OAzahAM57RfyGfXuHTvZzW9YuoozokbkovOowyC3NVw4MRF/5NiwBh7lv/Eu/IN2DntCBeI ioJ5NyoFMASa9W0SDmnH3Ao47Avbnjx7Ai1JLQOUM= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_082749_013272_44F710F2 X-CRM114-Status: GOOD ( 20.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, Marc Zyngier , Mohamed Mediouni , Will Deacon , Stan Skowronek Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Stan Skowronek This driver is needed to spawn CPUs for SMP on Apple Silicon platforms. Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni --- .../devicetree/bindings/arm/cpus.yaml | 1 + arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/apple_cpustart.c | 153 ++++++++++++++++++ 3 files changed, 155 insertions(+) create mode 100644 arch/arm64/kernel/apple_cpustart.c -- 2.29.2 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 14cd727d3c4b..a6ff8cb3db1e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -176,6 +176,7 @@ properties: oneOf: # On ARM v8 64-bit this property is required - enum: + - apple - psci - spin-table # On ARM 32-bit systems this property is optional diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 86364ab6f13f..497f43ca7f0f 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_ARM64_RELOC_TEST) += arm64-reloc-test.o arm64-reloc-test-y := reloc_test_core.o reloc_test_syms.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_CRASH_CORE) += crash_core.o +obj-$(CONFIG_ARCH_APPLE) += apple_cpustart.o obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o obj-$(CONFIG_ARM64_MTE) += mte.o diff --git a/arch/arm64/kernel/apple_cpustart.c b/arch/arm64/kernel/apple_cpustart.c new file mode 100644 index 000000000000..41d049eaaec7 --- /dev/null +++ b/arch/arm64/kernel/apple_cpustart.c @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) */ +/* + * Copyright (C) 2020 Corellium LLC + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define MAGIC_UNLOCK 0xc5acce55 + +struct cpu_apple_start_info { + void __iomem *pmgr_start; + u64 pmgr_start_size; + void __iomem *cputrc_rvbar; + void __iomem *dbg_unlock; +}; + +extern void apple_aic_cpu_prepare(unsigned int cpu); + +static int cpu_apple_start0_unlocked = 0; +static DEFINE_PER_CPU(struct cpu_apple_start_info, cpu_apple_start_info); + +static int __init cpu_apple_start_init(unsigned int cpu) +{ + return 0; +} + +static int cpu_apple_start_prepare(unsigned int cpu) +{ + struct device_node *node; + struct cpu_apple_start_info *info; + + info = per_cpu_ptr(&cpu_apple_start_info, cpu); + + if (info->pmgr_start && info->cputrc_rvbar && info->dbg_unlock) + return 0; + + node = of_find_compatible_node(NULL, NULL, "apple,startcpu"); + if (!node) { + pr_err("%s: missing startcpu node in device tree.\n", __func__); + return -EINVAL; + } + + if (!info->pmgr_start) { + info->pmgr_start = of_iomap(node, cpu * 3); + if (!info->pmgr_start) { + pr_err("%s: failed to map start register for CPU %d.\n", + __func__, cpu); + return -EINVAL; + } + if (!of_get_address(node, cpu * 3, &info->pmgr_start_size, + NULL)) + info->pmgr_start_size = 8; + } + + if (!info->cputrc_rvbar) { + info->cputrc_rvbar = of_iomap(node, cpu * 3 + 1); + if (!info->cputrc_rvbar) { + pr_err("%s: failed to map reset address register for CPU %d.\n", + __func__, cpu); + return -EINVAL; + } + } + + if (!info->dbg_unlock) { + info->dbg_unlock = of_iomap(node, cpu * 3 + 2); + if (!info->dbg_unlock) { + pr_err("%s: failed to map unlock register for CPU %d.\n", + __func__, cpu); + return -EINVAL; + } + } + + if (cpu) + apple_aic_cpu_prepare(cpu); + + return 0; +} + +static int cpu_apple_start_boot(unsigned int cpu) +{ + struct cpu_apple_start_info *info; + unsigned long addr; + + if (!cpu_apple_start0_unlocked) { + if (!cpu_apple_start_prepare(0)) { + info = per_cpu_ptr(&cpu_apple_start_info, 0); + writel(MAGIC_UNLOCK, info->dbg_unlock); + cpu_apple_start0_unlocked = 1; + } else + pr_err("%s: failed to unlock boot CPU\n", __func__); + } + + info = per_cpu_ptr(&cpu_apple_start_info, cpu); + + if (!info->pmgr_start || !info->cputrc_rvbar || !info->dbg_unlock) + return -EINVAL; + + writeq(__pa_symbol(secondary_entry) | 1, info->cputrc_rvbar); + readq(info->cputrc_rvbar); + writeq(__pa_symbol(secondary_entry) | 1, info->cputrc_rvbar); + addr = readq(info->cputrc_rvbar) & 0xFFFFFFFFFul; + dsb(sy); + + if (addr != (__pa_symbol(secondary_entry) | 1)) + pr_err("%s: CPU%d reset address: 0x%lx, failed to set to 0x%lx.\n", + __func__, cpu, addr, + (unsigned long)(__pa_symbol(secondary_entry) | 1)); + + writel(MAGIC_UNLOCK, info->dbg_unlock); + + writel(1 << cpu, info->pmgr_start); + if (info->pmgr_start_size >= 12) { + if (cpu < 4) { + writel(1 << cpu, info->pmgr_start + 4); + writel(0, info->pmgr_start + 8); + } else { + writel(0, info->pmgr_start + 4); + writel(1 << (cpu - 4), info->pmgr_start + 8); + } + } else + writel(1 << cpu, info->pmgr_start + 4); + + dsb(sy); + sev(); + + return 0; +} + +static void cpu_apple_wfi(void) +{ + /* can't do a proper WFI, because the CPU tends to lose state; will need + a proper wrapper sequence */ + dsb(sy); + wfe(); +} + +const struct cpu_operations cpu_apple_start_ops = { + .name = "apple", + .cpu_init = cpu_apple_start_init, + .cpu_prepare = cpu_apple_start_prepare, + .cpu_boot = cpu_apple_start_boot, + .cpu_wfi = cpu_apple_wfi, +}; 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Date: Wed, 20 Jan 2021 14:27:17 +0100 Message-Id: <20210120132717.395873-8-mohamed.mediouni@caramail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120132717.395873-1-mohamed.mediouni@caramail.com> References: <20210120132717.395873-1-mohamed.mediouni@caramail.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:UzbF93QD7ewtU45SWccubUGzjxleBAEd8cENkEmwy10LMjhlCnd DQGo+V/owwH1jTprv0HzwwC3JeJOHcSnQBIxmfgUQ39kzXLLPeruGif+m1AEZfvdNb2zEIh nxuipyANKmNwsP4C+wyEBfjE+aJbBpaULJXKnuNjRJLcb2Y7feUNZiojJboECOxdIMtMDqD g4Cp71tGcP6AZdOnkKZyQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:GiAGZBgh9e8=:ApCMlQctfbLVb/ERxyRHEW pTnRSo/156O+OQdCC5H2l6dRseBIppf4vBBHFrbSUKkr7CC6VCW4tjhoWKoDKD3kfoqQsJ8iV WvTcxv7R/x7RXFTMqtp3dgQ75lC1XLXGdC0ryLFww9u1AwEJjpFPL0PANlPVkynqlzeMIBzJ1 paOIcMU4c54fOq12uMm7k/CKxTGtYz3Lq+58hFyOgQd4dKZzFgJQOlsZ+V626DG+wpp0VTpIh b3gW0xxqAD6stxlOPj6sbTrpmLX6Fl7lm7Z2eTvGQB+0fDemuyRai58Kn1i42fHfrTOsWrA2W TzHeaZ/medH9kpubdFUK8UsqU8d84FYj9FvMIAkmneGcMVqA+9l8V4I2qe32Db0bQRgk75z+5 Q3oiUlaTdjkYXUWNiJzLqtMRHMJYjDwSE8bSppolE7XSjUm6UUsR41FQi7gvOrSuI96/zN1J8 MM/ZFoBTv0Rmeh6aW6iqda9YCPoes3IjTM+Q8E5OgmpVYR5Ih8Tddb1mOJ2Vcnp8/KD7x3o6q RcYa48ddJMuGbtt7Fu8WC5uAHq5suBKilza/h4AB08jdRm28ERY9LniFRz7ZSFnaT3SeHv6th ZtCx/d7huArqF0NxsosjM5bDu0VPr38nmLivYRmquZRkQrGSKH4hMJUbyu4kPiS8o69DpBUEq kf2+8nNkzgBGGvOXh9eX2KDeMgnx9xJ+SragVDQr5TBHYjIbi5PvcOPxgDi9QuvNivIdo/5Hm CLedIj8ZdhYMzwQRwrUEvELgiE/7ogy9MaCdA2k/zCx7TXAMg6YhcDMG4SPkzafF8kRkWiG3Z VxYO9l0WwsGnzRu+CcGyv++lOSn7h842+UhVOUAe3ra0f74uFtHGdrdJSutLNSpYYG0Tnnj0V H0iLmlghyYmeNM7XUD1FKGGWlUjX/IWuKqNcY7X2Q= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_082749_246747_53547F7E X-CRM114-Status: GOOD ( 22.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, Marc Zyngier , Mohamed Mediouni , Will Deacon , Stan Skowronek Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Stan Skowronek This includes IPI support and a workaround for non-working WFI on Apple processors. Signed-off-by: Stan Skowronek Signed-off-by: Mohamed Mediouni --- drivers/irqchip/irq-apple-aic.c | 177 +++++++++++++++++++++++++++++--- 1 file changed, 165 insertions(+), 12 deletions(-) -- 2.29.2 diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c index c601bc4b501a..ce4e39d56fcf 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -17,6 +17,7 @@ #include #include +#include #define REG_ID_REVISION 0x0000 #define REG_ID_CONFIG 0x0004 @@ -53,12 +54,17 @@ #define REG_PERCPU(r, c) \ ((r) + REG_CPU_REGION - REG_CPU_LOCAL + ((c) << REG_CPU_SHIFT)) +#define NUM_IPI 8 + static struct aic_chip_data { void __iomem *base; struct irq_domain *domain; unsigned int num_irqs; + bool fast_ipi; } aic; +static DEFINE_PER_CPU(atomic_t, aic_ipi_mask); + static void apple_aic_irq_mask(struct irq_data *d) { writel(REG_IRQ_xABLE_MASK(d->hwirq), @@ -78,18 +84,71 @@ static struct irq_chip apple_aic_irq_chip = { .irq_unmask = apple_aic_irq_unmask, }; -static void apple_aic_fiq_mask(struct irq_data *d) +static void apple_aic_fiq_ipi_mask(struct irq_data *d) { } -static void apple_aic_fiq_unmask(struct irq_data *d) +static void apple_aic_fiq_ipi_unmask(struct irq_data *d) { } static struct irq_chip apple_aic_irq_chip_fiq = { .name = "apple_aic_fiq", - .irq_mask = apple_aic_fiq_mask, - .irq_unmask = apple_aic_fiq_unmask, + .irq_mask = apple_aic_fiq_ipi_mask, + .irq_unmask = apple_aic_fiq_ipi_unmask, +}; + +#define SR_APPLE_IPI_LOCAL s3_5_c15_c0_0 +#define SR_APPLE_IPI_REMOTE s3_5_c15_c0_1 +#define SR_APPLE_IPI_STAT s3_5_c15_c1_1 + +#ifdef CONFIG_SMP +static void apple_aic_ipi_send_mask(struct irq_data *d, + const struct cpumask *mask) +{ + int cpu, lcpu; + int irqnr = d->hwirq - (aic.num_irqs + 2); + + if (WARN_ON(irqnr < 0 || irqnr >= NUM_IPI)) + return; + + /* + * Ensure that stores to Normal memory are visible to the + * other CPUs before issuing the IPI. + */ + wmb(); + + for_each_cpu (cpu, mask) { + smp_mb__before_atomic(); + atomic_or(1u << irqnr, per_cpu_ptr(&aic_ipi_mask, cpu)); + smp_mb__after_atomic(); + lcpu = get_cpu(); + if (aic.fast_ipi) { + if ((lcpu >> 2) == (cpu >> 2)) + write_sysreg(cpu & 3, SR_APPLE_IPI_LOCAL); + else + write_sysreg((cpu & 3) | ((cpu >> 2) << 16), + SR_APPLE_IPI_REMOTE); + } else + writel(lcpu == cpu ? REG_IPI_FLAG_SELF : + (REG_IPI_FLAG_OTHER << cpu), + aic.base + REG_IPI_SET); + put_cpu(); + } + + /* Force the above writes to be executed */ + if (aic.fast_ipi) + isb(); +} +#else +#define apple_aic_ipi_send_mask NULL +#endif + +static struct irq_chip apple_aic_irq_chip_ipi = { + .name = "apple_aic_ipi", + .irq_mask = apple_aic_fiq_ipi_mask, + .irq_unmask = apple_aic_fiq_ipi_unmask, + .ipi_send_mask = apple_aic_ipi_send_mask, }; static int apple_aic_irq_domain_xlate(struct irq_domain *d, @@ -98,16 +157,27 @@ static int apple_aic_irq_domain_xlate(struct irq_domain *d, unsigned long *out_hwirq, unsigned int *out_type) { - if (intspec[0]) { /* FIQ */ + switch (intspec[0]) { + case 0: /* IRQ */ + if (intspec[1] >= aic.num_irqs) + return -EINVAL; + if (out_hwirq) + *out_hwirq = intspec[1]; + break; + case 1: /* FIQ */ if (intspec[1] >= 2) return -EINVAL; if (out_hwirq) *out_hwirq = aic.num_irqs + intspec[1]; - } else { - if (intspec[1] >= aic.num_irqs) + break; + case 2: /* IPI */ + if (intspec[1] >= NUM_IPI) return -EINVAL; if (out_hwirq) - *out_hwirq = intspec[1]; + *out_hwirq = aic.num_irqs + 2 + intspec[1]; + break; + default: + return -EINVAL; } if (out_type) @@ -118,7 +188,13 @@ static int apple_aic_irq_domain_xlate(struct irq_domain *d, static int apple_aic_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw) { - if (hw >= aic.num_irqs) { + if (hw >= aic.num_irqs + 2) { + irq_set_percpu_devid(virq); + irq_domain_set_info(d, virq, hw, &apple_aic_irq_chip_ipi, + d->host_data, handle_percpu_devid_irq, NULL, + NULL); + irq_set_status_flags(virq, IRQ_NOAUTOEN); + } else if (hw >= aic.num_irqs) { irq_set_percpu_devid(virq); irq_domain_set_info(d, virq, hw, &apple_aic_irq_chip_fiq, d->host_data, handle_percpu_devid_irq, NULL, @@ -141,8 +217,10 @@ static const struct irq_domain_ops apple_aic_irq_domain_ops = { static void __exception_irq_entry apple_aic_handle_irq(struct pt_regs *regs) { + atomic_t *maskptr; uint32_t ack; - unsigned done = 0; + unsigned done = 0, irqnr; + unsigned long mask; while (1) { ack = readl(aic.base + REG_IRQ_ACK); @@ -154,6 +232,36 @@ static void __exception_irq_entry apple_aic_handle_irq(struct pt_regs *regs) handle_domain_irq(aic.domain, ack & REG_IRQ_ACK_NUM_MASK, regs); break; + case REG_IRQ_ACK_TYPE_IPI: +#ifdef CONFIG_SMP + if (ack == REG_IRQ_ACK_IPI_SELF) + writel(REG_IPI_FLAG_SELF, + aic.base + REG_IPI_CLEAR); + else + writel(REG_IPI_FLAG_OTHER, + aic.base + REG_IPI_CLEAR); + maskptr = get_cpu_ptr(&aic_ipi_mask); + smp_mb__before_atomic(); + mask = atomic_xchg(maskptr, 0); + smp_mb__after_atomic(); + put_cpu_ptr(&aic_ipi_mask); + for_each_set_bit (irqnr, &mask, NUM_IPI) { + handle_domain_irq(aic.domain, + aic.num_irqs + 2 + irqnr, + regs); + } + if (ack == REG_IRQ_ACK_IPI_SELF) + writel(REG_IPI_FLAG_SELF, + aic.base + + REG_PERCPU(REG_IPI_ENABLE, + __smp_processor_id())); + else + writel(REG_IPI_FLAG_OTHER, + aic.base + + REG_PERCPU(REG_IPI_ENABLE, + __smp_processor_id())); +#endif + break; } if (done) break; @@ -162,6 +270,27 @@ static void __exception_irq_entry apple_aic_handle_irq(struct pt_regs *regs) static void __exception_irq_entry apple_aic_handle_fiq(struct pt_regs *regs) { +#ifdef CONFIG_SMP + atomic_t *maskptr; + unsigned long mask; + unsigned irqnr; + + if (aic.fast_ipi) { + if (read_sysreg(SR_APPLE_IPI_STAT)) { + write_sysreg(1, SR_APPLE_IPI_STAT); + + maskptr = get_cpu_ptr(&aic_ipi_mask); + smp_mb__before_atomic(); + mask = atomic_xchg(maskptr, 0); + smp_mb__after_atomic(); + put_cpu_ptr(&aic_ipi_mask); + for_each_set_bit (irqnr, &mask, NUM_IPI) + handle_domain_irq(aic.domain, + aic.num_irqs + 2 + irqnr, + regs); + } + } +#endif handle_domain_irq(aic.domain, aic.num_irqs, regs); } @@ -169,6 +298,13 @@ void apple_aic_cpu_prepare(unsigned int cpu) { unsigned i; + if (aic.fast_ipi) + writel(REG_IPI_FLAG_SELF | REG_IPI_FLAG_OTHER, + aic.base + REG_PERCPU(REG_IPI_DISABLE, cpu)); + else + writel(REG_IPI_FLAG_SELF | REG_IPI_FLAG_OTHER, + aic.base + REG_PERCPU(REG_IPI_ENABLE, cpu)); + for (i = 0; i < aic.num_irqs; i++) writel(readl(aic.base + REG_IRQ_AFFINITY(i)) | (1u << cpu), aic.base + REG_IRQ_AFFINITY(i)); @@ -178,6 +314,9 @@ static int __init apple_aic_init(struct device_node *node, struct device_node *interrupt_parent) { unsigned i; +#ifdef CONFIG_SMP + int base_ipi, ret; +#endif if (!node) return -ENODEV; @@ -186,8 +325,11 @@ static int __init apple_aic_init(struct device_node *node, if (WARN(!aic.base, "unable to map aic registers\n")) return -EINVAL; + aic.fast_ipi = of_property_read_bool(node, "fast-ipi"); + aic.num_irqs = readl(aic.base + REG_ID_CONFIG) & 0xFFFF; - pr_info("Apple AIC: %d IRQs + 1 FIQ + 1 dummy\n", aic.num_irqs); + pr_info("Apple AIC: %d IRQs + 1 FIQ + 1 dummy + %d IPIs%s\n", + aic.num_irqs, NUM_IPI, aic.fast_ipi ? " (fast)" : ""); for (i = 0; i < aic.num_irqs; i++) writel(1, aic.base + REG_IRQ_AFFINITY(i)); @@ -201,10 +343,21 @@ static int __init apple_aic_init(struct device_node *node, apple_aic_cpu_prepare(0); - aic.domain = irq_domain_add_linear(node, aic.num_irqs + 2, + aic.domain = irq_domain_add_linear(node, aic.num_irqs + 2 + NUM_IPI, &apple_aic_irq_domain_ops, &apple_aic_irq_chip); irq_set_default_host(aic.domain); + +#ifdef CONFIG_SMP + base_ipi = aic.num_irqs + 2; + ret = irq_create_strict_mappings(aic.domain, base_ipi, aic.num_irqs + 2, + NUM_IPI); + if (ret < 0) + pr_err("%s: irq_create_strict_mappings failed with %d\n", + __func__, ret); + set_smp_ipi_range(base_ipi, NUM_IPI); +#endif + return 0; }