From patchwork Thu Jan 21 11:02:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12035591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FAA1C433E0 for ; Thu, 21 Jan 2021 11:05:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D8E5F23602 for ; Thu, 21 Jan 2021 11:05:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D8E5F23602 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=GKz1t6Vexk/Ocgtcd4bZUqqU+UutYSaekfvhUv0Ks7o=; b=RBCaq3bY5iWIMw9WA5mYQD4wFj k/xykX4l+1ROcWECWpOpCB4mUmuKugfhsy3s7npv2ebJI2wTmooSIzoa3mmNvF7fBvVHlhy0PH5vT Ndhjo+wm/nwZUJKqPIxjR1TeFF3ajLiEo4tnMZKuGA0CDrmLtzA62af+ZM870A9X26UYwtlWbZgXn G48bzsQ8F81hGi52js8Qolx794BSL7cHKjA3UKbvjGSvnvs6WE/pWhD8G3UlxXVmYVAue61pjR+Sq 7MbXRNJDZ2LcYVUFiqFKl0CZ/yVDF/Qd6qUL2lNmRxZkBKBL53DwhL6RPwTUrXXTdlMgUAzCeDUgj KKMSxPGg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2XkU-0002sH-Sp; Thu, 21 Jan 2021 11:03:34 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2XkQ-0002oG-Rp for linux-arm-kernel@lists.infradead.org; Thu, 21 Jan 2021 11:03:32 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4DLzxG2g2Bz7YPx; Thu, 21 Jan 2021 19:02:10 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.88.171) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 21 Jan 2021 19:03:07 +0800 From: Shameer Kolothum To: , Subject: [PATCH] genirq/msi: Make sure early activation of all PCI MSIs Date: Thu, 21 Jan 2021 11:02:47 +0000 Message-ID: <20210121110247.20320-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.47.88.171] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210121_060331_431836_D808A37A X-CRM114-Status: GOOD ( 19.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maz@kernel.org, linuxarm@openeuler.org, eric.auger@redhat.com, wangzhou1@hisilicon.com, prime.zeng@hisilicon.com, tglx@linutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We currently do early activation of MSI irqs for PCI/MSI based on the MSI_FLAG_ACTIVATE_EARLY flag. Though this activates all the allocated MSIs in the case of MSI-X, it only does so for the base irq in the case of MSI. This is because, for MSI, there is only one msi_desc entry for all the 32 irqs it can support and the current implementation iterates over the msi entries and ends up activating the base irq only. The above creates an issue on platforms where the msi controller supports direct injection of vLPIs(eg: ARM GICv4 ITS). On these platforms, upon irq activation, ITS driver maps the event to an ITT entry. And for Guest pass-through to work, early mapping of all the dev MSI vectors is required. Otherwise, the vfio irq bypass manager registration will fail. eg, On a HiSilicon D06 platform with GICv4 enabled, Guest boot with zip dev pass-through reports, "vfio-pci 0000:75:00.1: irq bypass producer (token 0000000006e5176a) registration fails: 66311" and Guest boot fails. This is traced to,    kvm_arch_irq_bypass_add_producer      kvm_vgic_v4_set_forwarding        vgic_its_resolve_lpi --> returns E_ITS_INT_UNMAPPED_INTERRUPT Hence make sure we activate all the irqs for both MSI and MSI-x cases. Signed-off-by: Shameer Kolothum --- It is unclear to me whether not performing the early activation of all MSI irqs was deliberate and has consequences on any other platforms. Please let me know. Thanks, Shameer --- kernel/irq/msi.c | 114 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 90 insertions(+), 24 deletions(-) diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 2c0c4d6d0f83..eec187fc32a9 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -395,6 +395,78 @@ static bool msi_check_reservation_mode(struct irq_domain *domain, return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit; } +static void msi_domain_deactivate_irq(struct irq_domain *domain, int irq) +{ + struct irq_data *irqd; + + irqd = irq_domain_get_irq_data(domain, irq); + if (irqd_is_activated(irqd)) + irq_domain_deactivate_irq(irqd); +} + +static int msi_domain_activate_irq(struct irq_domain *domain, + int irq, bool can_reserve) +{ + struct irq_data *irqd; + + irqd = irq_domain_get_irq_data(domain, irq); + if (!can_reserve) { + irqd_clr_can_reserve(irqd); + if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK) + irqd_set_msi_nomask_quirk(irqd); + } + return irq_domain_activate_irq(irqd, can_reserve); +} + +static int msi_domain_activate_msix_irqs(struct irq_domain *domain, + struct device *dev, bool can_reserve) +{ + struct msi_desc *desc; + int ret, irq; + + for_each_msi_entry(desc, dev) { + irq = desc->irq; + ret = msi_domain_activate_irq(domain, irq, can_reserve); + if (ret) + goto out; + } + return 0; + +out: + for_each_msi_entry(desc, dev) { + if (irq == desc->irq) + break; + msi_domain_deactivate_irq(domain, desc->irq); + } + return ret; +} + +static int msi_domain_activate_msi_irqs(struct irq_domain *domain, + struct device *dev, bool can_reserve) +{ + struct msi_desc *desc; + int i, ret, base, irq; + + desc = first_msi_entry(dev); + base = desc->irq; + + for (i = 0; i < desc->nvec_used; i++) { + irq = base + i; + ret = msi_domain_activate_irq(domain, irq, can_reserve); + if (ret) + goto out; + } + return 0; + +out: + for (i = 0; i < desc->nvec_used; i++) { + if (irq == base + i) + break; + msi_domain_deactivate_irq(domain, base + i); + } + return ret; +} + int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, int nvec) { @@ -443,21 +515,25 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, else dev_dbg(dev, "irq [%d-%d] for MSI\n", virq, virq + desc->nvec_used - 1); - /* - * This flag is set by the PCI layer as we need to activate - * the MSI entries before the PCI layer enables MSI in the - * card. Otherwise the card latches a random msi message. - */ - if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY)) - continue; + } - irq_data = irq_domain_get_irq_data(domain, desc->irq); - if (!can_reserve) { - irqd_clr_can_reserve(irq_data); - if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK) - irqd_set_msi_nomask_quirk(irq_data); - } - ret = irq_domain_activate_irq(irq_data, can_reserve); + /* + * This flag is set by the PCI layer as we need to activate + * the MSI entries before the PCI layer enables MSI in the + * card. Otherwise the card latches a random msi message. + * Early activation is also required when the msi controller + * supports direct injection of virtual LPIs(eg. ARM GICv4 ITS). + * Otherwise, the DevID/EventID -> LPI translation for pass-through + * devices will fail. Make sure we do activate all the allocated + * irqs for MSI and MSI-X cases. + */ + if ((info->flags & MSI_FLAG_ACTIVATE_EARLY)) { + desc = first_msi_entry(dev); + + if (desc->msi_attrib.is_msix) + ret = msi_domain_activate_msix_irqs(domain, dev, can_reserve); + else + ret = msi_domain_activate_msi_irqs(domain, dev, can_reserve); if (ret) goto cleanup; } @@ -475,16 +551,6 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, return 0; cleanup: - for_each_msi_entry(desc, dev) { - struct irq_data *irqd; - - if (desc->irq == virq) - break; - - irqd = irq_domain_get_irq_data(domain, desc->irq); - if (irqd_is_activated(irqd)) - irq_domain_deactivate_irq(irqd); - } msi_domain_free_irqs(domain, dev); return ret; }