From patchwork Sat Jan 23 10:39:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBB57C433E0 for ; Sat, 23 Jan 2021 10:47:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 665A623358 for ; Sat, 23 Jan 2021 10:47:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 665A623358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GRy-0000US-8r for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:47:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLJ-0002wo-5f; Sat, 23 Jan 2021 05:40:38 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:46520) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLF-0002uP-Kz; Sat, 23 Jan 2021 05:40:32 -0500 Received: by mail-pg1-x52c.google.com with SMTP id c22so5569264pgg.13; Sat, 23 Jan 2021 02:40:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BkVaQxIMTlL8Oph24ElXi5legL3wqrN1Wo0MOAKX7rk=; b=utT0Tc8RuTDqAcmOEFkzGs0WDw3wZ54N2aSKkf2MW5bC22nGRi6jupE5NyfLAYNcff QjbucA7PdFaUXfvKl42WK/SjTTw6TtC+/UaFha7/9PgbTnA3oRk6IfB5Hb7gq+CrTCTY vCC+1XLMmok3i43LC9zQeWWa3FuU982Zeqzk4xt/oKKt4Ls6Fks0ZIOzWjcFjzHMdDg3 R72H9d5a5K57o64JiE2a0Jd2e36u6D0nnXstt3+CskK1t+A3eElYk+/K55xg00Ivuncm aiMVVYwML11AvNMx+TyOCB8U8CHLe9Ssxzr1LTJSEQ4u/wHPUS2BfvwGVKGU1YJbEnEi 64gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BkVaQxIMTlL8Oph24ElXi5legL3wqrN1Wo0MOAKX7rk=; b=frLv2UdiTKYIb4Yo+L28Y7PpfHnujPfXopseSeMdKhb9I+qjw1w6eidQZzjEUI9LAL mNOyki36gHERwkssytKG10g9banNqHUOYqR2LPx6U47uifvnbK2JgZre9NSzqRjpwpUA rKpJJCFG8Ke3uqwEY6Fv5+9ulcJIv3xacXGQ1qYU3EFOFU25DNM+GUBjtyA3ReDUv6XF TDwULxjoYwrW5wA71jVsDKXUrdiC8xSXFEcYfx0eYJfsXnNvU2bqT6Xk04UncnXmlutl R+AqD5nieN0outPENitbCwzaMssG/h6tChbOsNcCTnrjEsEuLVqrSBdYBRtJMTXqOB/q bWSg== X-Gm-Message-State: AOAM533eTOfLfNYYrcr5fCJjKYKn6TM9tIFVA5S8bV+WfaoggOTHt4N6 5YPezPdUJr2+LwishhQ0gkg= X-Google-Smtp-Source: ABdhPJwIvx9uHPiBKoplu3Y/yRo0Yx5ug6gyCeQQ8o9/4q8XN6jpYmy2rFeh8QzFEP0kZUZ58B6ssg== X-Received: by 2002:a63:1602:: with SMTP id w2mr9384825pgl.128.1611398427432; Sat, 23 Jan 2021 02:40:27 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:27 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/25] hw/block: m25p80: Add ISSI SPI flash support Date: Sat, 23 Jan 2021 18:39:52 +0800 Message-Id: <20210123104016.17485-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Likewise, the same default value is used for fast read dual/quad I/O command. Per the datasheet [1], the number of dummy cycles is configurable, but this is not modeled at present. For flash whose size is larger than 16 MiB, the sequence of 3-byte address along with EXTADD bit in the bank address register (BAR) is not supported. We assume that guest software always uses op codes with 4-byte address sequence. Fortunately, this is the case for both U-Boot and Linux spi-nor drivers. QPI (Quad Peripheral Interface) that supports 2-cycle instruction has different default values for dummy cycles of fast read family commands, and is unsupported at the time being. [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf Signed-off-by: Bin Meng --- Changes in v2: - Mention QPI (Quad Peripheral Interface) mode is not supported hw/block/m25p80.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index b744a58d1c..217c130f56 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -412,6 +412,7 @@ typedef enum { MAN_NUMONYX, MAN_WINBOND, MAN_SST, + MAN_ISSI, MAN_GENERIC, } Manufacturer; @@ -487,6 +488,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_MACRONIX; case 0xBF: return MAN_SST; + case 0x9D: + return MAN_ISSI; default: return MAN_GENERIC; } @@ -706,6 +709,9 @@ static void complete_collecting_data(Flash *s) case MAN_SPANSION: s->quad_enable = !!(s->data[1] & 0x02); break; + case MAN_ISSI: + s->quad_enable = extract32(s->data[0], 6, 1); + break; case MAN_MACRONIX: s->quad_enable = extract32(s->data[0], 6, 1); if (s->len > 1) { @@ -895,6 +901,19 @@ static void decode_fast_read_cmd(Flash *s) SPANSION_DUMMY_CLK_LEN ); break; + case MAN_ISSI: + /* + * The Fast Read instruction code is followed by address bytes and + * dummy cycles, transmitted via the SI line. + * + * The number of dummy cycles is configurable but this is currently + * unmodeled, hence the default value 8 is used. + * + * QPI (Quad Peripheral Interface) mode has different default value + * of dummy cycles, but this is unsupported at the time being. + */ + s->needed_bytes += 1; + break; default: break; } @@ -934,6 +953,16 @@ static void decode_dio_read_cmd(Flash *s) break; } break; + case MAN_ISSI: + /* + * The Fast Read Dual I/O instruction code is followed by address bytes + * and dummy cycles, transmitted via the IO1 and IO0 line. + * + * The number of dummy cycles is configurable but this is currently + * unmodeled, hence the default value 4 is used. + */ + s->needed_bytes += 1; + break; default: break; } @@ -974,6 +1003,19 @@ static void decode_qio_read_cmd(Flash *s) break; } break; + case MAN_ISSI: + /* + * The Fast Read Quad I/O instruction code is followed by address bytes + * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. + * + * The number of dummy cycles is configurable but this is currently + * unmodeled, hence the default value 6 is used. + * + * QPI (Quad Peripheral Interface) mode has different default value + * of dummy cycles, but this is unsupported at the time being. + */ + s->needed_bytes += 3; + break; default: break; } @@ -1132,7 +1174,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) case RDSR: s->data[0] = (!!s->write_enable) << 1; - if (get_man(s) == MAN_MACRONIX) { + if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { s->data[0] |= (!!s->quad_enable) << 6; } if (get_man(s) == MAN_SST) { From patchwork Sat Jan 23 10:39:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0FA1C433DB for ; Sat, 23 Jan 2021 10:49:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6564623358 for ; Sat, 23 Jan 2021 10:49:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6564623358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:43192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GTu-0003z7-Bs for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:49:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLO-0002z1-2x; Sat, 23 Jan 2021 05:40:38 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:38063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLH-0002vX-QM; Sat, 23 Jan 2021 05:40:37 -0500 Received: by mail-pg1-x52a.google.com with SMTP id q7so5599856pgm.5; Sat, 23 Jan 2021 02:40:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yYTOVsDICNYs9a4Nc8bQDRVEnCpcAczZDVceLgRkdvo=; b=kcVubV9vjsxs3ZxGmi6MkWnOdGAQ1RVTzDbCWxXuar0/EM/BamDS4Z4nLxPluxgFRV Sn7BfbS3S75B6VUyOzxnwYmfX6JpF607XR4kqVgea95f8hVAt/g6rElinTiOneiY9VCJ rD1k+/IHgcoGnXxfv15VhMGUmNXUQjnk8Ioeu0uXGJLh8Xc5dE2y+9LW9yOsjXafC5en 4NF7+bVna9Oqp5lO2rbqfdOluAiN12p7CKoUlH0hDvqOvLHgnMor0ZB898xaJ8F8XiJZ tKB2XsldH0RVw+cRYHQOhqP3JHJrFRpgPxanovJQDNZsg0AqG/HHYYzzN/ZfZCU/p5Nu Pwzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yYTOVsDICNYs9a4Nc8bQDRVEnCpcAczZDVceLgRkdvo=; b=PNYwiDvf7QNihHgY63xeRNpFYRESzZ0k3kqamZHHAwA+4s0B4nEO8kTZVey1xuErU5 9Iej76Hn+mbNGo8MZ39XrytDRYFN6oldKRo05bb6cQqdLrGhGzxoG23vVVR7RtZ62O6Z LJeBfz/74mGOr+cUDYoeSYFfV9e8FmIvNBtet7V2fVL49Uy8p6TStaFNweiYYjmoG72T MoZmCKd9NUHqNP+ojY+8MnLXrQWFPMTXzeZZEJT1MVHsAWYH0+qNEVvUxktaOsVa6MB9 asWnRxKi19bXvBLCUYNGvsZ3BR5a6DHSX6bJkj8S5hJ5Bq9gzgUgOmNFeGG8lBInVX6o TAMA== X-Gm-Message-State: AOAM531Asvjh/5tb7Yn3C3Oaj3mOoG9sRjSLgI7N5GZe7UJr3uI+5W2U Kdyn0Z409iVw7wyApk7fRyo= X-Google-Smtp-Source: ABdhPJw8J2LCeCIrP3654oAube3BZMLZwuW/+nIlv2eDbJa7ctfivBd+8aKt+JdvIM3qBDDFLC9Xxg== X-Received: by 2002:a63:6344:: with SMTP id x65mr9102420pgb.172.1611398429996; Sat, 23 Jan 2021 02:40:29 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:29 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/25] hw/block: m25p80: Add various ISSI flash information Date: Sat, 23 Jan 2021 18:39:53 +0800 Message-Id: <20210123104016.17485-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- (no changes since v1) hw/block/m25p80.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 217c130f56..4bf8aa8158 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -210,6 +210,19 @@ static const FlashPartInfo known_devices[] = { { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, + /* ISSI */ + { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, + { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, + { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, + { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, + { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, + { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, + { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, + { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, + { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, + { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, + { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) }, + /* Macronix */ { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, From patchwork Sat Jan 23 10:39:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35591C433DB for ; Sat, 23 Jan 2021 10:44:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C717C22DCC for ; Sat, 23 Jan 2021 10:44:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C717C22DCC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GP8-0005L0-Oz for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:44:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLT-00032f-J2; Sat, 23 Jan 2021 05:40:45 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:39075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLM-0002wP-4C; Sat, 23 Jan 2021 05:40:43 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 30so5595825pgr.6; Sat, 23 Jan 2021 02:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l6w90ZfsMt4jWRp3kwdSmprnCxB/Wq/3rVtoRL2E9es=; b=kDqUTyeND1B/c0uEFLg94OdJlqjE0M5qP6AbQ3LXjv8fIbftzVbwKgwnNFNSm5xM4p +jSmvhfzNsKMjXaftpLBriWIMoJhUru4f9tQn/F3PYzXlzPuTexmatMd8GtkaON2PQqs Z2u8DLXMybwjRUzq3nbv3ruOsCOiVBHGUQTiFQ4peJVkN9eqWIWaWBokw3Axtl8LoaGp QJe4LKL1vg0OS5PFcJFs0k+1S/WUeNooEImw0gNIA9CuBJ7fO2clA3Gz9YN6+JpptI4w HdGhN7qUiUrkUvvaxChFewBxDVeQfyZvvMcvNW/z5SgrpeVgbe2f9MTiHOlyrWNjYM1j roEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l6w90ZfsMt4jWRp3kwdSmprnCxB/Wq/3rVtoRL2E9es=; b=Gn+D4ca6iDEaZP22teUcc9JXAZ67DriP8sYhjD4jefpuSq6fZasfUmzzGnTGjImwWM oFKuf19eZ/zKFuvuSPtc90tWTviBRETdxRB9MtgWifgrX7jpdNNqXvdnAf+AJ3YBxxwI oMP7JgeVJonLh2wi7ywVi0endDwYFO9wdQX1fQHkGGIZ5wgy5pY7I5Vhrz8RAoxlkr1o iFGCJX+jpG4wEfhg6sPtIXkWyx8BnvOD2sUbHwxTyNEj61SHD6uME68L8IKgreswipaq PkS0ys8IUG1jYpufvg1mbhmGsS2K+IFdFnbnGHRjm9TfmAhyAjSkP+C9Rh44S9i76efr RDhg== X-Gm-Message-State: AOAM530CbQMFzQzUCEBgwBiex8nu+TGVg2CCn/F8KgDw90Cj4fJ+JcOa +RPM7I6c9WmCtP/xBfMsO2E= X-Google-Smtp-Source: ABdhPJyJKZpokHs/r76KJqGkLKROGbrV9Kq9bRKENrsF2rDCH+U+Zcp09wRXU0k/vO4AMNDag7QHlg== X-Received: by 2002:a63:50a:: with SMTP id 10mr2144683pgf.273.1611398432792; Sat, 23 Jan 2021 02:40:32 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:32 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/25] hw/sd: ssi-sd: Fix incorrect card response sequence Date: Sat, 23 Jan 2021 18:39:54 +0800 Message-Id: <20210123104016.17485-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Pragnesh Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per the "Physical Layer Specification Version 8.00" chapter 7.5.1, "Command/Response", there is a minimum 8 clock cycles (Ncr) before the card response shows up on the data out line. However current implementation jumps directly to the sending response state after all 6 bytes command is received, which is a spec violation. Add a new state PREP_RESP in the ssi-sd state machine to handle it. Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel Tested-by: Pragnesh Patel Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: - Add a debug printf in the state handling codes hw/sd/ssi-sd.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 9a75e0095c..043e270066 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -36,6 +36,7 @@ do { fprintf(stderr, "ssi_sd: error: " fmt , ## __VA_ARGS__);} while (0) typedef enum { SSI_SD_CMD = 0, SSI_SD_CMDARG, + SSI_SD_PREP_RESP, SSI_SD_RESPONSE, SSI_SD_DATA_START, SSI_SD_DATA_READ, @@ -163,12 +164,16 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->response[1] = status; DPRINTF("Card status 0x%02x\n", status); } - s->mode = SSI_SD_RESPONSE; + s->mode = SSI_SD_PREP_RESP; s->response_pos = 0; } else { s->cmdarg[s->arglen++] = val; } return 0xff; + case SSI_SD_PREP_RESP: + DPRINTF("Prepare card response (Ncr)\n"); + s->mode = SSI_SD_RESPONSE; + return 0xff; case SSI_SD_RESPONSE: if (s->stopping) { s->stopping = 0; From patchwork Sat Jan 23 10:39:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9358C433DB for ; Sat, 23 Jan 2021 10:44:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3EA6422DCC for ; Sat, 23 Jan 2021 10:44:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3EA6422DCC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GPF-0005ev-D7 for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:44:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLb-00034E-Pg; Sat, 23 Jan 2021 05:40:52 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:34589) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLO-0002x9-0G; Sat, 23 Jan 2021 05:40:47 -0500 Received: by mail-pj1-x1036.google.com with SMTP id my11so7490870pjb.1; Sat, 23 Jan 2021 02:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RuQ3gOwEbnCFLQacowSgyfhpGP/J5gBP7ftXBeVEIVk=; b=TXrJWP8cIxN9PV4tHIr1LR0D5IQHovzllkN5impJQLzRmyfB/Cd4kOqQ11Kawuf4NJ BHpPi4Tm2+6j+/+pd+U/mYzYh260LnN1z6c8vDHgLUwgk2EVkJSGMNUgvfVPTJJuXc2+ eXcZ/U5ZgAeYbaNpRebF57gORT8SGmzpE+1IVSgEq/4cioE3w+uTzKyfjVs45HogSpqQ Qw5TqmBvSpw/6/2DHdWNFs0Cyc+PMEQqPXQO16IfPO0PLCLwDVDjE78KSQF/sHIKnRm+ OJwliPPowigLqddSDHtjOSF7/NGDRrI5afXdgrJUAh3wW9iwNU/3ik1xUHR7FPG4HvDQ YJcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RuQ3gOwEbnCFLQacowSgyfhpGP/J5gBP7ftXBeVEIVk=; b=a7MW76U4wHylEJK8DjnlYLYlRHNF9FlDmgDR9EgMrrw1QUNgqUjhR/BA2skVXQJqF/ LNiWjQ51/uEMl4On9Ysnmoh1QdynRoJ3ANlR+uuWo0936tdJdXmLM7jZWXg4Pkr7zoQn twha28EggynbegP2hzTRmbKWXsVRGerkh9av8c0nwCYD715JKhhrGwQJ2pUt6o2VoURN wFc+nonLF0QsvscSmD6JM1r6T9Usy6xzS0/Q+XaP7Chcn/K2IYiblwHBxRZ8x9/4Tyuh 6cqUOwpMiZ2HdEKRQXPP0IWQqloG0qthVPSyhlQZtWGQBcglKsyRsvj4smfYHf18knBO WKSA== X-Gm-Message-State: AOAM5338a/F04H3IBZalU2saWQvlsYeoFqqAoGJfR6QT437dXsTmPQ0t Ng9j/eandd2GME8yANcErFg= X-Google-Smtp-Source: ABdhPJxQhOyxnpicJMb8ceUpiLYZT3tR3nj4CI2SS/LodjTd+9q3xfMJhk6cOZEiZpQCtjIabYfIVA== X-Received: by 2002:a17:90b:881:: with SMTP id bj1mr228389pjb.150.1611398435478; Sat, 23 Jan 2021 02:40:35 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:35 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/25] hw/sd: sd: Support CMD59 for SPI mode Date: Sat, 23 Jan 2021 18:39:55 +0800 Message-Id: <20210123104016.17485-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Pragnesh Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng After the card is put into SPI mode, CRC check for all commands including CMD0 will be done according to CMD59 setting. But this command is currently unimplemented. Simply allow the decoding of CMD59, but the CRC remains unchecked. Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel Tested-by: Pragnesh Patel Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v1) hw/sd/sd.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 4375ed5b8b..bfea5547d5 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1517,18 +1517,12 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) if (!sd->spi) { goto bad_cmd; } - goto unimplemented_spi_cmd; + return sd_r1; default: bad_cmd: qemu_log_mask(LOG_GUEST_ERROR, "SD: Unknown CMD%i\n", req.cmd); return sd_illegal; - - unimplemented_spi_cmd: - /* Commands that are recognised but not yet implemented in SPI mode. */ - qemu_log_mask(LOG_UNIMP, "SD: CMD%i not implemented in SPI mode\n", - req.cmd); - return sd_illegal; } qemu_log_mask(LOG_GUEST_ERROR, "SD: CMD%i in a wrong state\n", req.cmd); From patchwork Sat Jan 23 10:39:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1244AC433E0 for ; Sat, 23 Jan 2021 10:52:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8CE0E23358 for ; Sat, 23 Jan 2021 10:52:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8CE0E23358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:53780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GWt-0008W0-Lw for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:52:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLb-00034C-P1; Sat, 23 Jan 2021 05:40:52 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:38670) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLR-0002yT-E0; Sat, 23 Jan 2021 05:40:46 -0500 Received: by mail-pl1-x634.google.com with SMTP id d4so4731698plh.5; Sat, 23 Jan 2021 02:40:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yZCtk3pSUPvfXlClwRPrI//hxIZ74y5ldXEVKrWZP+A=; b=XWuqzsC1/KZMYbpW5K2E9qNI3BdDT6iQ3Dhs4Yh4EWv2aGPABd5drqZRIZG2pHehvB 0LF5zCeM/9CdIn+XEF3aAONzf1UCyl0GMy1jiupVqfNnHGvxqj7U9rxlGzlVsZ6aGXCw EbB1KOfXLek/MdpLHuGr1fsqJS97yJYA1SoNZjMU0vYDR+2wVCI1PZQtD1UKwlQ1OnY1 cRzRPQ5ZxA02aIUitZzkqNFN1SjCShXA6imllI2eJZhMjm+TzRXXA6sXJLUoHqMu6AE/ KTLatw6r2fO5NiUbj/FfPpQk+Z0Nd3QpxnQYVXrQxBIrUo1ErbMI5ZhxM6DYOFsmQm3u m3/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yZCtk3pSUPvfXlClwRPrI//hxIZ74y5ldXEVKrWZP+A=; b=f/KEXbidWoZDAMnDq2ybFtpDLMxbQ6qkWUSRJsKCoCivYGxnMMvhD8EJSXHSi697bs pU4X9F9Bre7gJPrMjI+hLLrI0vbsfLDo/zEHq5O/0/6QG2MQ7122Wgl+9T+JhiEzu/Sy VKn3LbYW9wo+Di1JymvrNIv/ux+ZdhO/TumrRq0HeClV72KEtbsTBn7eygJL2v9m1MZZ 7koPphSzMr5AtsRTI+mpx8hFv63zkILCrQb+s+R9fB0QOjqc5kB526A631omBBRyUkKD 7FXam92B9QZNrAJdIK0q7UlPPr5gCRNmF2YOkoaUW5nkPpOKYY7AkDN4OvuIXJNCOLSY oclg== X-Gm-Message-State: AOAM530hPyopc+CBjzmpVySHoBK77S7sAq9RpuveqHQ+G8BGNCAwOswO ZB9DQuUtqC0Z02zRt57efjE= X-Google-Smtp-Source: ABdhPJxWnTh9D/WXpSrXJ/FGUn/EKdjbO67zPOkPrmz2gy51pYFla1iSPJTCp+TsxGNRCNxOJDZWhw== X-Received: by 2002:a17:90a:2947:: with SMTP id x7mr20584pjf.157.1611398438176; Sat, 23 Jan 2021 02:40:38 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:37 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/25] hw/sd: sd: Drop sd_crc16() Date: Sat, 23 Jan 2021 18:39:56 +0800 Message-Id: <20210123104016.17485-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Pragnesh Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng commit f6fb1f9b319f ("sdcard: Correct CRC16 offset in sd_function_switch()") changed the 16-bit CRC to be stored at offset 64. In fact, this CRC calculation is completely wrong. From the original codes, it wants to calculate the CRC16 of the first 64 bytes of sd->data[], however passing 64 as the `width` to sd_crc16() actually counts 256 bytes starting from the `message` for the CRC16 calculation, which is not what we want. Besides that, it seems existing sd_crc16() algorithm does not match the SD spec, which says CRC16 is the CCITT one but the calculation does not produce expected result. It turns out the CRC16 was never transferred outside the sd core, as in sd_read_byte() we see: if (sd->data_offset >= 64) sd->state = sd_transfer_state; Given above reasons, let's drop it. Signed-off-by: Bin Meng Reviewed-by: Pragnesh Patel Tested-by: Pragnesh Patel Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: - Fix several typos in the commit message hw/sd/sd.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index bfea5547d5..b3952514fe 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -271,23 +271,6 @@ static uint8_t sd_crc7(const void *message, size_t width) return shift_reg; } -static uint16_t sd_crc16(const void *message, size_t width) -{ - int i, bit; - uint16_t shift_reg = 0x0000; - const uint16_t *msg = (const uint16_t *)message; - width <<= 1; - - for (i = 0; i < width; i ++, msg ++) - for (bit = 15; bit >= 0; bit --) { - shift_reg <<= 1; - if ((shift_reg >> 15) ^ ((*msg >> bit) & 1)) - shift_reg ^= 0x1011; - } - - return shift_reg; -} - #define OCR_POWER_DELAY_NS 500000 /* 0.5ms */ FIELD(OCR, VDD_VOLTAGE_WINDOW, 0, 24) @@ -843,7 +826,6 @@ static void sd_function_switch(SDState *sd, uint32_t arg) sd->data[16 - (i >> 1)] |= new_func << ((i % 2) * 4); } memset(&sd->data[17], 0, 47); - stw_be_p(sd->data + 64, sd_crc16(sd->data, 64)); } static inline bool sd_wp_addr(SDState *sd, uint64_t addr) From patchwork Sat Jan 23 10:39:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 078D3C433E0 for ; Sat, 23 Jan 2021 10:53:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71713233E2 for ; Sat, 23 Jan 2021 10:53:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 71713233E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GY9-0002sq-EE for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:53:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLh-00035r-Va; Sat, 23 Jan 2021 05:40:58 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:53608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLT-0002yk-Vv; Sat, 23 Jan 2021 05:40:57 -0500 Received: by mail-pj1-x1031.google.com with SMTP id p15so5386208pjv.3; Sat, 23 Jan 2021 02:40:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ALbOnPfAfRKgJyHGBPzPuuobeeq+W6JbjseuGZyJZws=; b=OOv1jg3wWVbptbKdfWPn+gPNhsBvt02LBzkk3qcctDzuBdPju4i29mMVLQ1ZNaqr0e E7lMQH0rhBGk7Ceux+opbsPo5Z8IaLJ7O9kOrbMROqY9G2lqkk5cmJe/rpnNKxfsGhr1 tMdu4Fwl6mljLoi4wQoTC7YlUOSUypUlZSDjiNiIo+BdeSL00cNnJI3cUbdBfLyO+cUS ISrngtnIGBF1Zu0cg1QfCSTwt+1DIrYo48L2tWDhO+bXC634o9DyBScoSSXCrFGJALht 9NaGdtggQ62OWhsDkuKQa73KqW/j0x+e8kzGk2WoFbpcxWcrxwLZJCnTeeQPwRHejlPW mo7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ALbOnPfAfRKgJyHGBPzPuuobeeq+W6JbjseuGZyJZws=; b=HrVwSMguaSlUdVGmZrplk2OEFmRyf1I5xaW98Y9uoSrpynJOBxCbmzEqR39YDLKbLr 7xpgk2H6FYnv/O9eQgAfelTsFWcGHeTJ7xwduvnG7VhYZU2bV2vTw4x30izgAqA6Rvm0 AgLR5PdqukVoC3V1YpR40xE7LEdpKUSiQqLihtZdpw0CGil7VDEFi/Dh40EU1ohiXjW1 /6DtfAG90YPHxUY00DJB8P1X9T8MK7U7JjpsB8U3i6HCmHHfKSNtwCJ92r2Tu2RuFX+l cOg9pEwcm0jUjIW+9X5949OX7UdYEg9pHbAUgl3hsZnJBRGbFAP4JNw05Zpbpv2m5X/N fdFA== X-Gm-Message-State: AOAM530gQlSB4gol3lG5K1ORAsWa/qCYIjfKlNohg5ME1n+jyxtcY2cR Wg+nakblmc0BkMxKRNAprKfEn8HNUjBhZg== X-Google-Smtp-Source: ABdhPJwtL0i3HRpODt6E29cG6zASj7zBtkfgtPjs0iOJMcsRYGF6QMBZV/YPRfh9RjyBz/EAJrYVHA== X-Received: by 2002:a17:90a:fc3:: with SMTP id 61mr752613pjz.197.1611398440666; Sat, 23 Jan 2021 02:40:40 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:40 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines Date: Sat, 23 Jan 2021 18:39:57 +0800 Message-Id: <20210123104016.17485-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Import CRC16 calculation routines from Linux kernel v5.10: include/linux/crc-ccitt.h lib/crc-ccitt.c to QEMU: include/qemu/crc-ccitt.h util/crc-ccitt.c Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v1) include/qemu/crc-ccitt.h | 33 ++++++++++ util/crc-ccitt.c | 127 +++++++++++++++++++++++++++++++++++++++ util/meson.build | 1 + 3 files changed, 161 insertions(+) create mode 100644 include/qemu/crc-ccitt.h create mode 100644 util/crc-ccitt.c diff --git a/include/qemu/crc-ccitt.h b/include/qemu/crc-ccitt.h new file mode 100644 index 0000000000..06ee55b159 --- /dev/null +++ b/include/qemu/crc-ccitt.h @@ -0,0 +1,33 @@ +/* + * CRC16 (CCITT) Checksum Algorithm + * + * Copyright (c) 2021 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * From Linux kernel v5.10 include/linux/crc-ccitt.h + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _CRC_CCITT_H +#define _CRC_CCITT_H + +extern uint16_t const crc_ccitt_table[256]; +extern uint16_t const crc_ccitt_false_table[256]; + +extern uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len); +extern uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len); + +static inline uint16_t crc_ccitt_byte(uint16_t crc, const uint8_t c) +{ + return (crc >> 8) ^ crc_ccitt_table[(crc ^ c) & 0xff]; +} + +static inline uint16_t crc_ccitt_false_byte(uint16_t crc, const uint8_t c) +{ + return (crc << 8) ^ crc_ccitt_false_table[(crc >> 8) ^ c]; +} + +#endif /* _CRC_CCITT_H */ diff --git a/util/crc-ccitt.c b/util/crc-ccitt.c new file mode 100644 index 0000000000..b981d8ac55 --- /dev/null +++ b/util/crc-ccitt.c @@ -0,0 +1,127 @@ +/* + * CRC16 (CCITT) Checksum Algorithm + * + * Copyright (c) 2021 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * From Linux kernel v5.10 lib/crc-ccitt.c + * + * SPDX-License-Identifier: GPL-2.0-only + */ + +#include "qemu/osdep.h" +#include "qemu/crc-ccitt.h" + +/* + * This mysterious table is just the CRC of each possible byte. It can be + * computed using the standard bit-at-a-time methods. The polynomial can + * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12. + * Add the implicit x^16, and you have the standard CRC-CCITT. + */ +uint16_t const crc_ccitt_table[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, + 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, + 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, + 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, + 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, + 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, + 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, + 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, + 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, + 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, + 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, + 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, + 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, + 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, + 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, + 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, + 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, + 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, + 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, + 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, + 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, + 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, + 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, + 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, + 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, + 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, + 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, + 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, + 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 +}; + +/* + * Similar table to calculate CRC16 variant known as CRC-CCITT-FALSE + * Reflected bits order, does not augment final value. + */ +uint16_t const crc_ccitt_false_table[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, + 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, + 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, + 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, + 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, + 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, + 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, + 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, + 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, + 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, + 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, + 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, + 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, + 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, + 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, + 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, + 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, + 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, + 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, + 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, + 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, + 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, + 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0 +}; + +/** + * crc_ccitt - recompute the CRC (CRC-CCITT variant) + * for the data buffer + * + * @crc: previous CRC value + * @buffer: data pointer + * @len: number of bytes in the buffer + */ +uint16_t crc_ccitt(uint16_t crc, uint8_t const *buffer, size_t len) +{ + while (len--) { + crc = crc_ccitt_byte(crc, *buffer++); + } + return crc; +} + +/** + * crc_ccitt_false - recompute the CRC (CRC-CCITT-FALSE variant) + * for the data buffer + * + * @crc: previous CRC value + * @buffer: data pointer + * @len: number of bytes in the buffer + */ +uint16_t crc_ccitt_false(uint16_t crc, uint8_t const *buffer, size_t len) +{ + while (len--) { + crc = crc_ccitt_false_byte(crc, *buffer++); + } + return crc; +} diff --git a/util/meson.build b/util/meson.build index 540a605b78..05a376ae02 100644 --- a/util/meson.build +++ b/util/meson.build @@ -29,6 +29,7 @@ util_ss.add(files('qemu-config.c', 'notify.c')) util_ss.add(files('qemu-option.c', 'qemu-progress.c')) util_ss.add(files('keyval.c')) util_ss.add(files('crc32c.c')) +util_ss.add(files('crc-ccitt.c')) util_ss.add(files('uuid.c')) util_ss.add(files('getauxval.c')) util_ss.add(files('rcu.c')) From patchwork Sat Jan 23 10:39:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 833F0C433E6 for ; Sat, 23 Jan 2021 10:47:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 16B6822DCC for ; Sat, 23 Jan 2021 10:47:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 16B6822DCC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GRx-0000Tu-Sr for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:47:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51080) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLd-00034d-KN; Sat, 23 Jan 2021 05:40:54 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:39522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLW-00030G-FL; Sat, 23 Jan 2021 05:40:53 -0500 Received: by mail-pj1-x1030.google.com with SMTP id u4so5457468pjn.4; Sat, 23 Jan 2021 02:40:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ktbhuYLuMNGFg6d3UKLkt2kVZEQvBOKHZn5SKljkb2c=; b=HK4/4m5+ldSOJMsh245B9wTVkqqKPt4I34hQckT/uVgrPIJ0guMoEyNE1kkKLHS41+ KwyIdnMigYeFfpSpz0R00+qD4J9UVLpUm9S4zdpStNL9Z956TORzDvKaY5T56b+MSmpM MkjcybPOZ7aSGPWpAphJcD/pGIoumptdbt3q77mTFziPr3yim77jNBtPb9X/wf8LB+zO zrI3P5/1FmKvZT+ms6kxUCo4bzqECrcbzcf6LW2auXA/cHrLZLe87ErcNHSMUzlYK/6q S1NYDqkz3PsNZ/cpG6CrLAPOoNNa0XvmDhzTBzVQG+56mB8ThefhsfS5GoC1dAYMV/iV nZOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ktbhuYLuMNGFg6d3UKLkt2kVZEQvBOKHZn5SKljkb2c=; b=f4ESWWabmMzkgbsyCYh+l+UIH3ol+snvkr7wpKgbShQZoLYb84VRqouLWnNBH9nWBS TiMgQ11RpygMrtfNDvzdt7TwaPKSyOHh8lW3esVVbQ8l5GyccK2yYxO5RNXnlYlJq11c HqvT+6sVnbrcTh+BleC3CVUxr1VVdx/ENS9ItlhDUg3Iii1zPhgxkLiml3b7IMGVjJM2 6xIzS9SyTTcVp2uNcaWI+xpzy1JqWaEivZBX6+AH2JSdPiOosjf2rsBMXx+SI7j2MreA g2cPB2P1aXiqAJMDtaM/IAJeUEyfDBSq3v1HZYsO1PYpaMcqsCQA1ZndkiSS0zEL8rQZ lVRQ== X-Gm-Message-State: AOAM530waYM9hdfNq3NO1i2xasAechEHzCfgNrKuzOZkskFklx3v5wEA D0wZNBiJzFJWhMW4FL+Gpy4NBU7hTATewA== X-Google-Smtp-Source: ABdhPJzEN7Cpdp0yr8IHXv8/GSU+FP8kqxXtQwPvluJ9Ab9PmuoxftBJXsSEuIoMleJeAtEX+VyaiQ== X-Received: by 2002:a17:90b:3805:: with SMTP id mq5mr10644546pjb.93.1611398443189; Sat, 23 Jan 2021 02:40:43 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:42 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/25] hw/sd: ssi-sd: Suffix a data block with CRC16 Date: Sat, 23 Jan 2021 18:39:58 +0800 Message-Id: <20210123104016.17485-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per the SD spec, a valid data block is suffixed with a 16-bit CRC generated by the standard CCITT polynomial x16+x12+x5+1. This part is currently missing in the ssi-sd state machine. Without it, all data block transfer fails in guest software because the expected CRC16 is missing on the data out line. Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v1) hw/sd/ssi-sd.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 043e270066..8bccedfab2 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -17,6 +17,7 @@ #include "hw/qdev-properties.h" #include "hw/sd/sd.h" #include "qapi/error.h" +#include "qemu/crc-ccitt.h" #include "qemu/module.h" #include "qom/object.h" @@ -40,6 +41,7 @@ typedef enum { SSI_SD_RESPONSE, SSI_SD_DATA_START, SSI_SD_DATA_READ, + SSI_SD_DATA_CRC16, } ssi_sd_mode; struct ssi_sd_state { @@ -48,6 +50,7 @@ struct ssi_sd_state { int cmd; uint8_t cmdarg[4]; uint8_t response[5]; + uint16_t crc16; int32_t arglen; int32_t response_pos; int32_t stopping; @@ -194,12 +197,24 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) case SSI_SD_DATA_START: DPRINTF("Start read block\n"); s->mode = SSI_SD_DATA_READ; + s->response_pos = 0; return 0xfe; case SSI_SD_DATA_READ: val = sdbus_read_byte(&s->sdbus); + s->crc16 = crc_ccitt_false(s->crc16, (uint8_t *)&val, 1); if (!sdbus_data_ready(&s->sdbus)) { DPRINTF("Data read end\n"); + s->mode = SSI_SD_DATA_CRC16; + } + return val; + case SSI_SD_DATA_CRC16: + val = (s->crc16 & 0xff00) >> 8; + s->crc16 <<= 8; + s->response_pos++; + if (s->response_pos == 2) { + DPRINTF("CRC16 read end\n"); s->mode = SSI_SD_CMD; + s->response_pos = 0; } return val; } @@ -237,6 +252,7 @@ static const VMStateDescription vmstate_ssi_sd = { VMSTATE_INT32(cmd, ssi_sd_state), VMSTATE_UINT8_ARRAY(cmdarg, ssi_sd_state, 4), VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5), + VMSTATE_UINT16(crc16, ssi_sd_state), VMSTATE_INT32(arglen, ssi_sd_state), VMSTATE_INT32(response_pos, ssi_sd_state), VMSTATE_INT32(stopping, ssi_sd_state), @@ -288,6 +304,7 @@ static void ssi_sd_reset(DeviceState *dev) s->cmd = 0; memset(s->cmdarg, 0, sizeof(s->cmdarg)); memset(s->response, 0, sizeof(s->response)); + s->crc16 = 0; s->arglen = 0; s->response_pos = 0; s->stopping = 0; From patchwork Sat Jan 23 10:39:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10A04C433DB for ; Sat, 23 Jan 2021 10:56:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AC3D4233E2 for ; Sat, 23 Jan 2021 10:56:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AC3D4233E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GaV-0005ey-PW for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:56:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLk-0003BC-M2; Sat, 23 Jan 2021 05:41:00 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:36295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLc-000311-7l; Sat, 23 Jan 2021 05:41:00 -0500 Received: by mail-pj1-x102a.google.com with SMTP id e6so5475487pjj.1; Sat, 23 Jan 2021 02:40:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QtlieItfiW2uS3tWTv06gLh4blc9qN5sDQVQkFIfd3M=; b=or1c0Os3L8661o6959/JxYbcMuYeSo5dbi+B6VPP2Txs+F9HRPHvSXGRZBojk2RE1j 0HKb3uM9w/2giJaYVBO6IjsOEGe5AWOTexgYrn78nvxay97o6Mxw0t/YRLjc8ZEw+YUo 7i18RscXiSqbwYzQG3VgnotbPx9m+EyHCevLIAEpDCfGBS/qxp6+8nOC9XWJeClg/BRi voOD/lZFFGI7g46g3rgcew88EarY7IKIYdCoci6HHqxm6fVfl6VQQFCmGwECptJWYPFA QFYo/btECz7G3LQw8aXrGvz5oGczEYlgjCrF5oc/9aQ4kWZT6pgP5jmcgAXmvboOqb0G ltvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QtlieItfiW2uS3tWTv06gLh4blc9qN5sDQVQkFIfd3M=; b=qrUEzNg/33dCLposmLY1eoLaSkUB+aXpxKjnMlMNk2T3tDcZRjojqWuRyyi3yQ2qJi QRL5gYEhHQnbfOjD8MFLKjdSbrg+blHHBnIrDkUQKM1hMoYpTy32jC48TJC89UxSrWEV m6rnVWMavKGHbgXzniR+4+tEx9ALyZkHdAKOaOYa+5+sJGY+t0AtGn6GyCuM17SDvdH5 yB8h4cZO+GhKDTCEouv3U5NIqsycg5b5+KiLwBo3L1x6Q45yMD/HlhuD5mdHJtwIFcAk RjK4JBIrNsIE1T2xgW5N9pc4DgOoejWO4M/V/KrbEJE+1FtfRkFDh8sXklVmUrJDxZZ2 iguQ== X-Gm-Message-State: AOAM531QfZtCDhTyZ/15/49RexbNqZSQgzYqARRCq8LpsV7nIg3fXXie 3yPQoto/twj/4F5k5r1Ypro= X-Google-Smtp-Source: ABdhPJwk7iW0Yqwn1w6vBgUXg7LByq9z+7jNFQU/jvbMk1qgUi+J+WMm1Z9sGBYUb7ifw8Q/97BoFA== X-Received: by 2002:a17:90b:e8f:: with SMTP id fv15mr10848970pjb.178.1611398445618; Sat, 23 Jan 2021 02:40:45 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:45 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac Date: Sat, 23 Jan 2021 18:39:59 +0800 Message-Id: <20210123104016.17485-9-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per the "Physical Layer Specification Version 8.00" chapter 7.5.2, "Data Read", there is a minimum 8 clock cycles (Nac) after the card response and before data block shows up on the data out line. This applies to both single and multiple block read operations. Current implementation of single block read already satisfies the timing requirement as in the RESPONSE state after all responses are transferred the state remains unchanged. In the next 8 clock cycles it jumps to DATA_START state if data is ready. However we need an explicit state when expanding our support to multiple block read in the future. Let's add a new state PREP_DATA explicitly in the ssi-sd state machine to represent Nac. Note we don't change the single block read state machine to let it jump from RESPONSE state to DATA_START state as that effectively generates a 16 clock cycles Nac, which might not be safe. As the spec says the maximum Nac shall be calculated from several fields encoded in the CSD register, we don't want to bother updating CSD to ensure our Nac is within range to complicate things. Signed-off-by: Bin Meng Acked-by: Philippe Mathieu-Daudé --- Changes in v2: - new patch: add a state representing Nac hw/sd/ssi-sd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 8bccedfab2..5763afeba0 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -39,6 +39,7 @@ typedef enum { SSI_SD_CMDARG, SSI_SD_PREP_RESP, SSI_SD_RESPONSE, + SSI_SD_PREP_DATA, SSI_SD_DATA_START, SSI_SD_DATA_READ, SSI_SD_DATA_CRC16, @@ -194,6 +195,10 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->mode = SSI_SD_CMD; } return 0xff; + case SSI_SD_PREP_DATA: + DPRINTF("Prepare data block (Nac)\n"); + s->mode = SSI_SD_DATA_START; + return 0xff; case SSI_SD_DATA_START: DPRINTF("Start read block\n"); s->mode = SSI_SD_DATA_READ; From patchwork Sat Jan 23 10:40:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08D83C433DB for ; Sat, 23 Jan 2021 10:45:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A5D2522DCC for ; Sat, 23 Jan 2021 10:45:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A5D2522DCC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GQS-0006nK-FD for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:45:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLj-00036U-5q; Sat, 23 Jan 2021 05:40:59 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:36484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLc-00031C-8U; Sat, 23 Jan 2021 05:40:58 -0500 Received: by mail-pf1-x42e.google.com with SMTP id u67so5486630pfb.3; Sat, 23 Jan 2021 02:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c771B4ttrpmQTuPEon8/y7iMjVoswF3wTEbNwRcJGBY=; b=hJfOIDDt1Tu3nSjJ8bm5HeP8aXpkQPsSgms01avoWkV9ycqKaeHul2amTRvhnNWJ88 s2aDMGDPGmy8jEUJL1QW6BKyb+1NsIo/g/GFuVJOCnYRo9yGcYM3V2PQPMQ66iXtgUsR lelNi0ChDheL1naNr/o1cGAQzt+oBWtEQkIsPxNX9yaE61IxFqGDOFNvpey80SZPv7yV M/WLITDZ5Zr7xoEioIqB4sXdJ/kUVAlCy/OnwOtVUDXHmPqKZDhWjGmKZ0cNlrMMZaT4 ABEqJfQ5MNqDWfreo1S3syz/msSODWkPFdR34dVdfNXQVJKI9lr/oDUNX93cHo+I3N12 TcSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c771B4ttrpmQTuPEon8/y7iMjVoswF3wTEbNwRcJGBY=; b=O0W/swq3IGSE/sezAGaXwAMslxBA1jSmpywxdfmElCeSzx5eveFUEAjZyQv1CHw4Yr MD2Rb+yUFUbIiSrDx2wUtfkPVlfYqWKwhpSVq43Y24NusA7oyldWNqfBkkBBd2C1dT2m Xpw1vsyE5IHOJvCg+pjzmYvG2zKAoBp1EzHRiCIu05/nnDP59Mj1u5iZVMFms6oEwY/o hk6P4f87BgXgeHPJhQyWg8XGDVJntBmPm0MhzcXlxpo8XFe0KFbZQ0HIzbQavMmiG3xo D41s/6sKI6dwfND3wPDS3yfxR3jjdZhB7OBUkGPMVCq5rMRKyWbCF5ddexx8aC/WOmJ6 widQ== X-Gm-Message-State: AOAM5335QgbG3v1Dzc9PzZe95EsFF3fWoUQ6b6hB2oyaesF8uDw57D5I R7Mqk4GzOShaBEDA11HW6JZVq49Ry3Ca3A== X-Google-Smtp-Source: ABdhPJyBNrfo04uONZpjKOZHGcc7H+WOHzi6ioeQq40MoIB4FaLQRF8pHGEDJIiboXvqvqplUl7Fbg== X-Received: by 2002:a63:f255:: with SMTP id d21mr9159787pgk.149.1611398448080; Sat, 23 Jan 2021 02:40:48 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:47 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION Date: Sat, 23 Jan 2021 18:40:00 +0800 Message-Id: <20210123104016.17485-10-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This fixes the wrong command index for STOP_TRANSMISSION, the required command to interrupt the multiple block read command, in the old codes. It should be CMD12 (0x4c), not CMD13 (0x4d). Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: - Make this fix a separate patch from the CMD18 support hw/sd/ssi-sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 5763afeba0..9e2f13374a 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -83,7 +83,7 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) ssi_sd_state *s = SSI_SD(dev); /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */ - if (s->mode == SSI_SD_DATA_READ && val == 0x4d) { + if (s->mode == SSI_SD_DATA_READ && val == 0x4c) { s->mode = SSI_SD_CMD; /* There must be at least one byte delay before the card responds. */ s->stopping = 1; From patchwork Sat Jan 23 10:40:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48033C433DB for ; Sat, 23 Jan 2021 10:48:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC1BC22DCC for ; Sat, 23 Jan 2021 10:48:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EC1BC22DCC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38176 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GSq-0001yP-4L for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:48:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLj-00037Y-H6; Sat, 23 Jan 2021 05:40:59 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:41701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLd-00031J-ME; Sat, 23 Jan 2021 05:40:59 -0500 Received: by mail-pg1-x530.google.com with SMTP id i7so5588990pgc.8; Sat, 23 Jan 2021 02:40:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UmirUUOo4XgCFDxKI72dYVTFEGJcAFOI3F2A4yCDIsE=; b=LNw9GtvHw18EE5vAh3D0RUEwbKnkIdsT6mKJCs2fEKUc4jFX/NMt5VkHBwZNqCCoz1 5sgRdCUV0r704Sw/W2jRdbMHVM/fhP3+feSyr2z4CROMp4AYcSWaY3wComf3HSFQaMe8 u6hvrnI0qAugwrpGMF2lB3PbVL7IRIaWerOOh8DMpRzXwg4zSjhAAIwPnb11fnxBYoFn F2lAq4yYK3LlUurOwIBhacisW9/OZVX+/UPd2th27WnXeYXVm2d+H6N9Px9jmUsnaJ5v 7oAj5msiIPA4LiQQkr3ydGk0IpepCL/b65FNd7cBy7ScC/Sra0JOuw1qK8EnAvfbqx7q fypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UmirUUOo4XgCFDxKI72dYVTFEGJcAFOI3F2A4yCDIsE=; b=to6x4U78cYFMkGZKcCGJL23YwLFlU4DLXegtYW1Hytp1y9w6mXjSyGk2wCN6C0ZgSU H+R3mnxYK9bZw07NI/DCtpplMNP0ayT2fgfj0YHkiufx8sujGY6nd1F7u121lHh6H7rO x0peoO+NlRCrB2D62kHEB850dZhVEKfNf3Xmmvz7vPshwSW9cHr0UshmYeL2iRJwFUL6 1lo3jVggV8r9sBqMl5HAet6vS0Suqlysr41XmTcxX2UX4CIS9htrSYKw+atJLety1Fn0 IfoSOTJj61ZLyhf/4vVEzsdhMpvakiFJv35Yb/jBHcTpG6Ps+s9m9S/PotIpBUUM+CPA p3/w== X-Gm-Message-State: AOAM530RPDB8zDL7v8tBwWsmJShvuuabujF1IP1yJFhnHyCrRL10ryAG rOeAZxpk+gd568chN+qc+8EX6w4whKWpjQ== X-Google-Smtp-Source: ABdhPJzyCq25Q/DRU2NyWXeZI41Q2iQ5thb0Uqyf0vCB+jFIx17lRMZU3AhKRthm5pAoS4zOAp/6dg== X-Received: by 2002:a65:6a12:: with SMTP id m18mr3050066pgu.178.1611398450873; Sat, 23 Jan 2021 02:40:50 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:50 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/25] hw/sd: ssi-sd: Support multiple block read Date: Sat, 23 Jan 2021 18:40:01 +0800 Message-Id: <20210123104016.17485-11-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng In the case of a multiple block read operation every transferred block has its suffix of CRC16. Update the state machine logic to handle multiple block read. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- Changes in v2: - Fix 2 typos in the commit message - Add a comment block to explain the CMD12 timing - Catch CMD12 in all of the data read states per the timing requirement hw/sd/ssi-sd.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 9e2f13374a..c1532b004b 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -52,6 +52,7 @@ struct ssi_sd_state { uint8_t cmdarg[4]; uint8_t response[5]; uint16_t crc16; + int32_t read_bytes; int32_t arglen; int32_t response_pos; int32_t stopping; @@ -82,11 +83,26 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) { ssi_sd_state *s = SSI_SD(dev); - /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */ - if (s->mode == SSI_SD_DATA_READ && val == 0x4c) { - s->mode = SSI_SD_CMD; - /* There must be at least one byte delay before the card responds. */ - s->stopping = 1; + /* + * Special case: allow CMD12 (STOP TRANSMISSION) while reading data. + * + * See "Physical Layer Specification Version 8.00" chapter 7.5.2.2, + * to avoid conflict between CMD12 response and next data block, + * timing of CMD12 should be controlled as follows: + * + * - CMD12 issued at the timing that end bit of CMD12 and end bit of + * data block is overlapped + * - CMD12 issued after one clock cycle after host receives a token + * (either Start Block token or Data Error token) + * + * We need to catch CMD12 in all of the data read states. + */ + if (s->mode >= SSI_SD_PREP_DATA && s->mode <= SSI_SD_DATA_CRC16) { + if (val == 0x4c) { + s->mode = SSI_SD_CMD; + /* There must be at least one byte delay before the card responds */ + s->stopping = 1; + } } switch (s->mode) { @@ -206,8 +222,9 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) return 0xfe; case SSI_SD_DATA_READ: val = sdbus_read_byte(&s->sdbus); + s->read_bytes++; s->crc16 = crc_ccitt_false(s->crc16, (uint8_t *)&val, 1); - if (!sdbus_data_ready(&s->sdbus)) { + if (!sdbus_data_ready(&s->sdbus) || s->read_bytes == 512) { DPRINTF("Data read end\n"); s->mode = SSI_SD_DATA_CRC16; } @@ -218,7 +235,12 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->response_pos++; if (s->response_pos == 2) { DPRINTF("CRC16 read end\n"); - s->mode = SSI_SD_CMD; + if (s->read_bytes == 512 && s->cmd != 17) { + s->mode = SSI_SD_PREP_DATA; + } else { + s->mode = SSI_SD_CMD; + } + s->read_bytes = 0; s->response_pos = 0; } return val; @@ -258,6 +280,7 @@ static const VMStateDescription vmstate_ssi_sd = { VMSTATE_UINT8_ARRAY(cmdarg, ssi_sd_state, 4), VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5), VMSTATE_UINT16(crc16, ssi_sd_state), + VMSTATE_INT32(read_bytes, ssi_sd_state), VMSTATE_INT32(arglen, ssi_sd_state), VMSTATE_INT32(response_pos, ssi_sd_state), VMSTATE_INT32(stopping, ssi_sd_state), @@ -310,6 +333,7 @@ static void ssi_sd_reset(DeviceState *dev) memset(s->cmdarg, 0, sizeof(s->cmdarg)); memset(s->response, 0, sizeof(s->response)); s->crc16 = 0; + s->read_bytes = 0; s->arglen = 0; s->response_pos = 0; s->stopping = 0; From patchwork Sat Jan 23 10:40:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17903C433E0 for ; Sat, 23 Jan 2021 10:49:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 895AB23358 for ; Sat, 23 Jan 2021 10:49:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 895AB23358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:45494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GUO-0004vz-IA for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:49:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLl-0003EC-MV; Sat, 23 Jan 2021 05:41:01 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:36942) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLg-00032z-Ij; Sat, 23 Jan 2021 05:41:01 -0500 Received: by mail-pl1-x631.google.com with SMTP id q2so1958868plk.4; Sat, 23 Jan 2021 02:40:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B58xplxCooU/F15C0BemwLKQ+JY8xrgit1LkcRDbVyo=; b=uvu9tZz3bny3rIfJV3MH4SYrF56Q8vDO7r+9qPEA2tobJsP7l+/cLG5muX0X5K5l70 UAeVHPgXzJeD1xKV3e6DFHyL93iRRP/Dz4qyj061wKi0nG0orqgi76M5mD2hq0TPgt+w cQKHcZhEknwklnFdHXarfrdPRvGJndcOaoYwmVbvv1n6MFhcFSYphFy8biufnQR+/iiB bbYKQ33jQmIGWUaExvz+cNdws4D/sMqs9ACetYaiCxDXXdPs/GMTktbjGRnqe+FzFYG9 Ne6nmuWJvQ9nY+NludUctGJ88Aqa/cHG9rx5hdQLWQ60OoFbCXAyKvZ7JRbaZumoa2o8 xvcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B58xplxCooU/F15C0BemwLKQ+JY8xrgit1LkcRDbVyo=; b=YO62NRKudmKlz47EGswZPNaTUrAAoW6K7J1Spa25kV+JvGEbqUWJNs8kHCS7syJe1j Hg2EeDn5GqDtvNpj9cn233ITm6hyAJjNdWXpIWVMigDR/QU/Q7P/oldqW7mzgS/AdOY/ DnpIKPUltb+QbuReGT96fyOP8lA9ZaS67Eb8DLhmdnKgl9F4yZlUDMxSH4kT00ypBHPr B6LRulRyNyMZabZQ72yAl5dvA1aijNhb/pzQz82CeUoR80KA8lFa+ZXo5hZl/a/H8tHx u50A5MjB88hF4yxFdU55y5GTKq5NY+FbYpPWMoO9cPvdrKLgGYLBqk8ZGvvkj5/d8+U/ ZRNw== X-Gm-Message-State: AOAM532zXSfvAfqzpNHOrdh4ImHaiHKAEiXdjwuOs0OBQ13uRSjSYZZL 3Mj+/qHamB9ijMQjxoEo2t0= X-Google-Smtp-Source: ABdhPJxCM/i2LBRaGZlqrHPRdlnMCt39qiH4FWLFueXc4MiszGAtmH8muhP5xe7LoI8SCHZaY+fVdQ== X-Received: by 2002:a17:90a:3b04:: with SMTP id d4mr10433113pjc.48.1611398453341; Sat, 23 Jan 2021 02:40:53 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:52 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer Date: Sat, 23 Jan 2021 18:40:02 +0800 Message-Id: <20210123104016.17485-12-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the codes use hardcoded numbers (0xff/0xfe) for the dummy value and block start token. Replace them with macros. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: - Move multiple write token definitions out of this patch hw/sd/ssi-sd.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index c1532b004b..75e76cf87a 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -79,6 +79,12 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) #define SSI_SDR_ADDRESS_ERROR 0x2000 #define SSI_SDR_PARAMETER_ERROR 0x4000 +/* single block read/write, multiple block read */ +#define SSI_TOKEN_SINGLE 0xfe + +/* dummy value - don't care */ +#define SSI_DUMMY 0xff + static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) { ssi_sd_state *s = SSI_SD(dev); @@ -107,14 +113,14 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) switch (s->mode) { case SSI_SD_CMD: - if (val == 0xff) { + if (val == SSI_DUMMY) { DPRINTF("NULL command\n"); - return 0xff; + return SSI_DUMMY; } s->cmd = val & 0x3f; s->mode = SSI_SD_CMDARG; s->arglen = 0; - return 0xff; + return SSI_DUMMY; case SSI_SD_CMDARG: if (s->arglen == 4) { SDRequest request; @@ -189,15 +195,15 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) } else { s->cmdarg[s->arglen++] = val; } - return 0xff; + return SSI_DUMMY; case SSI_SD_PREP_RESP: DPRINTF("Prepare card response (Ncr)\n"); s->mode = SSI_SD_RESPONSE; - return 0xff; + return SSI_DUMMY; case SSI_SD_RESPONSE: if (s->stopping) { s->stopping = 0; - return 0xff; + return SSI_DUMMY; } if (s->response_pos < s->arglen) { DPRINTF("Response 0x%02x\n", s->response[s->response_pos]); @@ -210,16 +216,16 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) DPRINTF("End of command\n"); s->mode = SSI_SD_CMD; } - return 0xff; + return SSI_DUMMY; case SSI_SD_PREP_DATA: DPRINTF("Prepare data block (Nac)\n"); s->mode = SSI_SD_DATA_START; - return 0xff; + return SSI_DUMMY; case SSI_SD_DATA_START: DPRINTF("Start read block\n"); s->mode = SSI_SD_DATA_READ; s->response_pos = 0; - return 0xfe; + return SSI_TOKEN_SINGLE; case SSI_SD_DATA_READ: val = sdbus_read_byte(&s->sdbus); s->read_bytes++; @@ -246,7 +252,7 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) return val; } /* Should never happen. */ - return 0xff; + return SSI_DUMMY; } static int ssi_sd_post_load(void *opaque, int version_id) From patchwork Sat Jan 23 10:40:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAE9EC433DB for ; Sat, 23 Jan 2021 10:58:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33586233EA for ; Sat, 23 Jan 2021 10:58:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 33586233EA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GcX-0008JT-BC for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:58:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLl-0003Cz-98; Sat, 23 Jan 2021 05:41:01 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:41695) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLi-000337-Bx; Sat, 23 Jan 2021 05:41:00 -0500 Received: by mail-pg1-x529.google.com with SMTP id i7so5589077pgc.8; Sat, 23 Jan 2021 02:40:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nsH7YqqMFOy7hdEwufb73pDrnrkdgOcAfpojWeKqt3c=; b=iq9CZHAuRbn3CNUxdjBj0JW2zddyl4gEvYpdANKGGun9fBaKP/W9RmDQL0zTdpt9cH YQo/Cs+3BV1c+mwNXXeROmI7C7+pEeof+4KciUwJMywYVS05627WL77uR9JDbRUsOFxs B/dAdL93Eit+nuyEYFbdyEBZgk9qjrQfyu5VduiJM5Vnn5O+0bcA4ozE8599+mR40Wi2 oW0hH7b3qLUftA1fzBO/Z0qKfsweHT9AbZOAj+stlmI+CaP//MrDX+SZR8WMDY6s/aoc qL/RVc6PSAW/456ZiwanEXbovU2K23e7yxg2G9qnOxHTuZnwXRZOGyZ6Y/AFERzcCmjn m+MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nsH7YqqMFOy7hdEwufb73pDrnrkdgOcAfpojWeKqt3c=; b=hoijNytXeJD0FqYMlMfsp0/iVMoAXQvZ5NI2UVPw1oD4v2v2U1f4ZTB1+V9gHiYpk4 4+tfwIMrAGp4rjbYqL4b69LOvt/qsfTjNzvGeWJQ3hCHbJQ0qzT6tZ69Nt/h65JPYNMX ifcUPmy90TcClHBEtUyLm8Tz1JL5e+CA85xCW+GBZDxggCoQEx4Q0lurA1D0/G7vPnbS OhkKscYy8bnFnmy5NQZFci8bs24hVhrkxQN/UVLiiS4tzneQ80qojgyzELj620/q1cAV IzNnUdVnkj+ERFobJ00fkesjrv7pCq3zpXN61Rv9XwY5/0rbB74KJ4dvOiaSpeUyQWYj wfBQ== X-Gm-Message-State: AOAM531W4TnJLvfb70Lz1x2OF6qhJFlOvaGH0FwdFMm83AmFF7IGHkHf 21beyspsx1hrkmq29uX/tas= X-Google-Smtp-Source: ABdhPJzjZvrCPWUixEsMBEZfIGr4VS3yRKEtrb+cgdpHbwAPu3wBIjMuZ3NgcHcJOd3ipcm4350SNg== X-Received: by 2002:aa7:909a:0:b029:1bc:22d3:9e58 with SMTP id i26-20020aa7909a0000b02901bc22d39e58mr9321746pfa.29.1611398455832; Sat, 23 Jan 2021 02:40:55 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:55 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/25] hw/sd: sd: Remove duplicated codes in single/multiple block read/write Date: Sat, 23 Jan 2021 18:40:03 +0800 Message-Id: <20210123104016.17485-13-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The single block read (CMD17) codes are the same as the multiple block read (CMD18). Merge them into one. The same applies to single block write (CMD24) and multiple block write (CMD25). Signed-off-by: Bin Meng Acked-by: Alistair Francis --- (no changes since v1) hw/sd/sd.c | 47 ----------------------------------------------- 1 file changed, 47 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index b3952514fe..09753359bb 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1181,24 +1181,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) break; case 17: /* CMD17: READ_SINGLE_BLOCK */ - switch (sd->state) { - case sd_transfer_state: - - if (addr + sd->blk_len > sd->size) { - sd->card_status |= ADDRESS_ERROR; - return sd_r1; - } - - sd->state = sd_sendingdata_state; - sd->data_start = addr; - sd->data_offset = 0; - return sd_r1; - - default: - break; - } - break; - case 18: /* CMD18: READ_MULTIPLE_BLOCK */ switch (sd->state) { case sd_transfer_state: @@ -1245,35 +1227,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) /* Block write commands (Class 4) */ case 24: /* CMD24: WRITE_SINGLE_BLOCK */ - switch (sd->state) { - case sd_transfer_state: - /* Writing in SPI mode not implemented. */ - if (sd->spi) - break; - - if (addr + sd->blk_len > sd->size) { - sd->card_status |= ADDRESS_ERROR; - return sd_r1; - } - - sd->state = sd_receivingdata_state; - sd->data_start = addr; - sd->data_offset = 0; - sd->blk_written = 0; - - if (sd_wp_addr(sd, sd->data_start)) { - sd->card_status |= WP_VIOLATION; - } - if (sd->csd[14] & 0x30) { - sd->card_status |= WP_VIOLATION; - } - return sd_r1; - - default: - break; - } - break; - case 25: /* CMD25: WRITE_MULTIPLE_BLOCK */ switch (sd->state) { case sd_transfer_state: From patchwork Sat Jan 23 10:40:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36BC1C433E0 for ; Sat, 23 Jan 2021 10:48:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD9EF22DCC for ; Sat, 23 Jan 2021 10:48:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD9EF22DCC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:37904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GSn-0001rs-SF for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:48:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLm-0003HW-Ns; Sat, 23 Jan 2021 05:41:02 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:41855) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLl-000346-2p; Sat, 23 Jan 2021 05:41:02 -0500 Received: by mail-pl1-x62c.google.com with SMTP id h15so2235825pli.8; Sat, 23 Jan 2021 02:40:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8S+2pTjCNFYHJQpKubpfhi88hOIid6hv5Akr1gRnwjQ=; b=R999AIAk0j7suqvcy9wmiLFpq0GCTm6BcvAH6SWsdsJIpwBvUea20yCngEmT9HBxNe o0I67bpVWN4MECuqsuJG+L5+9mj1ldzIyl6Kfk/Mbymyu0jmF/oazgCodcd0jpFn927J Bc2zG+R1Xu+hCM7yO9HXWMpqSZfKkld93DFZBpbaCqLfcXdjzVs/tggZxT/B9/7Sp88l 5agFhkYEVCj2xpJQ39w0wQ4E42VFO1feZi47x6dywSbsR6T5geMAYdCrWRHmGxUjWrBA W5p4nAS/guzkuEZjsjapyjMVlgB6C/CpfUEBkOAE/QGpI+8dx+QDb1s5yIn/vDA8rDoF 55bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8S+2pTjCNFYHJQpKubpfhi88hOIid6hv5Akr1gRnwjQ=; b=WcxasobpiYS3dmwJ/hcFuba/hpnYDCsUmStVMzETek1sm9iqSyAIIc88MUSqirqg7u nDqT8fvbvRUcI9lKu9YkfFadyCTQVyMFq17Lr1aOGhESOJYszcf1jkythjPjJLLiA+eg jFVlzwODFHQz0KL8uGyRbk/O63zFhtVusUhhCIC0E0Q1XT/OT1+Az/Q+rA37hqzMWY2c I1wRzxQrGBJmvFga9n3Jwnub91MmhoPmErbFdsilBOCS4zGx8znI5vC4Dvp1CIogu8r4 NUcxurX6g0OhDdEmBFpRdcfS+YwNt5WBnwhcKGWcLzzdiC2DecA7v4cAdUPMywItykIb 5otQ== X-Gm-Message-State: AOAM532ha77ZDgkpKovpZvlEkv/e6GU/MRoxzgHCXK2P9Pv9TPYejXwN 5zg5vFRrSnaNYlVJkiflcj8= X-Google-Smtp-Source: ABdhPJwQxDxjuMF8XXvqjMGZT1JXiN5j6Q0S/gTnOUYjzQzawTAqsuGSk9j6b2v6lwXxm4q/kxr3sg== X-Received: by 2002:a17:90b:948:: with SMTP id dw8mr3408377pjb.72.1611398458950; Sat, 23 Jan 2021 02:40:58 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:40:57 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/25] hw/sd: sd: Allow single/multiple block write for SPI mode Date: Sat, 23 Jan 2021 18:40:04 +0800 Message-Id: <20210123104016.17485-14-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the single/multiple block write in SPI mode is blocked by sd_normal_command(). Remove the limitation. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- (no changes since v1) hw/sd/sd.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 09753359bb..946036d87c 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1230,9 +1230,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) case 25: /* CMD25: WRITE_MULTIPLE_BLOCK */ switch (sd->state) { case sd_transfer_state: - /* Writing in SPI mode not implemented. */ - if (sd->spi) - break; if (addr + sd->blk_len > sd->size) { sd->card_status |= ADDRESS_ERROR; From patchwork Sat Jan 23 10:40:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 935F2C433DB for ; Sat, 23 Jan 2021 10:51:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C1D723358 for ; Sat, 23 Jan 2021 10:51:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C1D723358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GVS-00068T-5Q for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:51:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLu-0003KU-QP; Sat, 23 Jan 2021 05:41:10 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:35396) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLn-00035Q-9G; Sat, 23 Jan 2021 05:41:10 -0500 Received: by mail-pl1-x632.google.com with SMTP id g3so4739871plp.2; Sat, 23 Jan 2021 02:41:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m6KHipQBQa0fN3miiY5k4Y+3eHUcfw7rpFhSKZm/tds=; b=Qtoc4qQ8YXN1BdojGY1NXIEnL7ljeJ5PgCw6anx0qCwKxHlElK7DoY54h1yRcNY305 8o4BmYQ6n66d5SGB2zS7YfsumWqcwnSp8uqMvIZJQ1ywp4r0bJessGxXheUDGMpo4Oby U7GJW/eSpRHZ67754ChsyOMdcmIG5Fg75bLtzrE5nMTOYRwm7iKQ5tAIT6FJl+l4S/LV Z8x3qNCHVe/B2JrLvFZ8SkjIG0106C+NuQuPCiaZdOJOk916j6yfcPntK+P69fb1ZS5V 6CRQGxYU95XwFpbItxAFoEfEv94+JfC2t7HoOIaNA6CHjzjjQQLQABkbWe9rapnHPius Fzgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m6KHipQBQa0fN3miiY5k4Y+3eHUcfw7rpFhSKZm/tds=; b=mXa75SnhbzRYIxPqYw1c/Kf+8euNZGJqAY0Xt9kskwNof3xwPFJX2PajrtC9lFSU8M CcGkPGHbfl0VEEHHmPkSwi+KOrRu56CDTrrShy1W9YJbitKvB+iQnNRkNfA7X3QQhF4+ HhOtnGvG6xiesBUs/HFatFI0lMDiRtq+wqUk7Xk7jSPpK2ImNEoI3oYdPFgLBemPT8B1 T+egSG3CMts90se7u6TkMenpCITp9m5/KLmhx+HSyuD/wE6F8+mV8R/CT5/v5vw4gfia 9sVwKwUvzSLG7CJZj9Appiw1A1eJQapa8i735bqMdjAL5iQ/t/tcLf/LmHMd0Dk+7lb7 SCEg== X-Gm-Message-State: AOAM532JOBGesFZbsJD2vNxn5Px/AYJbANpxxMlZLXLLqfFCK0vsPFKM p4CqD673Gc4Z1jJq8b5rPTQ= X-Google-Smtp-Source: ABdhPJzXvsdMGCS7+vhAAODPWuCtCJ+rOekr/vjuN4mTRyVQXE4xC5RYBpW8sClUDINB0h1MxqaJoQ== X-Received: by 2002:a17:90a:2ec1:: with SMTP id h1mr10837736pjs.18.1611398461404; Sat, 23 Jan 2021 02:41:01 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:01 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/25] hw/sd: sd.h: Cosmetic change of using spaces Date: Sat, 23 Jan 2021 18:40:05 +0800 Message-Id: <20210123104016.17485-15-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng QEMU coding convention prefers spaces over tabs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: - Correct the "coding" typo in the commit message include/hw/sd/sd.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h index 59d108d453..05ef9b73e5 100644 --- a/include/hw/sd/sd.h +++ b/include/hw/sd/sd.h @@ -33,27 +33,27 @@ #include "hw/qdev-core.h" #include "qom/object.h" -#define OUT_OF_RANGE (1 << 31) -#define ADDRESS_ERROR (1 << 30) -#define BLOCK_LEN_ERROR (1 << 29) -#define ERASE_SEQ_ERROR (1 << 28) -#define ERASE_PARAM (1 << 27) -#define WP_VIOLATION (1 << 26) -#define CARD_IS_LOCKED (1 << 25) -#define LOCK_UNLOCK_FAILED (1 << 24) -#define COM_CRC_ERROR (1 << 23) -#define ILLEGAL_COMMAND (1 << 22) -#define CARD_ECC_FAILED (1 << 21) -#define CC_ERROR (1 << 20) -#define SD_ERROR (1 << 19) -#define CID_CSD_OVERWRITE (1 << 16) -#define WP_ERASE_SKIP (1 << 15) -#define CARD_ECC_DISABLED (1 << 14) -#define ERASE_RESET (1 << 13) -#define CURRENT_STATE (7 << 9) -#define READY_FOR_DATA (1 << 8) -#define APP_CMD (1 << 5) -#define AKE_SEQ_ERROR (1 << 3) +#define OUT_OF_RANGE (1 << 31) +#define ADDRESS_ERROR (1 << 30) +#define BLOCK_LEN_ERROR (1 << 29) +#define ERASE_SEQ_ERROR (1 << 28) +#define ERASE_PARAM (1 << 27) +#define WP_VIOLATION (1 << 26) +#define CARD_IS_LOCKED (1 << 25) +#define LOCK_UNLOCK_FAILED (1 << 24) +#define COM_CRC_ERROR (1 << 23) +#define ILLEGAL_COMMAND (1 << 22) +#define CARD_ECC_FAILED (1 << 21) +#define CC_ERROR (1 << 20) +#define SD_ERROR (1 << 19) +#define CID_CSD_OVERWRITE (1 << 16) +#define WP_ERASE_SKIP (1 << 15) +#define CARD_ECC_DISABLED (1 << 14) +#define ERASE_RESET (1 << 13) +#define CURRENT_STATE (7 << 9) +#define READY_FOR_DATA (1 << 8) +#define APP_CMD (1 << 5) +#define AKE_SEQ_ERROR (1 << 3) enum SDPhySpecificationVersion { SD_PHY_SPECv1_10_VERS = 1, From patchwork Sat Jan 23 10:40:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5C8DC433DB for ; Sat, 23 Jan 2021 10:52:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C68D23358 for ; Sat, 23 Jan 2021 10:52:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C68D23358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GXK-0001CQ-Ai for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:52:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GLy-0003NC-RD; Sat, 23 Jan 2021 05:41:16 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:52471) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLt-00036w-9d; Sat, 23 Jan 2021 05:41:14 -0500 Received: by mail-pj1-x1036.google.com with SMTP id kx7so5394484pjb.2; Sat, 23 Jan 2021 02:41:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jl5yWzJQLZ/3iIKrZa05bEzfjs6tF2YDXsKTDBgwC7Q=; b=ghN7kRi9kaGtFlK+cuALRIlCAqzEcjLivXdPo+cGChUd1p46iS9i5VzfOfp74Qv3r0 AhFwm+34hVff18neio7j6oJw916qvw0P3GTirXtKshhNwXBG7vAXRxClZZUuYicOQ1f5 g/L3HZXa038S/2S1XzjrmuKmW2bthyl66Hzj2ApJSI6yfqn0uGeNAQrDEbS1Cqxg4FJW ub/ntjLuUsVoDBX7zAjqDWo4VT24xDhZB9boUU/4uoSpQZ9IA/aCgc5G7brOyoLBS2ah yM/UXiM5kuJO53ND9ptMjGjTo7RoLDexDKofLwWzDTkrxIMcTMzIRcxDmarz8Z++02AB hxbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jl5yWzJQLZ/3iIKrZa05bEzfjs6tF2YDXsKTDBgwC7Q=; b=Web+adlQ0FLZ56g2ub0eZ3R0T0MhGD15FOGCT7ct2IntN165RgFldpc053TRl1lZyR jeCxd8/GTNyIpyPVuzT/q+ZAZ/f6ljVqaT7xtR3W2QTZmz6/lvH6MUTKwVT8y2CGz4TB BVaCtOjD3bMAlcztpbzKSbgedC5PMdKVzerQagIxODvGDX1aKnSJPO+haIjYz3vx4tDD CWNujkS3xwFBxkBg4PmjmRKlfBX4BzKHMhxk8kgP6E87PGy9oISCIeZ3f+069Ka8LS2t VxtL5LbS9Qji//jdwypj1e7UHCvukZpnEAKPmOZuOoWeqgoVvcJLd1EOEoKx00Ch/ThV MG8Q== X-Gm-Message-State: AOAM532MTZ7QGn0v+vR+Kjl5t7THxnwP1ao8NrTstDbfP4pVQNA43xKF gLfTTZ37wS4MnvsqfAVLPoE= X-Google-Smtp-Source: ABdhPJxJUqnWbMsNdRNK2hRDx5ZrDhCwdR8icitT1fPvXvqhewZSA8FJ2Y+0rbcX/yiVgljq/hVcHQ== X-Received: by 2002:a17:90b:1a87:: with SMTP id ng7mr1236459pjb.211.1611398463901; Sat, 23 Jan 2021 02:41:03 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:03 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/25] hw/sd: Introduce receive_ready() callback Date: Sat, 23 Jan 2021 18:40:06 +0800 Message-Id: <20210123104016.17485-16-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present there is a data_ready() callback for the SD data read path. Let's add a receive_ready() for the SD data write path. Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v1) include/hw/sd/sd.h | 2 ++ hw/sd/core.c | 13 +++++++++++++ hw/sd/sd.c | 6 ++++++ 3 files changed, 21 insertions(+) diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h index 05ef9b73e5..47360ba4ee 100644 --- a/include/hw/sd/sd.h +++ b/include/hw/sd/sd.h @@ -116,6 +116,7 @@ struct SDCardClass { * Return: byte value read */ uint8_t (*read_byte)(SDState *sd); + bool (*receive_ready)(SDState *sd); bool (*data_ready)(SDState *sd); void (*set_voltage)(SDState *sd, uint16_t millivolts); uint8_t (*get_dat_lines)(SDState *sd); @@ -187,6 +188,7 @@ void sdbus_write_data(SDBus *sdbus, const void *buf, size_t length); * Read multiple bytes of data on the data lines of a SD bus. */ void sdbus_read_data(SDBus *sdbus, void *buf, size_t length); +bool sdbus_receive_ready(SDBus *sd); bool sdbus_data_ready(SDBus *sd); bool sdbus_get_inserted(SDBus *sd); bool sdbus_get_readonly(SDBus *sd); diff --git a/hw/sd/core.c b/hw/sd/core.c index 08c93b5903..30ee62c510 100644 --- a/hw/sd/core.c +++ b/hw/sd/core.c @@ -160,6 +160,19 @@ void sdbus_read_data(SDBus *sdbus, void *buf, size_t length) } } +bool sdbus_receive_ready(SDBus *sdbus) +{ + SDState *card = get_card(sdbus); + + if (card) { + SDCardClass *sc = SD_CARD_GET_CLASS(card); + + return sc->receive_ready(card); + } + + return false; +} + bool sdbus_data_ready(SDBus *sdbus) { SDState *card = get_card(sdbus); diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 946036d87c..c99c0e93bb 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2037,6 +2037,11 @@ uint8_t sd_read_byte(SDState *sd) return ret; } +static bool sd_receive_ready(SDState *sd) +{ + return sd->state == sd_receivingdata_state; +} + static bool sd_data_ready(SDState *sd) { return sd->state == sd_sendingdata_state; @@ -2147,6 +2152,7 @@ static void sd_class_init(ObjectClass *klass, void *data) sc->do_command = sd_do_command; sc->write_byte = sd_write_byte; sc->read_byte = sd_read_byte; + sc->receive_ready = sd_receive_ready; sc->data_ready = sd_data_ready; sc->enable = sd_enable; sc->get_inserted = sd_get_inserted; From patchwork Sat Jan 23 10:40:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E998AC43381 for ; Sat, 23 Jan 2021 11:02:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9058623437 for ; Sat, 23 Jan 2021 11:02:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9058623437 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:51440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3Gg3-0002oU-Gp for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 06:01:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GME-0003T2-I0; Sat, 23 Jan 2021 05:41:33 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:46474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLv-000373-6S; Sat, 23 Jan 2021 05:41:23 -0500 Received: by mail-pl1-x62e.google.com with SMTP id u11so4696559plg.13; Sat, 23 Jan 2021 02:41:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vMwNDhJzrNnSIXeq99hgPETYS9nHQnoJ/lsGNQKjl7o=; b=vAI90+uwkyzo2TYV1wvomtQHmfqHHOOKuB4LWWwQznOie+wU0RWBOntQ+uLne6RQ+G K/ab8eaWxpEVpM5kAR9yzAJVWKqKOqQXr6fri+6i/9CUXn/L6AqvEhAwuWFDDkvxU/kC 3jbguS7amRH6HEgqpEtInI8yV2Khzv9zL68WoUxL4fUQp5n2HlwCaNAf5+Bl1OmMqnVy s6geM66MHxX6yl7mzCS7QS3T5bycJ7q+iFeo1i5RKw3jXOavRHsdyFAF6McrVURXyFFl 7Z3iOPGdFumC6tAxKUDJhxuITTKIvhB28AZVV9gyzN5S7fWvJRnC3a8XB25+iRMefBSh 2S9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vMwNDhJzrNnSIXeq99hgPETYS9nHQnoJ/lsGNQKjl7o=; b=O15PsXbhA5JUdLoFrPTn0LBAb1fbCBQVAqSrzuIQUeNWFZBSZkrECDudBQWO/utguE uaqmHNZgU9Dt1/lWq/MLjZW5dXtxiSBwts1/PTzYcYcpM5jIo0fdNG1a75a04IbnRV6y hjFLlet7mimF2fC7YNQCSdFKMo6+G1jMReOClg2IrNsv3PrVeDoelTBJxCu9mgGqGmBz eZn6RNtYZbUebrzANCKQQVzbfx9Frqsv2JMh0e8HzcMci9TILgVuUXerAxMG5yH/zgNC 03Vtt4InQLFbimPn/e2T2nrLiGLfzQK7oIbdfchal5bxCk0he2AXBCrdUdi0ozyvogTK 3eAA== X-Gm-Message-State: AOAM533+B19/gTtZP3XKmti16IDRS6oBOyRLxrkPm+Bce4YvZkdgRhMW WAE0bD/7olbMnaoqKnUVRe4= X-Google-Smtp-Source: ABdhPJwZWEaCFEbOKJjbxN+lhiPTuX0P6CzH8k0lDuOf6RGXRAzrkoRhgrv9yX5CNU42pFdcmXQhZQ== X-Received: by 2002:a17:90a:7e82:: with SMTP id j2mr1850999pjl.217.1611398466523; Sat, 23 Jan 2021 02:41:06 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:05 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/25] hw/sd: ssi-sd: Support single block write Date: Sat, 23 Jan 2021 18:40:07 +0800 Message-Id: <20210123104016.17485-17-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add 2 more states for the block write operation. The SPI host needs to send a data start token to start the transfer, and the data block written to the card will be acknowledged by a data response token. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- Changes in v2: - Correct the "token" typo in the commit message - Add 'write_bytes' in vmstate_ssi_sd hw/sd/ssi-sd.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 75e76cf87a..240cfd919c 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -43,6 +43,8 @@ typedef enum { SSI_SD_DATA_START, SSI_SD_DATA_READ, SSI_SD_DATA_CRC16, + SSI_SD_DATA_WRITE, + SSI_SD_SKIP_CRC16, } ssi_sd_mode; struct ssi_sd_state { @@ -53,6 +55,7 @@ struct ssi_sd_state { uint8_t response[5]; uint16_t crc16; int32_t read_bytes; + int32_t write_bytes; int32_t arglen; int32_t response_pos; int32_t stopping; @@ -85,6 +88,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) /* dummy value - don't care */ #define SSI_DUMMY 0xff +/* data accepted */ +#define DATA_RESPONSE_ACCEPTED 0x05 + static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) { ssi_sd_state *s = SSI_SD(dev); @@ -113,10 +119,17 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) switch (s->mode) { case SSI_SD_CMD: - if (val == SSI_DUMMY) { + switch (val) { + case SSI_DUMMY: DPRINTF("NULL command\n"); return SSI_DUMMY; + break; + case SSI_TOKEN_SINGLE: + DPRINTF("Start write block\n"); + s->mode = SSI_SD_DATA_WRITE; + return SSI_DUMMY; } + s->cmd = val & 0x3f; s->mode = SSI_SD_CMDARG; s->arglen = 0; @@ -250,6 +263,27 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->response_pos = 0; } return val; + case SSI_SD_DATA_WRITE: + sdbus_write_byte(&s->sdbus, val); + s->write_bytes++; + if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) { + DPRINTF("Data write end\n"); + s->mode = SSI_SD_SKIP_CRC16; + s->response_pos = 0; + } + return val; + case SSI_SD_SKIP_CRC16: + /* we don't verify the crc16 */ + s->response_pos++; + if (s->response_pos == 2) { + DPRINTF("CRC16 receive end\n"); + s->mode = SSI_SD_RESPONSE; + s->write_bytes = 0; + s->arglen = 1; + s->response[0] = DATA_RESPONSE_ACCEPTED; + s->response_pos = 0; + } + return SSI_DUMMY; } /* Should never happen. */ return SSI_DUMMY; @@ -287,6 +321,7 @@ static const VMStateDescription vmstate_ssi_sd = { VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5), VMSTATE_UINT16(crc16, ssi_sd_state), VMSTATE_INT32(read_bytes, ssi_sd_state), + VMSTATE_INT32(write_bytes, ssi_sd_state), VMSTATE_INT32(arglen, ssi_sd_state), VMSTATE_INT32(response_pos, ssi_sd_state), VMSTATE_INT32(stopping, ssi_sd_state), @@ -340,6 +375,7 @@ static void ssi_sd_reset(DeviceState *dev) memset(s->response, 0, sizeof(s->response)); s->crc16 = 0; s->read_bytes = 0; + s->write_bytes = 0; s->arglen = 0; s->response_pos = 0; s->stopping = 0; From patchwork Sat Jan 23 10:40:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A734C433E0 for ; Sat, 23 Jan 2021 10:54:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D6A4233E2 for ; Sat, 23 Jan 2021 10:54:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9D6A4233E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GZ3-0003vv-PP for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:54:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51242) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GM1-0003QW-Nx; Sat, 23 Jan 2021 05:41:22 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:39077) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLv-00037b-6v; Sat, 23 Jan 2021 05:41:17 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 30so5596690pgr.6; Sat, 23 Jan 2021 02:41:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y2zcJszCz5lIVVf0OMd5bXgiApimd2gt80gUBOZlMWw=; b=EU0FlqEUNiNuAhc/YUBwsa5JH1DjGXIJ/+U6ExlYc2BHS6hyPpeg8cibNfNiqyOYg5 gjX3kVAlcqprWP0mVAieN4/VfnByfsd4tsj8iTJqH8LUKsVxG8Pde7dC6LQIy+iATyYw K1Azg2bP8Yd4QTU9KXQVDA7vjXyeEsbU9Y1L7/PaichgGkpmTbiqJKLlNocsrHd3qzl0 gdoS3soPuey6vkLEbTVLiNWJNix8dJ5ZKJq00/q0k0DhHJn8B4YjjRmpi6ye1l8IAXe7 S5CfEEneEWuCaF7YtfAxWOyjwSq8wJuE2BqVYfm3/7/Dh/VHGzApugURJeQMKrW5GX44 cBkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y2zcJszCz5lIVVf0OMd5bXgiApimd2gt80gUBOZlMWw=; b=MyIfEYLynl2V+cpyRUmp29UOdYUatlFxBqwFVRvV3FDBHQYUbY/0IV9scFGkzmuLf1 ipwhHQ3RccbEr8u4KsGpY5Gv/PizOJ9d6cB1IHKlkuU3rkNSjYSRc7ZauhmF3AKru1C4 kKaj/dmq4rz5Y6E+clH/Bf0PV7b6FZqFZYh4b1ThuobobuUYogxJlfjZ5jIsw6MilE/3 biMBkmtiSnbmmo4CeewU7mPSQRDpgr0PtXU3wsPlp28bNOB5D8g+Ql4VvGhMQv9n9X2f iWKVvMkodgqso+SJUDexK1pBrkw1k9SU/YuRS7BoV7ZwiTv0tiZZIFOb2PsBZRFOQF38 glBA== X-Gm-Message-State: AOAM530dEMfwvOw5HPBZLldkDJVq5LB47t9dv2j82SZIq4u88Xr5kpCa 533/rRRm7ezqmyFiewJSIwCaZKKa5Ym+Lw== X-Google-Smtp-Source: ABdhPJy+125FbsoUN05cwCPyYrWWmxbnmr7O7tOsA2SvAxsk4MRHD/AGUDsdGluR06DwEg6C2aD7MA== X-Received: by 2002:a63:6b42:: with SMTP id g63mr9091323pgc.107.1611398468967; Sat, 23 Jan 2021 02:41:08 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:08 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write Date: Sat, 23 Jan 2021 18:40:08 +0800 Message-Id: <20210123104016.17485-18-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng For a multiple block write operation, each block begins with a multi write start token. Unlike the SD mode that the multiple block write ends when receiving a STOP_TRAN command (CMD12), a special stop tran token is used to signal the card. Emulating this by manually sending a CMD12 to the SD card core, to bring it out of the receiving data state. Signed-off-by: Bin Meng Acked-by: Alistair Francis --- Changes in v2: - Correct the "token" typo in the commit message - Introduce multiple write token definitions in this patch hw/sd/ssi-sd.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 240cfd919c..ee4fbc3dfe 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -82,6 +82,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) #define SSI_SDR_ADDRESS_ERROR 0x2000 #define SSI_SDR_PARAMETER_ERROR 0x4000 +/* multiple block write */ +#define SSI_TOKEN_MULTI_WRITE 0xfc +/* terminate multiple block write */ +#define SSI_TOKEN_STOP_TRAN 0xfd /* single block read/write, multiple block read */ #define SSI_TOKEN_SINGLE 0xfe @@ -94,6 +98,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) { ssi_sd_state *s = SSI_SD(dev); + SDRequest request; + uint8_t longresp[16]; /* * Special case: allow CMD12 (STOP TRANSMISSION) while reading data. @@ -125,9 +131,31 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) return SSI_DUMMY; break; case SSI_TOKEN_SINGLE: + case SSI_TOKEN_MULTI_WRITE: DPRINTF("Start write block\n"); s->mode = SSI_SD_DATA_WRITE; return SSI_DUMMY; + case SSI_TOKEN_STOP_TRAN: + DPRINTF("Stop multiple write\n"); + + /* manually issue cmd12 to stop the transfer */ + request.cmd = 12; + request.arg = 0; + s->arglen = sdbus_do_command(&s->sdbus, &request, longresp); + if (s->arglen <= 0) { + s->arglen = 1; + /* a zero value indicates the card is busy */ + s->response[0] = 0; + DPRINTF("SD card busy\n"); + } else { + s->arglen = 1; + /* a non-zero value indicates the card is ready */ + s->response[0] = SSI_DUMMY; + } + + s->mode = SSI_SD_RESPONSE; + s->response_pos = 0; + return SSI_DUMMY; } s->cmd = val & 0x3f; @@ -136,8 +164,6 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) return SSI_DUMMY; case SSI_SD_CMDARG: if (s->arglen == 4) { - SDRequest request; - uint8_t longresp[16]; /* FIXME: Check CRC. */ request.cmd = s->cmd; request.arg = ldl_be_p(s->cmdarg); From patchwork Sat Jan 23 10:40:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24529C433E6 for ; Sat, 23 Jan 2021 10:52:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFFB823358 for ; Sat, 23 Jan 2021 10:52:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AFFB823358 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:55522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GX9-0000oW-TQ for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:52:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GM0-0003PA-NC; Sat, 23 Jan 2021 05:41:17 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:37877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GLx-00039f-An; Sat, 23 Jan 2021 05:41:16 -0500 Received: by mail-pf1-x433.google.com with SMTP id 11so5489947pfu.4; Sat, 23 Jan 2021 02:41:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZpmpBaqxwIW+T8AlgiMlZ3ja19EBYtyu/2rATDhidIU=; b=hw6+db9Cx1xhe2/NH3ajs3DIYY1ST3Iw4fAbNVxaxzp4I8fdedHKzf2WImgum3ZBjy 6TV10i65i4CZSQv7Maig3dnZWPXeWKRPyfW0H5XjD3fTMu9mkXYBaOThpTZwd0ZonPAB A2ecXCqakVMenSB5IZR0sZhWiHPdbQQU4RALTtglotDibIyujkcnfmWoQSoOt0UTYy31 NVOG6yuWNfmg8NfoMhPSeX3+euFcijPpB36iyxyelMnSARb6ehMRxdp1egOWBYlOlpN4 TWbxdrp+zBexSDyiUVdURbNvxb8lpEXa7ZG7XkzK1qNDpbFI/sX3yHSBMXVKJ97kb7ID yXLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZpmpBaqxwIW+T8AlgiMlZ3ja19EBYtyu/2rATDhidIU=; b=Z74HKv7SxqCyJM0kbJiWC/g3AwCyhDMrifAz/Xwz0WsdYtB+ygAvdUp5eUicH/ZCE+ W58RZY+1qiG5S52UoQ9lua5f3ET7xpYF6iQPKTA4CrwaP1zw8nIBGBYIcGhoqep2hLHh 3IftTlcwuetXRS+88Ih4fZuLfa5FVb/lMRDQTYphM4MUmAHJAZhQpgF6Tn4UOH3qdmLc b1WWANsgPCsM3XtXrrPmzoTtHhIwaNk5MtSvXK9E1D8CdVUn++B3Yd/yqKyC6N+auBhr PdJQKchM0/rkOoIgHAAG9XWDVvB0qAi038yMVcj2nuTlDsoXFgUtc5aHsYxAmHij7EEy N2og== X-Gm-Message-State: AOAM532ZpEr6V53/F51yBK8pBusf5UAFlYu/AAt161LDLq5te9PLebug kYKuuD/FgrApKVnC3ztvEjYISLtgeRWtrQ== X-Google-Smtp-Source: ABdhPJwCg94C8xeDUN0SD6LlzdudIauiznYGVJmIKdwoT3tosIQqVn1VREO/JXkt/Er87Vck+eg/sw== X-Received: by 2002:a62:7f8a:0:b029:1bc:8a1a:95b1 with SMTP id a132-20020a627f8a0000b02901bc8a1a95b1mr9411401pfd.73.1611398471408; Sat, 23 Jan 2021 02:41:11 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:11 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription Date: Sat, 23 Jan 2021 18:40:09 +0800 Message-Id: <20210123104016.17485-19-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng With all these fixes and improvements, there is no way for the VMStateDescription to keep backward compatibility. We will have to bump up version ids. The s->mode check in the post_load() hook is also updated. Signed-off-by: Bin Meng --- Changes in v2: - new patch: bump up version ids of VMStateDescription hw/sd/ssi-sd.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index ee4fbc3dfe..0c507f3ec5 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -4,6 +4,11 @@ * Copyright (c) 2007-2009 CodeSourcery. * Written by Paul Brook * + * Copyright (c) 2021 Wind River Systems, Inc. + * Improved by Bin Meng + * + * Validated with U-Boot v2021.01 and Linux v5.10 mmc_spi driver + * * This code is licensed under the GNU GPL v2. * * Contributions after 2012-01-13 are licensed under the terms of the @@ -319,7 +324,7 @@ static int ssi_sd_post_load(void *opaque, int version_id) { ssi_sd_state *s = (ssi_sd_state *)opaque; - if (s->mode > SSI_SD_DATA_READ) { + if (s->mode > SSI_SD_SKIP_CRC16) { return -EINVAL; } if (s->mode == SSI_SD_CMDARG && @@ -337,8 +342,8 @@ static int ssi_sd_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_ssi_sd = { .name = "ssi_sd", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .post_load = ssi_sd_post_load, .fields = (VMStateField []) { VMSTATE_UINT32(mode, ssi_sd_state), From patchwork Sat Jan 23 10:40:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A14E1C433E0 for ; Sat, 23 Jan 2021 10:51:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FA2E23381 for ; Sat, 23 Jan 2021 10:51:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FA2E23381 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GVS-00067h-58 for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:51:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GM6-0003Rm-LO; Sat, 23 Jan 2021 05:41:27 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:38667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GM0-0003C1-FN; Sat, 23 Jan 2021 05:41:22 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d4so4732272plh.5; Sat, 23 Jan 2021 02:41:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pRs6fw4syraDIfWHfkirOfF/LqfuKed1GwSHTU6tXmM=; b=TvPtMMAdT78IV8pwruzP8+XlqRihVM46eePgAsWGkGAu1L+84LbRdD0fZEhYSAaUwK slD5CgkuwnGePZn/ntes2JSjvu0vuaSbUS6l7VAwH+NsvwoZXNUiJyhPi6786mFhSjmu d7PyGAdfAV2KKLVgUPjgnvZDomDSOBZxvBoYIdYmQENQ8S/wvM6UvC5PE8IXpBo6h5wl 9qekMdre4xQDE/kRTDvEG6K5B+kLc1zlNLzqXzJjr4P5/StcNcPObfeNJuadZ7Obhs+X CIch49EprF34o7rdhWYZfGUs32FBfyrx+xExeoMDyMg2dpTcx4qDSCsLIlY/YiDM3ir3 UsVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pRs6fw4syraDIfWHfkirOfF/LqfuKed1GwSHTU6tXmM=; b=tvD9VW4y/cVUJVkCpVpku48QtL9MZ1W+YxVOmqafhFTlz1uJBIQ60noCBDeIWUkveI T0ccgqcJk8cqSafps+LtcxmTboAgfuoqFHAmEJznY3FYHOb2pK3OsdJPp6v7BsMGtG2w yXYt+3tt6+/XVNT1Jl1IVapjgFxb+mEt1I9Am01LN2Rdsn+gvdUp3c5cY7hlEU3+ev9X 5UGrrJxttQPdDi2hfsrJwG8DYXK3sBJyacLjYJVA9XLGNV8lyUzi5c5ir+GYWdwa926R QtKNpRpKabtTuA/e4LCPqFJPjXfb7H5T1JWYARRXAFGEW0z/q+Vd0ln9IlzQwZ6z0TTt fP2A== X-Gm-Message-State: AOAM532lzk5a2UE5N6Ysv1ZeAFqNE8DOieBFbFXMNIJUJh0347ydtwfO NQDiqq9k4rdNsU1F07ViFsA= X-Google-Smtp-Source: ABdhPJxmKZdm9BmmQxznWpECv0woLSwhSWWT6zP1A3cMwjxYth0kGpj0C5olmpFy9/InF8spZ1RAxg== X-Received: by 2002:a17:90a:5b06:: with SMTP id o6mr10748800pji.49.1611398474089; Sat, 23 Jan 2021 02:41:14 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:13 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/25] hw/ssi: Add SiFive SPI controller support Date: Sat, 23 Jan 2021 18:40:10 +0800 Message-Id: <20210123104016.17485-20-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng --- Changes in v2: - Log guest error when trying to write reserved registers - Log guest error when trying to access out-of-bounds registers - log guest error when writing to reserved bits for chip select registers and watermark registers - Log unimplemented warning when trying to write direct-map flash interface registers - Add test tx fifo full logic in sifive_spi_read(), hence remove setting the tx fifo full flag in sifive_spi_write(). - Populate register with their default value include/hw/ssi/sifive_spi.h | 47 +++++ hw/ssi/sifive_spi.c | 367 ++++++++++++++++++++++++++++++++++++ hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + 4 files changed, 419 insertions(+) create mode 100644 include/hw/ssi/sifive_spi.h create mode 100644 hw/ssi/sifive_spi.c diff --git a/include/hw/ssi/sifive_spi.h b/include/hw/ssi/sifive_spi.h new file mode 100644 index 0000000000..47d0d6a47c --- /dev/null +++ b/include/hw/ssi/sifive_spi.h @@ -0,0 +1,47 @@ +/* + * QEMU model of the SiFive SPI Controller + * + * Copyright (c) 2021 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_SPI_H +#define HW_SIFIVE_SPI_H + +#define SIFIVE_SPI_REG_NUM (0x78 / 4) + +#define TYPE_SIFIVE_SPI "sifive.spi" +#define SIFIVE_SPI(obj) OBJECT_CHECK(SiFiveSPIState, (obj), TYPE_SIFIVE_SPI) + +typedef struct SiFiveSPIState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t num_cs; + qemu_irq *cs_lines; + + SSIBus *spi; + + Fifo8 tx_fifo; + Fifo8 rx_fifo; + + uint32_t regs[SIFIVE_SPI_REG_NUM]; +} SiFiveSPIState; + +#endif /* HW_SIFIVE_SPI_H */ diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c new file mode 100644 index 0000000000..61504336ad --- /dev/null +++ b/hw/ssi/sifive_spi.c @@ -0,0 +1,367 @@ +/* + * QEMU model of the SiFive SPI Controller + * + * Copyright (c) 2021 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/ssi/ssi.h" +#include "sysemu/sysemu.h" +#include "qemu/fifo8.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/ssi/sifive_spi.h" + +#define R_SCKDIV (0x00 / 4) +#define R_SCKMODE (0x04 / 4) +#define R_CSID (0x10 / 4) +#define R_CSDEF (0x14 / 4) +#define R_CSMODE (0x18 / 4) +#define R_DELAY0 (0x28 / 4) +#define R_DELAY1 (0x2C / 4) +#define R_FMT (0x40 / 4) +#define R_TXDATA (0x48 / 4) +#define R_RXDATA (0x4C / 4) +#define R_TXMARK (0x50 / 4) +#define R_RXMARK (0x54 / 4) +#define R_FCTRL (0x60 / 4) +#define R_FFMT (0x64 / 4) +#define R_IE (0x70 / 4) +#define R_IP (0x74 / 4) + +#define FMT_DIR (1 << 3) + +#define TXDATA_FULL (1 << 31) +#define RXDATA_EMPTY (1 << 31) + +#define IE_TXWM (1 << 0) +#define IE_RXWM (1 << 1) + +#define IP_TXWM (1 << 0) +#define IP_RXWM (1 << 1) + +#define FIFO_CAPACITY 8 + +static void sifive_spi_txfifo_reset(SiFiveSPIState *s) +{ + fifo8_reset(&s->tx_fifo); + + s->regs[R_TXDATA] &= ~TXDATA_FULL; + s->regs[R_IP] &= ~IP_TXWM; +} + +static void sifive_spi_rxfifo_reset(SiFiveSPIState *s) +{ + fifo8_reset(&s->rx_fifo); + + s->regs[R_RXDATA] |= RXDATA_EMPTY; + s->regs[R_IP] &= ~IP_RXWM; +} + +static void sifive_spi_update_cs(SiFiveSPIState *s) +{ + int i; + + for (i = 0; i < s->num_cs; i++) { + if (s->regs[R_CSDEF] & (1 << i)) { + qemu_set_irq(s->cs_lines[i], !(s->regs[R_CSMODE])); + } + } +} + +static void sifive_spi_update_irq(SiFiveSPIState *s) +{ + int level; + + if (fifo8_num_used(&s->tx_fifo) < s->regs[R_TXMARK]) { + s->regs[R_IP] |= IP_TXWM; + } else { + s->regs[R_IP] &= ~IP_TXWM; + } + + if (fifo8_num_used(&s->rx_fifo) > s->regs[R_RXMARK]) { + s->regs[R_IP] |= IP_RXWM; + } else { + s->regs[R_IP] &= ~IP_RXWM; + } + + level = s->regs[R_IP] & s->regs[R_IE] ? 1 : 0; + qemu_set_irq(s->irq, level); +} + +static void sifive_spi_reset(DeviceState *d) +{ + SiFiveSPIState *s = SIFIVE_SPI(d); + + memset(s->regs, 0, sizeof(s->regs)); + + /* The reset value is high for all implemented CS pins */ + s->regs[R_CSDEF] = (1 << s->num_cs) - 1; + + /* Populate register with their default value */ + s->regs[R_SCKDIV] = 0x03; + s->regs[R_DELAY0] = 0x1001; + s->regs[R_DELAY1] = 0x01; + + sifive_spi_txfifo_reset(s); + sifive_spi_rxfifo_reset(s); + + sifive_spi_update_cs(s); + sifive_spi_update_irq(s); +} + +static void sifive_spi_flush_txfifo(SiFiveSPIState *s) +{ + uint8_t tx; + uint8_t rx; + + while (!fifo8_is_empty(&s->tx_fifo)) { + tx = fifo8_pop(&s->tx_fifo); + s->regs[R_TXDATA] &= ~TXDATA_FULL; + + rx = ssi_transfer(s->spi, tx); + + if (fifo8_is_full(&s->rx_fifo)) { + s->regs[R_IP] |= IP_RXWM; + } else { + if (!(s->regs[R_FMT] & FMT_DIR)) { + fifo8_push(&s->rx_fifo, rx); + s->regs[R_RXDATA] &= ~RXDATA_EMPTY; + + if (fifo8_is_full(&s->rx_fifo)) { + s->regs[R_IP] |= IP_RXWM; + } + } + } + } +} + +static bool sifive_spi_is_bad_reg(hwaddr addr, bool allow_reserved) +{ + bool bad; + + switch (addr) { + /* reserved offsets */ + case 0x08: + case 0x0C: + case 0x1C: + case 0x20: + case 0x24: + case 0x30: + case 0x34: + case 0x38: + case 0x3C: + case 0x44: + case 0x58: + case 0x5C: + case 0x68: + case 0x6C: + bad = allow_reserved ? false : true; + break; + default: + bad = false; + } + + if (addr >= (SIFIVE_SPI_REG_NUM << 2)) { + bad = true; + } + + return bad; +} + +static uint64_t sifive_spi_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveSPIState *s = opaque; + uint32_t r; + + if (sifive_spi_is_bad_reg(addr, true)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read at address 0x%" + HWADDR_PRIx "\n", __func__, addr); + return 0; + } + + addr >>= 2; + switch (addr) { + case R_TXDATA: + if (fifo8_is_full(&s->tx_fifo)) { + return TXDATA_FULL; + } + r = 0; + break; + + case R_RXDATA: + if (fifo8_is_empty(&s->rx_fifo)) { + return RXDATA_EMPTY; + } + r = fifo8_pop(&s->rx_fifo); + break; + + default: + r = s->regs[addr]; + break; + } + + sifive_spi_update_irq(s); + + return r; +} + +static void sifive_spi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveSPIState *s = opaque; + uint32_t value = val64; + + if (sifive_spi_is_bad_reg(addr, false)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write at addr=0x%" + HWADDR_PRIx " value=0x%x\n", __func__, addr, value); + return; + } + + addr >>= 2; + switch (addr) { + case R_CSID: + if (value >= s->num_cs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csid %d\n", + __func__, value); + } else { + s->regs[R_CSID] = value; + sifive_spi_update_cs(s); + } + break; + + case R_CSDEF: + if (value >= (1 << s->num_cs)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csdef %x\n", + __func__, value); + } else { + s->regs[R_CSDEF] = value; + } + break; + + case R_CSMODE: + if (value > 3) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csmode %x\n", + __func__, value); + } else { + s->regs[R_CSMODE] = value; + sifive_spi_update_cs(s); + } + break; + + case R_TXDATA: + if (!fifo8_is_full(&s->tx_fifo)) { + fifo8_push(&s->tx_fifo, (uint8_t)value); + sifive_spi_flush_txfifo(s); + } + break; + + case R_RXDATA: + case R_IP: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write to read-only reigster 0x%" + HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, value); + break; + + case R_TXMARK: + case R_RXMARK: + if (value >= FIFO_CAPACITY) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid watermark %d\n", + __func__, value); + } else { + s->regs[addr] = value; + } + break; + + case R_FCTRL: + case R_FFMT: + qemu_log_mask(LOG_UNIMP, + "%s: direct-map flash interface unimplemented\n", + __func__); + break; + + default: + s->regs[addr] = value; + break; + } + + sifive_spi_update_irq(s); +} + +static const MemoryRegionOps sifive_spi_ops = { + .read = sifive_spi_read, + .write = sifive_spi_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void sifive_spi_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + SiFiveSPIState *s = SIFIVE_SPI(dev); + int i; + + s->spi = ssi_create_bus(dev, "spi"); + sysbus_init_irq(sbd, &s->irq); + + s->cs_lines = g_new0(qemu_irq, s->num_cs); + for (i = 0; i < s->num_cs; i++) { + sysbus_init_irq(sbd, &s->cs_lines[i]); + } + + memory_region_init_io(&s->mmio, OBJECT(s), &sifive_spi_ops, s, + TYPE_SIFIVE_SPI, 0x1000); + sysbus_init_mmio(sbd, &s->mmio); + + fifo8_create(&s->tx_fifo, FIFO_CAPACITY); + fifo8_create(&s->rx_fifo, FIFO_CAPACITY); +} + +static Property sifive_spi_properties[] = { + DEFINE_PROP_UINT32("num-cs", SiFiveSPIState, num_cs, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, sifive_spi_properties); + dc->reset = sifive_spi_reset; + dc->realize = sifive_spi_realize; +} + +static const TypeInfo sifive_spi_info = { + .name = TYPE_SIFIVE_SPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveSPIState), + .class_init = sifive_spi_class_init, +}; + +static void sifive_spi_register_types(void) +{ + type_register_static(&sifive_spi_info); +} + +type_init(sifive_spi_register_types) diff --git a/hw/ssi/Kconfig b/hw/ssi/Kconfig index 9e54a0c8dd..7d90a02181 100644 --- a/hw/ssi/Kconfig +++ b/hw/ssi/Kconfig @@ -2,6 +2,10 @@ config PL022 bool select SSI +config SIFIVE_SPI + bool + select SSI + config SSI bool diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index dee00c0da6..3d6bc82ab1 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -2,6 +2,7 @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi.c')) softmmu_ss.add(when: 'CONFIG_XILINX_SPI', if_true: files('xilinx_spi.c')) From patchwork Sat Jan 23 10:40:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DCF0C433E0 for ; Sat, 23 Jan 2021 10:57:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A5881233E2 for ; Sat, 23 Jan 2021 10:57:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A5881233E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3Gbz-0007ZN-IA for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:57:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GMS-0003UO-Sb; Sat, 23 Jan 2021 05:41:45 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:46481) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GM2-0003E6-CE; Sat, 23 Jan 2021 05:41:33 -0500 Received: by mail-pl1-x635.google.com with SMTP id u11so4696684plg.13; Sat, 23 Jan 2021 02:41:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3ks4evfVetiWrSqpIJZMkw/VBfcoyQkIYry7CxkotKo=; b=jwTFZPisiy3JbKXtfZgh77Y2dwD6pzwmdKctlCYj4jASmkgrok9wNoww6rgAoJLg+C mDepuHKHVkOq53S5I4Dijm2dmcyVXPQFTHlCcznlVWKwMsToW+ucFqcDpocK8WfkrIi1 Qdo+8QK7JC62azct06hyFxoAdXwGVjEgbUFSuwMesqthSFOR00/DpTcw/ITw4CfLPbig h/iWfrbcmRkxBlYZ1svbRX4Xf7/enZSvpQWYqKcqCV/K2RADSPF16u3sDq1oI/kGLHo1 IDXrRqTYxXFdlkInTWRcWfHTCmXj1btusTjMIZdZGal48Lb98N23c4scnd/MJRcWrR8D kZYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3ks4evfVetiWrSqpIJZMkw/VBfcoyQkIYry7CxkotKo=; b=HyMXGDQO86pl71k8EWR4bgVYkQRUQ1XrkP15NxgDaFhE9vEdET95OCMYAoDUsqPoxi TSJnW/14royLVeghIcou6roKh831z+YmO1E+++S7NeS2tvpftwa0YIahCOI+5PhVjsiR yvLloyQqxirlE1VztUPrETF9eqUvWFRnBwf1GQ3ovB8pdmR+JyYooPYldM2dAL6N+aCb zvk49We10KFl4m3R3ktboogrR1dn7ZJixrYefV9hCeOFk1Ysji/bbkmFkYeIQOS4JALi 9bHvbDbjfLqdqD2k9JdGTaxvj3V4oCgNSfL7yZzhiK9s9mTv4lrWxI427Xd2X4B00g6K vXiQ== X-Gm-Message-State: AOAM530XsqilCNOTkT/WBb4QusyFmClphAoq2MZ67o1x4LECpdfeH1sO r9sMP/9lPK/QChaSdHaAb6E= X-Google-Smtp-Source: ABdhPJxjcmJl4cKaHRGeqc6tEkPaKqENq4mRztrXt7XUAANNlQUR47yWIak0zv1Q+czQgxmuSQGJbQ== X-Received: by 2002:a17:90b:881:: with SMTP id bj1mr230769pjb.150.1611398476570; Sat, 23 Jan 2021 02:41:16 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:16 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/25] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Date: Sat, 23 Jan 2021 18:40:11 +0800 Message-Id: <20210123104016.17485-21-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - Correct the "connects" typo in the commit message - Mention in the commit message that property does not populate the second group which represents the memory mapped address of the SPI flash include/hw/riscv/sifive_u.h | 4 +++ hw/riscv/sifive_u.c | 52 +++++++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 2 ++ 3 files changed, 58 insertions(+) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a9f7b4a084..8824b7c031 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -26,6 +26,7 @@ #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" +#include "hw/ssi/sifive_spi.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -45,6 +46,7 @@ typedef struct SiFiveUSoCState { SIFIVEGPIOState gpio; SiFiveUOTPState otp; SiFivePDMAState dma; + SiFiveSPIState spi0; CadenceGEMState gem; uint32_t serial; @@ -82,6 +84,7 @@ enum { SIFIVE_U_DEV_UART0, SIFIVE_U_DEV_UART1, SIFIVE_U_DEV_GPIO, + SIFIVE_U_DEV_QSPI0, SIFIVE_U_DEV_OTP, SIFIVE_U_DEV_DMC, SIFIVE_U_DEV_FLASH0, @@ -120,6 +123,7 @@ enum { SIFIVE_U_PDMA_IRQ5 = 28, SIFIVE_U_PDMA_IRQ6 = 29, SIFIVE_U_PDMA_IRQ7 = 30, + SIFIVE_U_QSPI0_IRQ = 51, SIFIVE_U_GEM_IRQ = 0x35 }; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 59b61cea01..43a0e983d2 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -15,6 +15,7 @@ * 5) OTP (One-Time Programmable) memory with stored serial number * 6) GEM (Gigabit Ethernet Controller) and management block * 7) DMA (Direct Memory Access Controller) + * 8) SPI0 connected to an SPI flash * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -44,6 +45,7 @@ #include "hw/char/serial.h" #include "hw/cpu/cluster.h" #include "hw/misc/unimp.h" +#include "hw/ssi/ssi.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" @@ -74,6 +76,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, @@ -342,6 +345,32 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, "sifive,fu540-c000-ccache"); g_free(nodename); + nodename = g_strdup_printf("/soc/spi@%lx", + (long)memmap[SIFIVE_U_DEV_QSPI0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, + 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); + g_free(nodename); + + nodename = g_strdup_printf("/soc/spi@%lx/flash@0", + (long)memmap[SIFIVE_U_DEV_QSPI0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); + qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); + qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); + qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); + g_free(nodename); + phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_DEV_GEM].base); @@ -439,6 +468,9 @@ static void sifive_u_machine_init(MachineState *machine) int i; uint32_t fdt_load_addr; uint64_t kernel_entry; + DriveInfo *dinfo; + DeviceState *flash_dev; + qemu_irq flash_cs; /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); @@ -571,6 +603,19 @@ static void sifive_u_machine_init(MachineState *machine) riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); + + /* Connect an SPI flash to SPI0 */ + flash_dev = qdev_new("is25wp256"); + dinfo = drive_get_next(IF_MTD); + if (dinfo) { + qdev_prop_set_drive_err(flash_dev, "drive", + blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); + + flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); } static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) @@ -680,6 +725,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); } static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -827,6 +873,12 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) create_unimplemented_device("riscv.sifive.u.l2cc", memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); + + sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, + memmap[SIFIVE_U_DEV_QSPI0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); } static Property sifive_u_soc_props[] = { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index facb0cbacc..6330297b4e 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -52,9 +52,11 @@ config SIFIVE_U select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_PLIC + select SIFIVE_SPI select SIFIVE_UART select SIFIVE_U_OTP select SIFIVE_U_PRCI + select SSI_M25P80 select UNIMP config SPIKE From patchwork Sat Jan 23 10:40:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83B25C433E0 for ; Sat, 23 Jan 2021 11:04:30 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B84C23437 for ; Sat, 23 Jan 2021 11:04:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B84C23437 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GiS-0004pB-Vx for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 06:04:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51356) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GMT-0003Uc-6X; Sat, 23 Jan 2021 05:41:45 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:56250) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GM6-0003GM-WA; Sat, 23 Jan 2021 05:41:44 -0500 Received: by mail-pj1-x102e.google.com with SMTP id j12so5373654pjy.5; Sat, 23 Jan 2021 02:41:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CRMA1MnKqvkEHxIrGAmR2UJfAUJXEXBwFdwyTK+WES4=; b=e4k5d/c6deZ3njIB3BjZgDjIRwtCNs6c703I6n5go6PQrNjCyfErxYHuRuKXbK6bNm pUJ1/3PaBE/h7D08NtCr2+PGA7BuEKCwEARZw4VOYu+Y6aG2wtuvnTxtWkT5vEbzF6bg zLdFl19akAR0/Nbt0Ad5w8gOKxO/LYztiAJjLIQ1XA0HLXNKOQJxkRpL7WU2kSn+ynju L7dSiR+8q/BJZZvTBMYNWcKjaO7Sf/vEFrKEfAgLepgWuuZHbCdC3e+lyvbV4A1fRjOe NG8aLOUjF3KItr3gew+1W9qBVc/3i4FJ7fnOe5uP0N/jcFTV1vw52cPhX86SHTpgViUM vnNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CRMA1MnKqvkEHxIrGAmR2UJfAUJXEXBwFdwyTK+WES4=; b=HyE1vmeB/NjtTZQ9lq9gx2ZF3dlHwjviOs/UhxJa/dj9gnnSMCB7A/HIyNHYAv3QlR iTmdQvjQHldJyXBe06jcKfGSDErcMgBK7ncSuGCZmGvz790KyR3I0tI/ih5ROFklk9sr 98fb3xt7NCkrwW0Djlllhhv6LSWlfCqHjhwPGRcbD4dtknWjd+RG36eP0KeHo0F5DXCD CuDs4up/wGitTXvWK8Apxp4s2PTvqlYsC9uvYjUs7d2BgzVZtB/OnxusrlDVKTkQYP/R D2VWtyDvuO2lu1rq0Jg3VIzR+TO1U43h0nZauOlXZQ+G7aHTJDZlLr5dxI3JNshTxTNV 56TA== X-Gm-Message-State: AOAM5316UMMApcqWvJddQvVcy3F3V11aUyeg8MOcwsYXSuwKkUCOTlCb wdBmRuEQe8obSW9/KEOgnTg= X-Google-Smtp-Source: ABdhPJyMiB5nJXdRXXoKjtSl301IW4Wmk7HkVxCrN2N92mFxrW0O75gYQNIpzaVMsxzsALt2a22HbQ== X-Received: by 2002:a17:90a:2947:: with SMTP id x7mr22923pjf.157.1611398479078; Sat, 23 Jan 2021 02:41:19 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:18 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/25] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Date: Sat, 23 Jan 2021 18:40:12 +0800 Message-Id: <20210123104016.17485-22-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - Correct the "connects" typo in the commit message include/hw/riscv/sifive_u.h | 3 +++ hw/riscv/sifive_u.c | 43 +++++++++++++++++++++++++++++++++++-- hw/riscv/Kconfig | 1 + 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 8824b7c031..de1464a2ce 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -47,6 +47,7 @@ typedef struct SiFiveUSoCState { SiFiveUOTPState otp; SiFivePDMAState dma; SiFiveSPIState spi0; + SiFiveSPIState spi2; CadenceGEMState gem; uint32_t serial; @@ -85,6 +86,7 @@ enum { SIFIVE_U_DEV_UART1, SIFIVE_U_DEV_GPIO, SIFIVE_U_DEV_QSPI0, + SIFIVE_U_DEV_QSPI2, SIFIVE_U_DEV_OTP, SIFIVE_U_DEV_DMC, SIFIVE_U_DEV_FLASH0, @@ -99,6 +101,7 @@ enum { SIFIVE_U_L2CC_IRQ2 = 3, SIFIVE_U_UART0_IRQ = 4, SIFIVE_U_UART1_IRQ = 5, + SIFIVE_U_QSPI2_IRQ = 6, SIFIVE_U_GPIO_IRQ0 = 7, SIFIVE_U_GPIO_IRQ1 = 8, SIFIVE_U_GPIO_IRQ2 = 9, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 43a0e983d2..6c1158a848 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -16,6 +16,7 @@ * 6) GEM (Gigabit Ethernet Controller) and management block * 7) DMA (Direct Memory Access Controller) * 8) SPI0 connected to an SPI flash + * 9) SPI2 connected to an SD card * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -77,6 +78,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, + [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, @@ -345,6 +347,31 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, "sifive,fu540-c000-ccache"); g_free(nodename); + nodename = g_strdup_printf("/soc/spi@%lx", + (long)memmap[SIFIVE_U_DEV_QSPI2].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, + 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); + g_free(nodename); + + nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", + (long)memmap[SIFIVE_U_DEV_QSPI2].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); + qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); + qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); + g_free(nodename); + nodename = g_strdup_printf("/soc/spi@%lx", (long)memmap[SIFIVE_U_DEV_QSPI0].base); qemu_fdt_add_subnode(fdt, nodename); @@ -469,8 +496,8 @@ static void sifive_u_machine_init(MachineState *machine) uint32_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; - DeviceState *flash_dev; - qemu_irq flash_cs; + DeviceState *flash_dev, *sd_dev; + qemu_irq flash_cs, sd_cs; /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); @@ -616,6 +643,12 @@ static void sifive_u_machine_init(MachineState *machine) flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); + + /* Connect an SD card to SPI2 */ + sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); + + sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); } static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) @@ -726,6 +759,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); + object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); } static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -879,6 +913,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_DEV_QSPI0].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); + sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, + memmap[SIFIVE_U_DEV_QSPI2].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); } static Property sifive_u_soc_props[] = { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 6330297b4e..d139074b02 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -57,6 +57,7 @@ config SIFIVE_U select SIFIVE_U_OTP select SIFIVE_U_PRCI select SSI_M25P80 + select SSI_SD select UNIMP config SPIKE From patchwork Sat Jan 23 10:40:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2DB3C433DB for ; Sat, 23 Jan 2021 11:00:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 31D3F233FC for ; Sat, 23 Jan 2021 11:00:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 31D3F233FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3Ge9-0001QH-WC for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 06:00:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GMT-0003Ua-5Y; Sat, 23 Jan 2021 05:41:45 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:32948) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GMC-0003GR-Fs; Sat, 23 Jan 2021 05:41:42 -0500 Received: by mail-pl1-x632.google.com with SMTP id b8so4748725plx.0; Sat, 23 Jan 2021 02:41:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XV11gAa0FiYpl9jGReeHl+vRsCJUXpPRsTFXVz7CXvo=; b=QwTY8Ad5O/zS8wQdKHR/N+7oA7I8mFomf2xaVS8qBUHQ9rBQVoXQ+rgGVW21IG1+XU LtNpTKh/kQkjOBL9gKSMxmikqdMT6OUfoiYKNyVAL83OLm618w9sl0MgvRW5RP0goKsi LhYuKnPToEbyA71xhml9rAovLHX7RPDZAiDSebb3hAbeI4PoualqTqINgZD9WPCrJD5t VaxvGVpTofZNgns0LEgLgyfvxn2bYo3cG9cR8DHkbYOqs1864PSbvef0n4KwgPfkco2S c2RRwXLdK9qQSBgXRjgdTeM7G8+Vb4kJZ4DpxQQZp/EW6XzA3Zq/Up35bQpi8FPTqpiZ nsXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XV11gAa0FiYpl9jGReeHl+vRsCJUXpPRsTFXVz7CXvo=; b=QmHBOOfdDloNsFBvy//vL7XdF6Mll4Bh6zCZ/sYxOGpIrZ9+OFGCD6+SawsQCt6OE5 MnLgQmPHQYvihAAyVNyGheksIT84BagfhkVoeJ0U50m4oruhGNcusGKnNZjDaIQ73aki 0N6zvLQUDfiJSec3F5QCCdVoMFNfN28MxMJ6/hjPbiEkSbk0FoVfnvogZT2QPLNY2hk0 v3Y5ufnmkvNPepL2ehHvKj0LpuWm7GGUhM8ZuiPDqg3SZiL8E3m7XOMDYH9P0U4IjP6X TXS1vRZReYU+/1+EktVlJu9WeHjSa1ltYJuTDQBcXAVUFn1lZ9UJttce31nbU7+zenPN slEQ== X-Gm-Message-State: AOAM532s4nUc8VOXj46w9fitBVYehFtlQsvBNFD0GYqFB6VVa/x1m3FF uFxft0glKluQbzJI1uWJ73o= X-Google-Smtp-Source: ABdhPJziT0EZAq03NnMq6ZjN7KRaYxg9QP8bL5mJzV2BgKsnmWZCTKyt/Z9zihITDFpBh5NqHqKpxA== X-Received: by 2002:a17:90a:c291:: with SMTP id f17mr10553810pjt.62.1611398481546; Sat, 23 Jan 2021 02:41:21 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:21 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Date: Sat, 23 Jan 2021 18:40:13 +0800 Message-Id: <20210123104016.17485-23-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng All other peripherals' IRQs are in the format of decimal value. Change SIFIVE_U_GEM_IRQ to be consistent. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/sifive_u.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index de1464a2ce..2656b39808 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -127,7 +127,7 @@ enum { SIFIVE_U_PDMA_IRQ6 = 29, SIFIVE_U_PDMA_IRQ7 = 30, SIFIVE_U_QSPI0_IRQ = 51, - SIFIVE_U_GEM_IRQ = 0x35 + SIFIVE_U_GEM_IRQ = 53 }; enum { From patchwork Sat Jan 23 10:40:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4503C433E0 for ; Sat, 23 Jan 2021 10:57:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80FA0233E2 for ; Sat, 23 Jan 2021 10:57:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 80FA0233E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3Gbe-0006oL-Ls for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:57:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GMT-0003UZ-5X; Sat, 23 Jan 2021 05:41:45 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:50389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GMC-0003Gh-PK; Sat, 23 Jan 2021 05:41:43 -0500 Received: by mail-pj1-x102d.google.com with SMTP id md11so5399893pjb.0; Sat, 23 Jan 2021 02:41:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gk6VLOJ8dC9W0TNqig3ksBlOBksYube8P0MfFHo64eg=; b=oRAcgiHsJqFqvZE5q1SwDXLHphKwyCGzHTI4Dv9Ic8KUU91z8pD8flSAia+gvOoFCm /rxrPBbmOikHrk3BGNCmaEC3IK0GBRC8TrgJgH5xM0LdqZdyPmb/SGEOZ7DL1n81X7Wi LVP1T3DCW5jn8EnR6VGncBTC9r86Hzn8jETy8IXFzW93+VyKCC5Oy6jaN/LkL7on0IAe IN6ea724kciW11C/7GxRJBxEkvmWS656cGvCSma3Gkx3dkV/h20/bRHLXaO7+z9qmjlt s0DLiw/oI5N1MSXTGT+3+x+ry2P0BsIhZhdnlmdhDkwVKVTIO/cN/kSMG0yYIl1H/Stc VzCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gk6VLOJ8dC9W0TNqig3ksBlOBksYube8P0MfFHo64eg=; b=aY8FT5xkfWq5G2G8vtcGYu/+VjCepq05iXuHuMFQnrt9VvDrlgs4HSY+/o5wd/2yMf YE7h6RUImzfjR18y4XHvf5pSvF/YB8pIAuD3XjrUpyHSoDkPbVZ/GE0KkiBl069/HHLM MUm2xUBGcPGMlv9o/ZrOrNnEa9ztPr+z4sr0njt5/Nq7QmnXVbdDcCuzInLSsrgPHkVA R4mUf7UhiZC3BpdBkkOB4nW9UUkMC5qbKPUhhPo6/TXl4WowtkmQ21QilKO2tvFZ1vry +WPYyUuPq4gcJTzWu4JyccEUMlOSuqGOigDNURLG8GytqXWHZLN4P69gu836jlyV3+jm UhkQ== X-Gm-Message-State: AOAM5307A0G4mOumB4TKvaxs3YyuXU0fW/Xs3c34jsewiT/8F3pMW1Hj +9r8Jz7QYD9yHviMQew2lOk= X-Google-Smtp-Source: ABdhPJxVZrVQ66aD2+emLqn96NuKY8q5E6uGxCZ3n1OeJAqxMroMNSpcSVNEW1XdbeSv6xYskJ11lA== X-Received: by 2002:a17:90b:e8f:: with SMTP id fv15mr10851243pjb.178.1611398484099; Sat, 23 Jan 2021 02:41:24 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:23 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 23/25] docs/system: Sort targets in alphabetical order Date: Sat, 23 Jan 2021 18:40:14 +0800 Message-Id: <20210123104016.17485-24-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/targets.rst | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 560783644d..564cea9a9b 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -7,16 +7,21 @@ various targets are mentioned in the following sections. Contents: +.. + This table of contents should be kept sorted alphabetically + by the title text of each file, which isn't the same ordering + as an alphabetical sort by filename. + .. toctree:: - target-i386 + target-arm + target-avr + target-m68k + target-mips target-ppc + target-rx + target-s390x target-sparc target-sparc64 - target-mips - target-arm - target-m68k + target-i386 target-xtensa - target-s390x - target-rx - target-avr From patchwork Sat Jan 23 10:40:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAEAFC433E6 for ; Sat, 23 Jan 2021 10:54:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7864C233E2 for ; Sat, 23 Jan 2021 10:54:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7864C233E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3GZ4-0003wq-39 for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 05:54:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GMT-0003UX-6E; Sat, 23 Jan 2021 05:41:45 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:40781) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GME-0003Hv-6V; Sat, 23 Jan 2021 05:41:43 -0500 Received: by mail-pf1-x429.google.com with SMTP id i63so5468691pfg.7; Sat, 23 Jan 2021 02:41:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQOMtGdz0w0TywH10TJtkHuiebtl24nbFHb0UeqsueY=; b=SrFxQ9dTqZv0qxnrpOmx/VyXccUIpYyMZ5IdIhhoJJnatNlSDSr32a8znRuT/TxxH8 ISuWbvKTWQzjKwJjGQXxfTjoydv1jXOsnIZ836Rmxuzq7nELQk6AF5zo8wN9i1wwqE2M 34YIU+tySOizsSm3UlMOM1FG7I8a904IJ0r4/0MfAcjdhoocEmZ8fBiJMVqimQr5gC25 k/0koWM3mrui5qCf83MjzJlKQ9biUuaNwW/Lg8JY/MbU+fV/nL6O6Q1qnotetwj6IYBs lxPneoXlNW6irQ4+o8Q1wqUJB0xZZsQC4F3CNGDJELNw+JqkbNfqNYgCBUDSUOOigFrL T2og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UQOMtGdz0w0TywH10TJtkHuiebtl24nbFHb0UeqsueY=; b=PdRFjeeyx0vXScdZgN+7B3bFpIdYGvZGNq25s2r/G9TkMsVml8DMvWJkIhwAcnMqZx +QzT2NAV7ThsVacX5KjbBt/b+Ee4L16CgEkZsqgh/7FtR4UZZULBZtEifblbpzrkDCBC Gxbiy9DdRB2nH8T+Hmycxsp/bJKbiWXk6WCX5qZ1XCD2lOea8tikFr2x2KOLy7dQQZji ZRHeI5TWf+0zH/6ZkhZcnka0bwEsImKASByfQrxLtTpWGRAaEki0aC4ZwQy/wnL8kq6r LSVJ6BigZSoCrTLpv73qPCTW6+5IRMY7WS263qxcEVMGZlRxIVNmaupza7Dl9PI+BrPi Ffig== X-Gm-Message-State: AOAM533s27qs16gJeMI6Y1NkU/3xz2th8IvYFwk2tz+3lRNlFpqv1THj YGqZiS9Sc5S6geNG9Jkf4xQ= X-Google-Smtp-Source: ABdhPJweOxTuHixjpAcjy/UJR1o/OPBFsrB5R/wDESVSP58adBmk437l5rfR5h8zoQOhazxQ8fLlGQ== X-Received: by 2002:a63:d814:: with SMTP id b20mr9054712pgh.202.1611398486596; Sat, 23 Jan 2021 02:41:26 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:26 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 24/25] docs/system: Add RISC-V documentation Date: Sat, 23 Jan 2021 18:40:15 +0800 Message-Id: <20210123104016.17485-25-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add RISC-V system emulator documentation for generic information. `Board-specific documentation` and `RISC-V CPU features` are only a placeholder and will be added in the future. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) docs/system/target-riscv.rst | 62 ++++++++++++++++++++++++++++++++++++ docs/system/targets.rst | 1 + 2 files changed, 63 insertions(+) create mode 100644 docs/system/target-riscv.rst diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst new file mode 100644 index 0000000000..9f4b7586e5 --- /dev/null +++ b/docs/system/target-riscv.rst @@ -0,0 +1,62 @@ +.. _RISC-V-System-emulator: + +RISC-V System emulator +====================== + +QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the +``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine, +``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine. + +QEMU has generally good support for RISC-V guests. It has support for +several different machines. The reason we support so many is that +RISC-V hardware is much more widely varying than x86 hardware. RISC-V +CPUs are generally built into "system-on-chip" (SoC) designs created by +many different companies with different devices, and these SoCs are +then built into machines which can vary still further even if they use +the same SoC. + +For most boards the CPU type is fixed (matching what the hardware has), +so typically you don't need to specify the CPU type by hand, except for +special cases like the ``virt`` board. + +Choosing a board model +---------------------- + +For QEMU's RISC-V system emulation, you must specify which board +model you want to use with the ``-M`` or ``--machine`` option; +there is no default. + +Because RISC-V systems differ so much and in fundamental ways, typically +operating system or firmware images intended to run on one machine +will not run at all on any other. This is often surprising for new +users who are used to the x86 world where every system looks like a +standard PC. (Once the kernel has booted, most user space software +cares much less about the detail of the hardware.) + +If you already have a system image or a kernel that works on hardware +and you want to boot with QEMU, check whether QEMU lists that machine +in its ``-machine help`` output. If it is listed, then you can probably +use that board model. If it is not listed, then unfortunately your image +will almost certainly not boot on QEMU. (You might be able to +extract the file system and use that with a different kernel which +boots on a system that QEMU does emulate.) + +If you don't care about reproducing the idiosyncrasies of a particular +bit of hardware, such as small amount of RAM, no PCI or other hard +disk, etc., and just want to run Linux, the best option is to use the +``virt`` board. This is a platform which doesn't correspond to any +real hardware and is designed for use in virtual machines. You'll +need to compile Linux with a suitable configuration for running on +the ``virt`` board. ``virt`` supports PCI, virtio, recent CPUs and +large amounts of RAM. It also supports 64-bit CPUs. + +Board-specific documentation +---------------------------- + +Unfortunately many of the RISC-V boards QEMU supports are currently +undocumented; you can get a complete list by running +``qemu-system-riscv64 --machine help``, or +``qemu-system-riscv32 --machine help``. + +RISC-V CPU features +------------------- diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 564cea9a9b..75ed1087fd 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -19,6 +19,7 @@ Contents: target-m68k target-mips target-ppc + target-riscv target-rx target-s390x target-sparc From patchwork Sat Jan 23 10:40:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12041437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13B05C433DB for ; Sat, 23 Jan 2021 11:02:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5606D233FC for ; Sat, 23 Jan 2021 11:02:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5606D233FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:52908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l3Ggw-0003RR-CE for qemu-devel@archiver.kernel.org; Sat, 23 Jan 2021 06:02:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3GMa-0003Vz-IG; Sat, 23 Jan 2021 05:41:57 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:38074) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3GMI-0003Km-5t; Sat, 23 Jan 2021 05:41:52 -0500 Received: by mail-pg1-x532.google.com with SMTP id q7so5601048pgm.5; Sat, 23 Jan 2021 02:41:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dR1NHgzgveUZa3WdaBmcmETuElRn3dOZVSTTQ8RUVS8=; b=njAUaPR7hks6j+ESad6DvcJTLii1hGK7yRCKHJp5G7nKEsTNDMt2/jNOgy2xhWGAnb xjoHyAS/Fkc5W9zU/MTQ3PJtGpyxNl1bxP2/LutVFKkf3kV/xPL+yuGQjZO5awKrq80D j5RgjBo9r4FPUnwN1K6cMt0yUn+ZTdATi/eu8hecODjTb7N550iRqRQM/ByMy3mlw3+Z iDluShRFRe4Gyr9TQFDTuKArQCeZPMHku4rnyAWa3AtuKg9FnaI8ACZBINFWZtF17FFL nVAngy95JUjiNqCt2pr3uO7gaSbW//tv81tN5DZCFFx3nUxdAfEqd3Zc5WZeJTGsp9f9 jEjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dR1NHgzgveUZa3WdaBmcmETuElRn3dOZVSTTQ8RUVS8=; b=KTAFweYVTt9V7REIx/8iFoQoyZExplT9BeE2VZ2G+jdVzIRKVhyo57eJXk46EAZte4 ZQHUcMbHYVE4ShZwJQIRvKPUj2sAjSwuGGHPkwLRY76/mFuV4v8txU7sFJDKsEFw4u2n CyGMV65ZTrBxWq0ka6vWCAY0a9+8Y5i87SfwCA4CwNYUjhtLM785jvPx9ucwZ1eVLCkc m3stWNAbfXxCDzHyJMkDQ1MpnK3EpuI+RIBm/3wh4kUokFQDRCLzP75aEfErfoF4wCf3 ahAyK2rpVdyeaBLJsACK4k1Rq6uMy9KjZgxIZB+aKgFTOzmTIQnDIeK2S+ragS0cfEO6 0Zmg== X-Gm-Message-State: AOAM5339Dyv/zf7BxxRhvpwIYecqyIdWgk6vB6MwG6wRrm5QGv7HHmjT cT8BJbJNmNMKDD48gQshHAU= X-Google-Smtp-Source: ABdhPJyoi+J1UukPhRoRlMbgZfjoi9u2iLDEi8JN2X021Yt70+hdv4xiHUwYCv1oD8nGtA0i/VwIHA== X-Received: by 2002:a63:2d46:: with SMTP id t67mr1600929pgt.242.1611398489231; Sat, 23 Jan 2021 02:41:29 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id a5sm10575463pgl.41.2021.01.23.02.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 02:41:28 -0800 (PST) From: Bin Meng To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 25/25] docs/system: riscv: Add documentation for sifive_u machine Date: Sat, 23 Jan 2021 18:40:16 +0800 Message-Id: <20210123104016.17485-26-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com> References: <20210123104016.17485-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds detailed documentation for RISC-V `sifive_u` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Machine-specific options - Running Linux kernel - Running VxWorks kernel - Running U-Boot, and with an alternate configuration Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: - Correct several typos in sifive_u.rst - Update doc to mention U-Boot v2021.01 docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 10 + 2 files changed, 346 insertions(+) create mode 100644 docs/system/riscv/sifive_u.rst diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst new file mode 100644 index 0000000000..3ad2426413 --- /dev/null +++ b/docs/system/riscv/sifive_u.rst @@ -0,0 +1,336 @@ +SiFive HiFive Unleashed (``sifive_u``) +====================================== + +SiFive HiFive Unleashed Development Board is the ultimate RISC‑V development +board featuring the Freedom U540 multi-core RISC‑V processor. + +Supported devices +----------------- + +The ``sifive_u`` machine supports the following devices: + + * 1 E51 / E31 core + * Up to 4 U54 / U34 cores + * Core Level Interruptor (CLINT) + * Platform-Level Interrupt Controller (PLIC) + * Power, Reset, Clock, Interrupt (PRCI) + * L2 Loosely Integrated Memory (L2-LIM) + * DDR memory controller + * 2 UARTs + * 1 GEM Ethernet controller + * 1 GPIO controller + * 1 One-Time Programmable (OTP) memory with stored serial number + * 1 DMA controller + * 2 QSPI controllers + * 1 ISSI 25WP256 flash + * 1 SD card in SPI mode + +Please note the real world HiFive Unleashed board has a fixed configuration of +1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode. +With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores. It +is also possible to create a 32-bit variant with the same peripherals except +that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help +testing of 32-bit guest software. + +Hardware configuration information +---------------------------------- + +The ``sifive_u`` machine automatically generates a device tree blob ("dtb") +which it passes to the guest. This provides information about the addresses, +interrupt lines and other configuration of the various devices in the system. +Guest software should discover the devices that are present in the generated +DTB instead of using a DTB for the real hardware, as some of the devices are +not modeled by QEMU and trying to access these devices may cause unexpected +behavior. + +Boot options +------------ + +The ``sifive_u`` machine can start using the standard -kernel functionality +for loading a Linux kernel, a VxWorks kernel, a modified U-Boot bootloader +(S-mode) or ELF executable with the default OpenSBI firmware image as the +-bios. It also supports booting the unmodified U-Boot bootloader using the +standard -bios functionality. + +Machine-specific options +------------------------ + +The following machine-specific options are supported: + +- serial=nnn + + The board serial number. When not given, the default serial number 1 is used. + + SiFive reserves the first 1 KiB of the 16 KiB OTP memory for internal use. + The current usage is only used to store the serial number of the board at + offset 0xfc. U-Boot reads the serial number from the OTP memory, and uses + it to generate a unique MAC address to be programmed to the on-chip GEM + Ethernet controller. When multiple QEMU ``sifive_u`` machines are created + and connected to the same subnet, they all have the same MAC address hence + it creates an unusable network. In such scenario, user should give different + values to serial= when creating different ``sifive_u`` machines. + +- start-in-flash + + When given, QEMU's ROM codes jump to QSPI memory-mapped flash directly. + Otherwise QEMU will jump to DRAM or L2LIM depending on the msel= value. + When not given, it defaults to direct DRAM booting. + +- msel=[6|11] + + Mode Select (MSEL[3:0]) pins value, used to control where to boot from. + + The FU540 SoC supports booting from several sources, which are controlled + using the Mode Select pins on the chip. Typically, the boot process runs + through several stages before it begins execution of user-provided programs. + These stages typically include the following: + + 1. Zeroth Stage Boot Loader (ZSBL), which is contained in an on-chip mask + ROM and provided by QEMU. Note QEMU implemented ROM codes are not the + same as what is programmed in the hardware. The QEMU one is a simplified + version, but it provides the same functionality as the hardware. + 2. First Stage Boot Loader (FSBL), which brings up PLLs and DDR memory. + This is U-Boot SPL. + 3. Second Stage Boot Loader (SSBL), which further initializes additional + peripherals as needed. This is U-Boot proper combined with an OpenSBI + fw_dynamic firmware image. + + msel=6 means FSBL and SSBL are both on the QSPI flash. msel=11 means FSBL + and SSBL are both on the SD card. + +Running Linux kernel +-------------------- + +Linux mainline v5.10 release is tested at the time of writing. To build a +Linux mainline kernel that can be booted by the ``sifive_u`` machine in +64-bit mode, simply configure the kernel using the defconfig configuration: + +.. code-block:: bash + + $ export ARCH=riscv + $ export CROSS_COMPILE=riscv64-linux- + $ make defconfig + $ make + +To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -kernel arch/riscv/boot/Image \ + -initrd /path/to/rootfs.ext4 \ + -append "root=/dev/ram" + +To build a Linux mainline kernel that can be booted by the ``sifive_u`` machine +in 32-bit mode, use the rv32_defconfig configuration. A patch is required to +fix the 32-bit boot issue for Linux kernel v5.10. + +.. code-block:: bash + + $ export ARCH=riscv + $ export CROSS_COMPILE=riscv64-linux- + $ curl https://patchwork.kernel.org/project/linux-riscv/patch/20201219001356.2887782-1-atish.patra@wdc.com/mbox/ > riscv.patch + $ git am riscv.patch + $ make rv32_defconfig + $ make + +Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command +line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit +applications shall be used in order for kernel to boot to user space. + +Running VxWorks kernel +---------------------- + +VxWorks 7 SR0650 release is tested at the time of writing. To build a 64-bit +VxWorks mainline kernel that can be booted by the ``sifive_u`` machine, simply +create a VxWorks source build project based on the sifive_generic BSP, and a +VxWorks image project to generate the bootable VxWorks image, by following the +BSP documentation instructions. + +A pre-built 64-bit VxWorks 7 image for HiFive Unleashed board is available as +part of the VxWorks SDK for testing as well. Instructions to download the SDK: + +.. code-block:: bash + + $ wget https://labs.windriver.com/downloads/wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2 + $ tar xvf wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2 + $ ls bsps/sifive_generic_1_0_0_0/uboot/uVxWorks + +To boot the VxWorks kernel in QEMU with the ``sifive_u`` machine, use: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -nic tap,ifname=tap0,script=no,downscript=no \ + -kernel /path/to/vxWorks \ + -append "gem(0,0)host:vxWorks h=192.168.200.1 e=192.168.200.2:ffffff00 u=target pw=vxTarget f=0x01" + +It is also possible to test 32-bit VxWorks on the ``sifive_u`` machine. Create +a 32-bit project to build the 32-bit VxWorks image, and use exact the same +command line options with ``qemu-system-riscv32``. + +Running U-Boot +-------------- + +U-Boot mainline v2021.01 release is tested at the time of writing. To build a +U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine, use +the sifive_fu540_defconfig with similar commands as described above for Linux: + +.. code-block:: bash + + $ export CROSS_COMPILE=riscv64-linux- + $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin + $ make sifive_fu540_defconfig + +You will get spl/u-boot-spl.bin and u-boot.itb file in the build tree. + +To start U-Boot using the ``sifive_u`` machine, prepare an SPI flash image, or +SD card image that is properly partitioned and populated with correct contents. +genimage_ can be used to generate these images. + +A sample configuration file for a 128 MiB SD card image is: + +.. code-block:: bash + + $ cat genimage_sdcard.cfg + image sdcard.img { + size = 128M + + hdimage { + gpt = true + } + + partition u-boot-spl { + image = "u-boot-spl.bin" + offset = 17K + partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47 + } + + partition u-boot { + image = "u-boot.itb" + offset = 1041K + partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985 + } + } + +SPI flash image has slightly different partition offsets, and the size has to +be 32 MiB to match the ISSI 25WP256 flash on the real board: + +.. code-block:: bash + + $ cat genimage_spi-nor.cfg + image spi-nor.img { + size = 32M + + hdimage { + gpt = true + } + + partition u-boot-spl { + image = "u-boot-spl.bin" + offset = 20K + partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47 + } + + partition u-boot { + image = "u-boot.itb" + offset = 1044K + partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985 + } + } + +Assume U-Boot binaries are put in the same directory as the config file, +we can generate the image by: + +.. code-block:: bash + + $ genimage --config genimage_.cfg --inputpath . + +Boot U-Boot from SD card, by specifying msel=11 and pass the SD card image +to QEMU ``sifive_u`` machine: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u,msel=11 -smp 5 -m 8G \ + -display none -serial stdio \ + -bios /path/to/u-boot-spl.bin \ + -drive file=/path/to/sdcard.img,if=sd + +Changing msel= value to 6, allows booting U-Boot from the SPI flash: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u,msel=6 -smp 5 -m 8G \ + -display none -serial stdio \ + -bios /path/to/u-boot-spl.bin \ + -drive file=/path/to/spi-nor.img,if=mtd + +Note when testing U-Boot, QEMU automatically generated device tree blob is +not used because U-Boot itself embeds device tree blobs for U-Boot SPL and +U-Boot proper. Hence the number of cores and size of memory have to match +the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G). + +Above use case is to run upstream U-Boot for the SiFive HiFive Unleashed +board on QEMU ``sifive_u`` machine out of the box. This allows users to +develop and test the recommended RISC-V boot flow with a real world use +case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM, +then U-Boot SPL loads the combined payload image of OpenSBI fw_dynamic +firmware and U-Boot proper. However sometimes we want to have a quick test +of booting U-Boot on QEMU without the needs of preparing the SPI flash or +SD card images, an alternate way can be used, which is to create a U-Boot +S-mode image by modifying the configuration of U-Boot: + +.. code-block:: bash + + $ make menuconfig + +then manually select the following configuration in U-Boot: + + Device Tree Control > Provider of DTB for DT Control > Prior Stage bootloader DTB + +This lets U-Boot to use the QEMU generated device tree blob. During the build, +a build error will be seen below: + +.. code-block:: none + + MKIMAGE u-boot.img + ./tools/mkimage: Can't open arch/riscv/dts/hifive-unleashed-a00.dtb: No such file or directory + ./tools/mkimage: failed to build FIT + make: *** [Makefile:1440: u-boot.img] Error 1 + +The above errors can be safely ignored as we don't run U-Boot SPL under QEMU +in this alternate configuration. + +Boot the 64-bit U-Boot S-mode image directly: + +.. code-block:: bash + + $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -kernel /path/to/u-boot.bin + +It's possible to create a 32-bit U-Boot S-mode image as well. + +.. code-block:: bash + + $ export CROSS_COMPILE=riscv64-linux- + $ make sifive_fu540_defconfig + $ make menuconfig + +then manually update the following configuration in U-Boot: + + Device Tree Control > Provider of DTB for DT Control > Prior Stage bootloader DTB + RISC-V architecture > Base ISA > RV32I + Boot images > Text Base > 0x80400000 + +Use the same command line options to boot the 32-bit U-Boot S-mode image: + +.. code-block:: bash + + $ qemu-system-riscv32 -M sifive_u -smp 5 -m 2G \ + -display none -serial stdio \ + -kernel /path/to/u-boot.bin + +.. _genimage: https://github.com/pengutronix/genimage diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 9f4b7586e5..94d99c4c82 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -58,5 +58,15 @@ undocumented; you can get a complete list by running ``qemu-system-riscv64 --machine help``, or ``qemu-system-riscv32 --machine help``. +.. + This table of contents should be kept sorted alphabetically + by the title text of each file, which isn't the same ordering + as an alphabetical sort by filename. + +.. toctree:: + :maxdepth: 1 + + riscv/sifive_u + RISC-V CPU features -------------------