From patchwork Tue Feb 2 13:29:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A21DC433E9 for ; Tue, 2 Feb 2021 13:33:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 513D864F45 for ; Tue, 2 Feb 2021 13:33:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232512AbhBBNda (ORCPT ); Tue, 2 Feb 2021 08:33:30 -0500 Received: from mail.kernel.org ([198.145.29.99]:59628 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232369AbhBBNbg (ORCPT ); Tue, 2 Feb 2021 08:31:36 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2310764F76; Tue, 2 Feb 2021 13:30:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=nJFVkFVcxLt04mnBQIBfm4IXRi2ERW4Q1DqINzouepk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PPTE7k8kTk+XXzwTslQP0Ritd+T4aPUY8VCOztRnA7mqy4ZhQaU13lMM9J+EHkc0b yHwbrU5KYbfnq7JwpONZhJCQD/Di55pgcdQKKTe1A1eH6OI/ZwrRwUhK3UBmPyXzDC W4Xpyu5c2qmm8psfC/oPx0S9HEzxNZBhGCMmHnPs/RB7YKB0JX4AR4RwxUvZdTkn8i tSD6s1rzTdzE75rWsXszeu9TLr8mzm4G9X5mH7xiIfRuVg7+2ZuLQ4T2h3CcQljtK/ 4UBVJP+WXDZnacBS1vF+DGD8+gZ1M5qSrMEKnOzmksi1K9bu2AUlO4BAKSOTtNlWyw T4oAWoVR/1HPQ== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yn-Db; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Fabio Estevam , Gustavo Pimentel , Jaehoon Chung , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kunihiko Hayashi , Lucas Stach , Marek Szyprowski , Martin Blumenstingl , NXP Linux Team , Neil Armstrong , Pengutronix Kernel Team , Richard Zhu , Rob Herring , Sascha Hauer , Shawn Guo , Thierry Reding , Thomas Petazzoni , Zhou Wang , devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 01/13] doc: bindings: pci: designware-pcie.txt: convert it to yaml Date: Tue, 2 Feb 2021 14:29:46 +0100 Message-Id: <706e684f571e142362d7be74eb1dcee2c8558052.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware-pcie.txt | 77 ---------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos-pcie.yaml | 2 +- .../devicetree/bindings/pci/snps,pcie.yaml | 139 ++++++++++++++++++ .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 169 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/snps,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt index b6acbe694ffb..da9253d43550 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: @@ -33,7 +33,7 @@ Required properties: - phy-names: must contain "pcie" - device_type: - should be "pci". As specified in designware-pcie.txt + should be "pci". As specified in snps,pcie.yaml Example configuration: diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 979dc7b6cfe8..84b53ae2c376 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -1,7 +1,7 @@ * Axis ARTPEC-6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt deleted file mode 100644 index 78494c4050f7..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Synopsys DesignWare PCIe interface - -Required properties: -- compatible: - "snps,dw-pcie" for RC mode; - "snps,dw-pcie-ep" for EP mode; -- reg: For designware cores version < 4.80 contains the configuration - address space. For designware core version >= 4.80, contains - the configuration and ATU address space -- reg-names: Must be "config" for the PCIe configuration space and "atu" for - the ATU address space. - (The old way of getting the configuration address space from "ranges" - is deprecated and should be avoided.) -RC mode: -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI - properties to define the mapping of the PCIe interface to interrupt - numbers. -EP mode: -- num-ib-windows: number of inbound address translation windows -- num-ob-windows: number of outbound address translation windows - -Optional properties: -- num-lanes: number of lanes to use (this property should be specified unless - the link is brought already up in BIOS) -- reset-gpio: GPIO pin number of power good signal -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" -- snps,enable-cdm-check: This is a boolean property and if present enables - automatic checking of CDM (Configuration Dependent Module) registers - for data corruption. CDM registers include standard PCIe configuration - space registers, Port Logic registers, DMA and iATU (internal Address - Translation Unit) registers. -RC mode: -- num-viewport: number of view ports configured in hardware. If a platform - does not specify it, the driver assumes 2. -- bus-range: PCI bus numbers covered (it is recommended for new devicetrees - to specify this property, to keep backwards compatibility a range of - 0x00-0xff is assumed if not present) - -EP mode: -- max-functions: maximum number of functions that can be configured - -Example configuration: - - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie"; - reg = <0xdfc00000 0x0001000>, /* IP registers */ - <0xd0000000 0x0002000>; /* Configuration space */ - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 - 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - interrupts = <25>, <24>; - #interrupt-cells = <1>; - num-lanes = <1>; - }; -or - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie-ep"; - reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ - <0xdfc01000 0x0001000>, /* IP registers 2 */ - <0xd0000000 0x2000000>; /* Configuration space */ - reg-names = "dbi", "dbi2", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <1>; - }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..9470b279e3e4 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -1,7 +1,7 @@ * Freescale i.MX6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt index 760b4d740616..2f62119d97b9 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. It shares common functions with the DesignWare PCIe core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index d6796ef54ea1..4d243bfb9709 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 6bbe43818ad5..a38f8e38a67b 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..8070adfc1746 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -1,7 +1,7 @@ Freescale Layerscape PCIe controller This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index bd43f3c3ece4..4644d79e0e0c 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -1,7 +1,7 @@ NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) This PCIe controller is based on the Synopsis Designware PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Some of the controller instances are dual mode where in they can work either in root port mode or endpoint mode but one at a time. @@ -22,7 +22,7 @@ Required properties: property. - reg-names: Must include the following entries: "appl": Controller's application logic registers - "config": As per the definition in designware-pcie.txt + "config": As per the definition in snps,pcie.yaml "atu_dma": iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for SW access. diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 7a813d0e6d63..4531b895e9ea 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -1,7 +1,7 @@ * Marvell Armada 7K/8K PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "marvell,armada8k-pcie" diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 47202a2938f2..ac271a0ca078 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -3,9 +3,9 @@ TI Keystone PCIe interface Keystone PCI host Controller is based on the Synopsys DesignWare PCI hardware version 3.65. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt +Documentation/devicetree/bindings/pci/snps,pcie.yaml -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt +Please refer to Documentation/devicetree/bindings/pci/snps,pcie.yaml for the details of DesignWare DT bindings. Additional properties are described here as well as properties that are not applicable. @@ -82,11 +82,11 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the Address Translation Unit configuration registers and "addr_space" used to map remote RC address space num-ib-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-ob-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-lanes: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml power-domains: As documented by the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. ti,syscon-pcie-mode: phandle to the device control module required to configure diff --git a/Documentation/devicetree/bindings/pci/pcie-al.txt b/Documentation/devicetree/bindings/pci/pcie-al.txt index 557a5089229d..6e1e20e15ae9 100644 --- a/Documentation/devicetree/bindings/pci/pcie-al.txt +++ b/Documentation/devicetree/bindings/pci/pcie-al.txt @@ -2,7 +2,7 @@ Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare PCI core. It inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Properties of the host controller node that differ from it are: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..43c3086cf6ea 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -33,22 +33,22 @@ - device_type: Usage: required Value type: - Definition: Should be "pci". As specified in designware-pcie.txt + Definition: Should be "pci". As specified in snps,pcie.yaml - #address-cells: Usage: required Value type: - Definition: Should be 3. As specified in designware-pcie.txt + Definition: Should be 3. As specified in snps,pcie.yaml - #size-cells: Usage: required Value type: - Definition: Should be 2. As specified in designware-pcie.txt + Definition: Should be 2. As specified in snps,pcie.yaml - ranges: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupts: Usage: required @@ -63,17 +63,17 @@ - #interrupt-cells: Usage: required Value type: - Definition: Should be 1. As specified in designware-pcie.txt + Definition: Should be 1. As specified in snps,pcie.yaml - interrupt-map-mask: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupt-map: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - clocks: Usage: required diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index 1810bf722350..8a4fe2d021ed 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -13,7 +13,7 @@ maintainers: description: |+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in - designware-pcie.txt. + snps,pcie.yaml. allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/pci/snps,pcie.yaml b/Documentation/devicetree/bindings/pci/snps,pcie.yaml new file mode 100644 index 000000000000..eeb5dad6937d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/snps,pcie.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/snps,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare PCIe interface + +maintainers: + - Jingoo Han + - Gustavo Pimentel + +description: | + Synopsys DesignWare PCIe host controller + +anyOf: + - {} + - items: + contains: + enum: + - snps,dw-pcie + - snps,dw-pcie-ep + +properties: + compatible: + description: | + The compatible can be either: + - snps,dw-pcie # for RC mode + - snps,dw-pcie-ep # For EP mode + or some other value, when there's a host-specific driver + + reg: + description: | + Contains DBI and the configuration address space for all + Designware versions. + For Designware core version >= 4.80, should also contain the + ATU address space. + minItems: 2 + maxItems: 4 + + reset-gpio: + description: GPIO pin number for the PERST# signal + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 8 + + clock-names: + items: + contains: + enum: [ pcie, pcie_bus ] + minItems: 2 + maxItems: 8 + + "snps,enable-cdm-check": + $ref: /schemas/types.yaml#definitions/flag + description: | + This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. + + # The following are optional properties for RC mode + + num-viewport: + description: | + number of view ports configured in hardware. If a platform + does not specify it, the driver assumes 2. + deprecated: true + + # The following are mandatory properties for EP Mode + + num-ib-windows: + description: number of inbound address translation windows + maxItems: 1 + deprecated: true + + num-ob-windows: + description: number of outbound address translation windows + maxItems: 1 + deprecated: true + + # The following are optional properties for EP mode + + max-functions: + description: maximum number of functions that can be configured + +required: + - reg + - reg-names + +allOf: + - if: + properties: + compatible: + contains: + const: snps,dw-pcie + then: + allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + const: snps,dw-pcie-ep + then: + required: + - compatible + +additionalProperties: false + +examples: + - | + pcie: pcie@dfc00000 { + compatible = "snps,dw-pcie"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + interrupts = <25>, <24>; + #interrupt-cells = <1>; + num-lanes = <1>; + }; + pcie_ep: pcie_ep@dfd00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <1>; + }; diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index d6cf8a560ef0..9c8733d21de4 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -10,7 +10,7 @@ description: | UniPhier PCIe endpoint controller is based on the Synopsys DesignWare PCI core. It shares common features with the PCIe DesignWare core and inherits common properties defined in - Documentation/devicetree/bindings/pci/designware-pcie.txt. + Documentation/devicetree/bindings/pci/snps,pcie.yaml. maintainers: - Kunihiko Hayashi diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index d5cbfe6b0d89..dfebfdb9b819 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -12,7 +12,7 @@ PCIe DesignWare Controller number of PHYs as specified in *phys* property. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - - num-lanes as specified in ../designware-pcie.txt + - num-lanes as specified in ../snps,pcie.yaml - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the register offset to specify lane selection. @@ -32,7 +32,7 @@ HOST MODE device_type, ranges, interrupt-map-mask, - interrupt-map : as specified in ../designware-pcie.txt + interrupt-map : as specified in ../snps,pcie.yaml - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument should contain the register offset within syscon and the 2nd argument should contain the bit field diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index c4b7381733a0..17cfe504d800 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -6,7 +6,7 @@ on Socionext UniPhier SoCs. UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Required properties: - compatible: Should be "socionext,uniphier-pcie". diff --git a/MAINTAINERS b/MAINTAINERS index 2dd0a662d931..0bcba0d4994c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13673,7 +13673,7 @@ M: Jingoo Han M: Gustavo Pimentel L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/designware-pcie.txt +F: Documentation/devicetree/bindings/pci/snps,pcie.yaml F: drivers/pci/controller/dwc/*designware* PCI DRIVER FOR TI DRA7XX/J721E From patchwork Tue Feb 2 13:29:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BF14C433E6 for ; Tue, 2 Feb 2021 13:31:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C27B760232 for ; Tue, 2 Feb 2021 13:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231216AbhBBNa7 (ORCPT ); Tue, 2 Feb 2021 08:30:59 -0500 Received: from mail.kernel.org ([198.145.29.99]:59292 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230002AbhBBNan (ORCPT ); Tue, 2 Feb 2021 08:30:43 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id BB60664DBD; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272601; bh=TxE7xvaYuKCsDfLLB+VpyMyldri1PDixonE3P/pTmZE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GExqZEbBL7kEEbK8fmyTmU6A2ILR+To1fjXWI9NkWuJivNWqo/Aa2YTA93NZFZJzL qjaZuRHIVvzLPpRssjxbzwJBEOXqmTEWHB6Ph27OUEL2LRHxWcCRo/l8WXBbBjo0Al JFtZfrXS/paveroKQDclso9ZgQgpu+/kmlGy8O39bdY/21Nvp+0QlL/WFdVE0NzjOB 42E6x2AN6tb6OhWZgYUrfGQpd12menSnIVwUSlMYtBg2xg7rafPXJZSXROy8uQfFWl jcsH6turZoh6CrS/kPFiUcDDiE16t1tOXL4etgbEn1dtOUk5NP1Q72kwUibf8IWg6k gjMLV1VCm0ffw== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yp-FH; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 02/13] doc: bindings: kirin-pcie.txt: convert it to yaml Date: Tue, 2 Feb 2021 14:29:47 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the file into a JSON description at the yaml format. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 90 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- MAINTAINERS | 2 +- 3 files changed, 91 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..46f9f3f25dbc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# +# - $ref: snps,pcie.yaml# + +properties: + compatible: + const: hisilicon,kirin960-pcie + + reg: + description: | + Should contain rc_dbi, apb, phy, config registers location and length. + + reg-names: + items: + - const: dbi # controller configuration registers + - const: apb # apb Ctrl register defined by Kirin + - const: phy # apb PHY register defined by Kirin + - const: config # PCIe configuration space registers + + reset-gpios: + description: The GPIO to generate PCIe PERST# assert and deassert signal. + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - reset-gpios + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index a38f8e38a67b..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 0bcba0d4994c..701d7115af74 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13817,7 +13817,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB From patchwork Tue Feb 2 13:29:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D784DC4332D for ; Tue, 2 Feb 2021 13:42:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8DC7464FAD for ; Tue, 2 Feb 2021 13:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232658AbhBBNme (ORCPT ); Tue, 2 Feb 2021 08:42:34 -0500 Received: from mail.kernel.org ([198.145.29.99]:59600 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232331AbhBBNb2 (ORCPT ); Tue, 2 Feb 2021 08:31:28 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id E564B64F69; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=sSaD7ZjZax5SWdJfL3lxHnmESoHHAqsZQp3tIpWjuII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FN6Lh7lwWo4uhRohZnqPfaAUvBwF98JO5/606yFydvSu5+xuMD5P9AaiSECToYLk5 gGDh+13QvzOEkvwW+WWLRzJO5qUdibsgagO8c+PdcM4KUN987FP8sy9jH1s8m3TFTw U0402UsU9X4EXXVOkJ8oRPse99rWxZrAMGMnbr2KdOUBOtyjB+eXQnu2Osbl8PLO4s jIaJWoPwVc5YB4HCYEgOuxtGkc1SWu0Wt3JBR/bSwKoB7zR15bwdbxKqFyx1uNE5tU hswKvy7le8OPQeAIDiTOBWzFLd6HAUpGsSWxkMqNfFzyYiTbIqvxQj+TnXmwraBeC7 Z5QwHTjxleQ4g== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yr-Gs; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 03/13] doc: bindings: add new parameters used by Hikey 970 Date: Tue, 2 Feb 2021 14:29:48 +0100 Message-Id: <95dea944565d0a7ee5a35449c18c703dd005158c.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There are a few extra optional bindings that are needed for Hikey 970 PCI to work. Add them. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 60 ++++++++++++++++++- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml index 46f9f3f25dbc..7a58883e07ec 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -34,8 +34,18 @@ properties: - const: config # PCIe configuration space registers reset-gpios: - description: The GPIO to generate PCIe PERST# assert and deassert signal. - maxItems: 1 + description: The GPIOs to generate PCIe PERST# assert and deassert signal. + minItems: 1 + maxItems: 4 + + clkreq-gpios: + description: CLKREQ signal GPIO pins to be enabled during PCI power on + minItems: 1 + maxItems: 3 + + eye_param: + description: items to adjust the eye parameters + maxItems: 5 required: - compatible @@ -52,12 +62,13 @@ examples: - | #include #include + #include soc { #address-cells = <2>; #size-cells = <2>; - pcie: pcie@f4000000 { + pcie1: pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, @@ -87,4 +98,47 @@ examples: "pcie_apb_sys", "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; }; + + pcie2: pcie@f5000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xfc000000 0x0 0x80000>, + <0x0 0xf5000000 0x0 0x2000>; + pci-supply = <&ldo33>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + msi-parent = <&its_pcie>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>; + }; }; From patchwork Tue Feb 2 13:29:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBD3CC43381 for ; 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Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Manivannan Sadhasivam , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH 04/13] pci: dwc: pcie-kirin: add HI3670 PCI-E controller support Date: Tue, 2 Feb 2021 14:29:49 +0100 Message-Id: <8d988a1cd73c7eae083f5e026a2db71070210fdb.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Manivannan Sadhasivam Add HiSilicon HI3670 SoC PCI-E controller support based on Designware PCI-E controller IP. [mchehab+huawei@kernel.org: fix merge conflicts] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 723 +++++++++++++++++++++++- 1 file changed, 707 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 026fd1e42a55..5925d2b345a8 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -29,6 +29,7 @@ #define to_kirin_pcie(x) dev_get_drvdata((x)->dev) #define REF_CLK_FREQ 100000000 +#define AXI_CLK_FREQ 207500000 /* PCIe ELBI registers */ #define SOC_PCIECTRL_CTRL0_ADDR 0x000 @@ -60,6 +61,65 @@ #define PCIE_DEBOUNCE_PARAM 0xF0F400 #define PCIE_OE_BYPASS (0x3 << 28) +/* PCIe CTRL registers */ +#define SOC_PCIECTRL_CTRL0_ADDR 0x000 +#define SOC_PCIECTRL_CTRL1_ADDR 0x004 +#define SOC_PCIECTRL_CTRL7_ADDR 0x01c +#define SOC_PCIECTRL_CTRL12_ADDR 0x030 +#define SOC_PCIECTRL_CTRL20_ADDR 0x050 +#define SOC_PCIECTRL_CTRL21_ADDR 0x054 +#define SOC_PCIECTRL_STATE0_ADDR 0x400 + +/* PCIe PHY registers */ +#define SOC_PCIEPHY_CTRL0_ADDR 0x000 +#define SOC_PCIEPHY_CTRL1_ADDR 0x004 +#define SOC_PCIEPHY_CTRL2_ADDR 0x008 +#define SOC_PCIEPHY_CTRL3_ADDR 0x00c +#define SOC_PCIEPHY_CTRL38_ADDR 0x0098 +#define SOC_PCIEPHY_STATE0_ADDR 0x400 + +#define PCIE_LINKUP_ENABLE (0x8020) +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) +#define PCIEPHY_RESET_BIT (0x1 << 17) +#define PCIEPHY_PIPE_LINE0_RESET_BIT (0x1 << 19) + +#define PORT_MSI_CTRL_ADDR 0x820 +#define PORT_MSI_CTRL_UPPER_ADDR 0x824 +#define PORT_MSI_CTRL_INT0_ENABLE 0x828 + +#define EYEPARAM_NOCFG 0xFFFFFFFF +#define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define SUP_DIG_LVL_OVRD_IN 0xf +#define LANEN_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define LANEN_DIG_ASIC_TX_OVRD_IN_2 0x1003 + +/* kirin970 pciephy register */ +#define SOC_PCIEPHY_MMC1PLL_CTRL1 0xc04 +#define SOC_PCIEPHY_MMC1PLL_CTRL16 0xC40 +#define SOC_PCIEPHY_MMC1PLL_CTRL17 0xC44 +#define SOC_PCIEPHY_MMC1PLL_CTRL20 0xC50 +#define SOC_PCIEPHY_MMC1PLL_CTRL21 0xC54 +#define SOC_PCIEPHY_MMC1PLL_STAT0 0xE00 + +#define CRGPERIPH_PEREN12 0x470 +#define CRGPERIPH_PERDIS12 0x474 +#define CRGPERIPH_PCIECTRL0 0x800 + +/* define ie,oe cfg */ +#define IO_IE_EN_HARD_BYPASS (0x1 << 27) +#define IO_OE_EN_HARD_BYPASS (0x1 << 11) +#define IO_HARD_CTRL_DEBOUNCE_BYPASS (0x1 << 10) +#define IO_OE_GT_MODE (0x2 << 7) +#define DEBOUNCE_WAITCFG_IN (0xf << 20) +#define DEBOUNCE_WAITCFG_OUT (0xf << 13) + +/* noc power domain */ +#define NOC_POWER_IDLEREQ_1 0x38c +#define NOC_POWER_IDLE_1 0x394 +#define NOC_PW_MASK 0x10000 +#define NOC_PW_SET_BIT 0x1 + /* peri_crg ctrl */ #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 @@ -84,12 +144,21 @@ struct kirin_pcie { void __iomem *phy_base; struct regmap *crgctrl; struct regmap *sysctrl; + struct regmap *pmctrl; struct clk *apb_sys_clk; struct clk *apb_phy_clk; struct clk *phy_ref_clk; struct clk *pcie_aclk; struct clk *pcie_aux_clk; - int gpio_id_reset; + int gpio_id_reset[4]; + int gpio_id_clkreq[3]; + u32 eye_param[5]; +}; + +struct kirin_pcie_ops { + long (*get_resource)(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev); + int (*power_on)(struct kirin_pcie *kirin_pcie); }; /* Registers in PCIeCTRL */ @@ -116,6 +185,28 @@ static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) return readl(kirin_pcie->phy_base + reg); } +static inline void kirin970_apb_phy_writel(struct kirin_pcie *kirin_pcie, + u32 val, u32 reg) +{ + writel(val, kirin_pcie->phy_base + 0x40000 + reg); +} + +static inline u32 kirin970_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) +{ + return readl(kirin_pcie->phy_base + 0x40000 + reg); +} + +static inline void kirin_apb_natural_phy_writel(struct kirin_pcie *kirin_pcie, + u32 val, u32 reg) +{ + writel(val, kirin_pcie->phy_base + reg * 4); +} + +static inline u32 kirin_apb_natural_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) +{ + return readl(kirin_pcie->phy_base + reg * 4); +} + static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { @@ -144,9 +235,68 @@ static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, return 0; } -static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) +void kirin970_pcie_get_eyeparam(struct kirin_pcie *pcie) { + struct device *dev = pcie->pci->dev; + int i; + struct device_node *np; + + np = dev->of_node; + + if (of_property_read_u32_array(np, "eye_param", pcie->eye_param, 5)) { + for (i = 0; i < 5; i++) + pcie->eye_param[i] = EYEPARAM_NOCFG; + } + + dev_dbg(dev, "eye_param_vboost = [0x%x]\n", pcie->eye_param[0]); + dev_dbg(dev, "eye_param_iboost = [0x%x]\n", pcie->eye_param[1]); + dev_dbg(dev, "eye_param_pre = [0x%x]\n", pcie->eye_param[2]); + dev_dbg(dev, "eye_param_post = [0x%x]\n", pcie->eye_param[3]); + dev_dbg(dev, "eye_param_main = [0x%x]\n", pcie->eye_param[4]); +} + +static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie) +{ + u32 val; + + val = kirin_apb_natural_phy_readl(kirin_pcie, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); + + if (kirin_pcie->eye_param[1] != EYEPARAM_NOCFG) { + val &= (~0xf00); + val |= (kirin_pcie->eye_param[1] << 8) | (0x1 << 12); + } + kirin_apb_natural_phy_writel(kirin_pcie, val, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); + + val = kirin_apb_natural_phy_readl(kirin_pcie, LANEN_DIG_ASIC_TX_OVRD_IN_2); + val &= (~0x1FBF); + if (kirin_pcie->eye_param[2] != EYEPARAM_NOCFG) + val |= (kirin_pcie->eye_param[2]<< 0) | (0x1 << 6); + + if (kirin_pcie->eye_param[3] != EYEPARAM_NOCFG) + val |= (kirin_pcie->eye_param[3] << 7) | (0x1 << 13); + + kirin_apb_natural_phy_writel(kirin_pcie, val, LANEN_DIG_ASIC_TX_OVRD_IN_2); + + val = kirin_apb_natural_phy_readl(kirin_pcie, SUP_DIG_LVL_OVRD_IN); + if (kirin_pcie->eye_param[0] != EYEPARAM_NOCFG) { + val &= (~0x1C0); + val |= (kirin_pcie->eye_param[0] << 6) | (0x1 << 9); + } + kirin_apb_natural_phy_writel(kirin_pcie, val, SUP_DIG_LVL_OVRD_IN); + + val = kirin_apb_natural_phy_readl(kirin_pcie, LANEN_DIG_ASIC_TX_OVRD_IN_1); + if (kirin_pcie->eye_param[4] != EYEPARAM_NOCFG) { + val &= (~0x7E00); + val |= (kirin_pcie->eye_param[4] << 9) | (0x1 << 15); + } + kirin_apb_natural_phy_writel(kirin_pcie, val, LANEN_DIG_ASIC_TX_OVRD_IN_1); +} + +static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); if (IS_ERR(kirin_pcie->apb_base)) @@ -167,6 +317,122 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->sysctrl)) return PTR_ERR(kirin_pcie->sysctrl); + kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, + "reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[0] < 0) + return -ENODEV; + + return 0; +} + +static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *apb; + struct resource *phy; + struct resource *dbi; + int ret; + + apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb"); + kirin_pcie->apb_base = devm_ioremap_resource(dev, apb); + if (IS_ERR(kirin_pcie->apb_base)) + return PTR_ERR(kirin_pcie->apb_base); + + phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); + kirin_pcie->phy_base = devm_ioremap_resource(dev, phy); + if (IS_ERR(kirin_pcie->phy_base)) + return PTR_ERR(kirin_pcie->phy_base); + + dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); + if (IS_ERR(kirin_pcie->pci->dbi_base)) + return PTR_ERR(kirin_pcie->pci->dbi_base); + + kirin970_pcie_get_eyeparam(kirin_pcie); + + kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, + "switch,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[0] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_reset[1] = of_get_named_gpio(dev->of_node, + "eth,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[1] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_reset[2] = of_get_named_gpio(dev->of_node, + "m_2,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[2] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_reset[3] = of_get_named_gpio(dev->of_node, + "mini1,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[3] < 0) + return -ENODEV; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[0], + "pcie_switch_reset"); + if (ret) + return ret; + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[1], + "pcie_eth_reset"); + if (ret) + return ret; + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[2], + "pcie_m_2_reset"); + if (ret) + return ret; + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[3], + "pcie_mini1_reset"); + if (ret) + return ret; + + kirin_pcie->gpio_id_clkreq[0] = of_get_named_gpio(dev->of_node, + "eth,clkreq-gpios", 0); + if (kirin_pcie->gpio_id_clkreq[0] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_clkreq[1] = of_get_named_gpio(dev->of_node, + "m_2,clkreq-gpios", 0); + if (kirin_pcie->gpio_id_clkreq[1] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_clkreq[2] = of_get_named_gpio(dev->of_node, + "mini1,clkreq-gpios", 0); + if (kirin_pcie->gpio_id_clkreq[2] < 0) + return -ENODEV; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[0], + "pcie_eth_clkreq"); + if (ret) + return ret; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[1], + "pcie_m_2_clkreq"); + if (ret) + return ret; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[2], + "pcie_mini1_clkreq"); + if (ret) + return ret; + + kirin_pcie->crgctrl = + syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); + if (IS_ERR(kirin_pcie->crgctrl)) + return PTR_ERR(kirin_pcie->crgctrl); + + kirin_pcie->sysctrl = + syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl"); + if (IS_ERR(kirin_pcie->sysctrl)) + return PTR_ERR(kirin_pcie->sysctrl); + + kirin_pcie->pmctrl = + syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl"); + if (IS_ERR(kirin_pcie->sysctrl)) + return PTR_ERR(kirin_pcie->sysctrl); + return 0; } @@ -208,6 +474,21 @@ static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie) regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); } +static int kirin970_pcie_clk_ctrl(struct clk *clk, int clk_on) +{ + int ret = 0; + + if (clk_on) { + ret = clk_prepare_enable(clk); + if (ret) + return ret; + } else { + clk_disable_unprepare(clk); + } + + return ret; +} + static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) { int ret = 0; @@ -255,7 +536,401 @@ static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) return ret; } -static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) +static void kirin970_pcie_natural_cfg(struct kirin_pcie *kirin_pcie) +{ + u32 val; + + /* change 2p mem_ctrl */ + kirin_apb_ctrl_writel(kirin_pcie, 0x02605550, SOC_PCIECTRL_CTRL20_ADDR); + + /* pull up sys_aux_pwr_det */ + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL7_ADDR); + val |= (0x1 << 10); + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL7_ADDR); + + /* output, pull down */ + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL12_ADDR); + val &= ~(0x3 << 2); + val |= (0x1 << 1); + val &= ~(0x1 << 0); + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL12_ADDR); + + /* Handle phy_reset and lane0_reset to HW */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL1_ADDR); + val |= PCIEPHY_RESET_BIT; + val &= ~PCIEPHY_PIPE_LINE0_RESET_BIT; + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL1_ADDR); + + /* fix chip bug: TxDetectRx fail */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL38_ADDR); + val |= (0x1 << 2); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL38_ADDR); +} + +static void kirin970_pcie_pll_init(struct kirin_pcie *kirin_pcie) +{ + u32 val; + + /* choose FNPLL */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL1); + val |= (0x1 << 27); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL1); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL16); + val &= 0xF000FFFF; + /* fnpll fbdiv = 0xD0 */ + val |= (0xd0 << 16); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL17); + val &= 0xFF000000; + /* fnpll fracdiv = 0x555555 */ + val |= (0x555555 << 0); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL17); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL20); + val &= 0xF5FF88FF; + /* fnpll dll_en = 0x1 */ + val |= (0x1 << 27); + /* fnpll postdiv1 = 0x5 */ + val |= (0x5 << 8); + /* fnpll postdiv2 = 0x4 */ + val |= (0x4 << 12); + /* fnpll pll_mode = 0x0 */ + val &= ~(0x1 << 25); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + + kirin970_apb_phy_writel(kirin_pcie, 0x20, SOC_PCIEPHY_MMC1PLL_CTRL21); +} + +static int kirin970_pcie_pll_ctrl(struct kirin_pcie *kirin_pcie, bool enable) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 val; + int time = 200; + + if (enable) { + /* pd = 0 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL16); + val &= ~(0x1 << 0); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_STAT0); + + /* choose FNPLL */ + while (!(val & 0x10)) { + if (!time) { + dev_err(dev, "wait for pll_lock timeout\n"); + return -1; + } + time --; + udelay(1); + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_STAT0); + } + + /* pciepll_bp = 0 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL20); + val &= ~(0x1 << 16); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + + } else { + /* pd = 1 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL16); + val |= (0x1 << 0); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + /* pciepll_bp = 1 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL20); + val |= (0x1 << 16); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + } + + return 0; +} + +static void kirin970_pcie_hp_debounce_gt(struct kirin_pcie *kirin_pcie, bool open) +{ + if (open) + /* gt_clk_pcie_hp/gt_clk_pcie_debounce open */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PEREN12, 0x9000); + else + /* gt_clk_pcie_hp/gt_clk_pcie_debounce close */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x9000); +} + +static void kirin970_pcie_phyref_gt(struct kirin_pcie *kirin_pcie, bool open) +{ + unsigned int val; + + regmap_read(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, &val); + + if (open) + val &= ~(0x1 << 1); //enable hard gt mode + else + val |= (0x1 << 1); //disable hard gt mode + + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x4000); +} + +static void kirin970_pcie_oe_ctrl(struct kirin_pcie *kirin_pcie, bool en_flag) +{ + unsigned int val; + + regmap_read(kirin_pcie->crgctrl , CRGPERIPH_PCIECTRL0, &val); + + /* set ie cfg */ + val |= IO_IE_EN_HARD_BYPASS; + + /* set oe cfg */ + val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS; + + /* set phy_debounce in&out time */ + val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT); + + /* select oe_gt_mode */ + val |= IO_OE_GT_MODE; + + if (en_flag) + val &= ~IO_OE_EN_HARD_BYPASS; + else + val |= IO_OE_EN_HARD_BYPASS; + + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); +} + +static void kirin970_pcie_ioref_gt(struct kirin_pcie *kirin_pcie, bool open) +{ + unsigned int val; + + if (open) { + kirin_apb_ctrl_writel(kirin_pcie, 0x20000070, SOC_PCIECTRL_CTRL21_ADDR); + + kirin970_pcie_oe_ctrl(kirin_pcie, true); + + /* en hard gt mode */ + regmap_read(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, &val); + val &= ~(0x1 << 0); + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x2000); + + } else { + /* disable hard gt mode */ + regmap_read(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, &val); + val |= (0x1 << 0); + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x2000); + + kirin970_pcie_oe_ctrl(kirin_pcie, false); + } +} + +static int kirin970_pcie_allclk_ctrl(struct kirin_pcie *kirin_pcie, bool clk_on) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 val; + int ret = 0; + + if (!clk_on) + goto ALL_CLOSE; + + /* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL1_ADDR); + val &= ~(0x1 << 8); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL1_ADDR); + + kirin970_pcie_pll_init(kirin_pcie); + + ret = kirin970_pcie_pll_ctrl(kirin_pcie, true); + if (ret) { + dev_err(dev, "Failed to enable pll\n"); + return -1; + } + kirin970_pcie_hp_debounce_gt(kirin_pcie, true); + kirin970_pcie_phyref_gt(kirin_pcie, true); + kirin970_pcie_ioref_gt(kirin_pcie, true); + + ret = clk_set_rate(kirin_pcie->pcie_aclk, AXI_CLK_FREQ); + if (ret) { + dev_err(dev, "Failed to set rate\n"); + goto GT_CLOSE; + } + + ret = kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aclk, true); + if (ret) { + dev_err(dev, "Failed to enable pcie_aclk\n"); + goto GT_CLOSE; + } + + ret = kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aux_clk, true); + if (ret) { + dev_err(dev, "Failed to enable pcie_aux_clk\n"); + goto AUX_CLK_FAIL; + } + + return 0; + +ALL_CLOSE: + kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aux_clk, false); +AUX_CLK_FAIL: + kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aclk, false); +GT_CLOSE: + kirin970_pcie_ioref_gt(kirin_pcie, false); + kirin970_pcie_phyref_gt(kirin_pcie, false); + kirin970_pcie_hp_debounce_gt(kirin_pcie, false); + + kirin970_pcie_pll_ctrl(kirin_pcie, false); + + return ret; +} + +static bool is_pipe_clk_stable(struct kirin_pcie *kirin_pcie) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 val; + u32 time = 100; + u32 pipe_clk_stable = 0x1 << 19; + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_STATE0_ADDR); + while (val & pipe_clk_stable) { + mdelay(1); + if (time == 0) { + dev_err(dev, "PIPE clk is not stable\n"); + return false; + } + time--; + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_STATE0_ADDR); + } + + return true; +} + +static int kirin970_pcie_noc_power(struct kirin_pcie *kirin_pcie, bool enable) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 time = 100; + unsigned int val = NOC_PW_MASK; + int rst; + + if (enable) + val = NOC_PW_MASK | NOC_PW_SET_BIT; + else + val = NOC_PW_MASK; + rst = enable ? 1 : 0; + + regmap_write(kirin_pcie->pmctrl, NOC_POWER_IDLEREQ_1, val); + + time = 100; + regmap_read(kirin_pcie->pmctrl, NOC_POWER_IDLE_1, &val); + while((val & NOC_PW_SET_BIT) != rst) { + udelay(10); + if (!time) { + dev_err(dev, "Failed to reverse noc power-status\n"); + return -1; + } + time--; + regmap_read(kirin_pcie->pmctrl, NOC_POWER_IDLE_1, &val); + } + + return 0; +} + +static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) +{ + struct device *dev = kirin_pcie->pci->dev; + int ret; + u32 val; + + /* Power supply for Host */ + regmap_write(kirin_pcie->sysctrl, + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); + usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); + kirin_pcie_oe_enable(kirin_pcie); + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[0], 0); + if (ret) + dev_err(dev, "Failed to pulse eth clkreq signal\n"); + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[1], 0); + if (ret) + dev_err(dev, "Failed to pulse m.2 clkreq signal\n"); + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[2], 0); + if (ret) + dev_err(dev, "Failed to pulse mini1 clkreq signal\n"); + + ret = kirin_pcie_clk_ctrl(kirin_pcie, true); + if (ret) + return ret; + + /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ + regmap_write(kirin_pcie->sysctrl, + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); + regmap_write(kirin_pcie->crgctrl, + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); + regmap_write(kirin_pcie->sysctrl, + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); + + kirin970_pcie_natural_cfg(kirin_pcie); + + ret = kirin970_pcie_allclk_ctrl(kirin_pcie, true); + if (ret) + goto close_clk; + + /* pull down phy_test_powerdown signal */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL0_ADDR); + val &= ~(0x1 << 22); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL0_ADDR); + + /* deassert controller perst_n */ + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL12_ADDR); + val |= (0x1 << 2); + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL12_ADDR); + udelay(10); + + /* perst assert Endpoints */ + usleep_range(21000, 23000); + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); + if (ret) + goto close_clk; + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[1], 1); + if (ret) + goto close_clk; + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[2], 1); + if (ret) + goto close_clk; + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[3], 1); + if (ret) + goto close_clk; + + usleep_range(10000, 11000); + + ret = is_pipe_clk_stable(kirin_pcie); + if (!ret) + goto close_clk; + + kirin970_pcie_set_eyeparam(kirin_pcie); + + ret = kirin970_pcie_noc_power(kirin_pcie, false); + if (ret) + goto close_clk; + + return 0; +close_clk: + kirin_pcie_clk_ctrl(kirin_pcie, false); + return ret; +} + +static int kirin960_pcie_power_on(struct kirin_pcie *kirin_pcie) { int ret; @@ -282,9 +957,9 @@ static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) goto close_clk; /* perst assert Endpoint */ - if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) { + if (!gpio_request(kirin_pcie->gpio_id_reset[0], "pcie_perst")) { usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1); + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); if (ret) goto close_clk; usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); @@ -419,11 +1094,29 @@ static const struct dw_pcie_host_ops kirin_pcie_host_ops = { .host_init = kirin_pcie_host_init, }; +struct kirin_pcie_ops kirin960_pcie_ops = { + .get_resource = kirin960_pcie_get_resource, + .power_on = kirin960_pcie_power_on, +}; + +struct kirin_pcie_ops kirin970_pcie_ops = { + .get_resource = kirin970_pcie_get_resource, + .power_on = kirin970_pcie_power_on, +}; + +static const struct of_device_id kirin_pcie_match[] = { + { .compatible = "hisilicon,kirin960-pcie", .data = &kirin960_pcie_ops }, + { .compatible = "hisilicon,kirin970-pcie", .data = &kirin970_pcie_ops }, + {}, +}; + static int kirin_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct kirin_pcie *kirin_pcie; struct dw_pcie *pci; + const struct of_device_id *of_id; + struct kirin_pcie_ops *ops; int ret; if (!dev->of_node) { @@ -431,6 +1124,9 @@ static int kirin_pcie_probe(struct platform_device *pdev) return -EINVAL; } + of_id = of_match_node(kirin_pcie_match, dev->of_node); + ops = (struct kirin_pcie_ops *)of_id->data; + kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); if (!kirin_pcie) return -ENOMEM; @@ -448,20 +1144,20 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; - ret = kirin_pcie_get_resource(kirin_pcie, pdev); + ret = ops->get_resource(kirin_pcie, pdev); if (ret) return ret; - kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node, + kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) { + if (kirin_pcie->gpio_id_reset[0] == -EPROBE_DEFER) { return -EPROBE_DEFER; - } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) { + } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset[0])) { dev_err(dev, "unable to get a valid gpio pin\n"); return -ENODEV; } - ret = kirin_pcie_power_on(kirin_pcie); + ret = ops->power_on(kirin_pcie); if (ret) return ret; @@ -470,11 +1166,6 @@ static int kirin_pcie_probe(struct platform_device *pdev) return dw_pcie_host_init(&pci->pp); } -static const struct of_device_id kirin_pcie_match[] = { - { .compatible = "hisilicon,kirin960-pcie" }, - {}, -}; - static struct platform_driver kirin_pcie_driver = { .probe = kirin_pcie_probe, .driver = { From patchwork Tue Feb 2 13:29:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88675C43381 for ; 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Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 06/13] pci: dwc: pcie-kirin: simplify error handling logic Date: Tue, 2 Feb 2021 14:29:51 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of returning -ENODEV when of_get_named_gpio() fails, make it return the actual error code. With that, there's no need anymore to check for -EPROBE_DEFER at kirin_pcie_probe(). Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 5925d2b345a8..f46a51ffd2c8 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -320,7 +320,7 @@ static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, "reset-gpios", 0); if (kirin_pcie->gpio_id_reset[0] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[0]; return 0; } @@ -354,22 +354,22 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, "switch,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[0] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[0]; kirin_pcie->gpio_id_reset[1] = of_get_named_gpio(dev->of_node, "eth,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[1] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[1]; kirin_pcie->gpio_id_reset[2] = of_get_named_gpio(dev->of_node, "m_2,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[2] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[2]; kirin_pcie->gpio_id_reset[3] = of_get_named_gpio(dev->of_node, "mini1,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[3] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[3]; ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[0], "pcie_switch_reset"); @@ -1148,11 +1148,7 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; - kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[0] == -EPROBE_DEFER) { - return -EPROBE_DEFER; - } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset[0])) { + if (!gpio_is_valid(kirin_pcie->gpio_id_reset[0])) { dev_err(dev, "unable to get a valid gpio pin\n"); return -ENODEV; } From patchwork Tue Feb 2 13:29:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34423C4332B for ; Tue, 2 Feb 2021 13:31:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E46D164DBD for ; Tue, 2 Feb 2021 13:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbhBBNbB (ORCPT ); Tue, 2 Feb 2021 08:31:01 -0500 Received: from mail.kernel.org ([198.145.29.99]:59344 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231713AbhBBNan (ORCPT ); Tue, 2 Feb 2021 08:30:43 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id D15B164F5F; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=Kq8Ew8T+rpiYwjmx29cnowJ2F9DKPIXYcwC0xRArm8w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hzzZJpCMHKf6jBeFAhaJLL2a+bvIfWpjjB2JnCRtm2CnmUGQHUCNtAIQttHhk/qle +fuRf7hb2c/IAK4qHixnckJv6q244xOFqlrrv3QeONhujIGS1d6rqwjM0+1uF+2qLi eKxOgf6qy7Lh42YBO2Tf8orNjD5swiZvZyDAYqB1/tOmnknDcL1KmhTSekefoBXziA MmwRJSTvdb7W8ObCub8LJ0C1ZY1fC9SmnrS16rw1kFK2HpoPNNFWy3gqaTlgyeoYGA 4RKfBLB/oBDXFKnnNc8srdZYtKDVbH+zk1SZcgtUOnIFsrEG8irLL2T8YKuqU/ZZrF oy2crB4xkRITw== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yz-MY; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 07/13] pci: dwc: pcie-kirin: simplify kirin 970 get resource logic Date: Tue, 2 Feb 2021 14:29:52 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use devm_platform_ioremap_resource_byname() in order to simplify the logic and to make the logic for Kirin 970 similar to the one for Kirin 960. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index f46a51ffd2c8..e1ebe0747978 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -297,13 +297,13 @@ static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, { struct device *dev = &pdev->dev; - kirin_pcie->apb_base = - devm_platform_ioremap_resource_byname(pdev, "apb"); + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, + "apb"); if (IS_ERR(kirin_pcie->apb_base)) return PTR_ERR(kirin_pcie->apb_base); - kirin_pcie->phy_base = - devm_platform_ioremap_resource_byname(pdev, "phy"); + kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, + "phy"); if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); @@ -329,23 +329,20 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *apb; - struct resource *phy; - struct resource *dbi; int ret; - apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb"); - kirin_pcie->apb_base = devm_ioremap_resource(dev, apb); + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, + "apb"); if (IS_ERR(kirin_pcie->apb_base)) return PTR_ERR(kirin_pcie->apb_base); - phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); - kirin_pcie->phy_base = devm_ioremap_resource(dev, phy); + kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, + "phy"); if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); - dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); - kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); + kirin_pcie->pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, + "dbi"); if (IS_ERR(kirin_pcie->pci->dbi_base)) return PTR_ERR(kirin_pcie->pci->dbi_base); From patchwork Tue Feb 2 13:29:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC54C433E6 for ; Tue, 2 Feb 2021 13:32:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CAF7364DBD for ; Tue, 2 Feb 2021 13:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231846AbhBBNb5 (ORCPT ); Tue, 2 Feb 2021 08:31:57 -0500 Received: from mail.kernel.org ([198.145.29.99]:59574 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232332AbhBBNbZ (ORCPT ); Tue, 2 Feb 2021 08:31:25 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id DDAE164F65; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=pfDNid8GVXG6AUlZB+EoyM5rAGYDRiXG0+Zst8HO5jU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sUnMslDEY8EJtGiSDmGcVE0lyThkGx+ZVx8kXbLtc5K8Y8/Yj+VpiVDr60xozI1Yb xCZo4esS2qRv8P5NdOP/pgd9wWLk7vNMXy3ExnepmEg6A1s2DF8HICR18pc4O8ODNi 0cTkVMVag6HWv9neotjl2YF6UsHktfWgxSDKGd/9+BuUaNBhJ7eTF/G4crBFhdNT9j zxC+ywhF2477e6h7r+v1OV70rv92fCMJ83rKPzmcscNlAmqMTGQeUoXofUI/TpQHcb rFh0tGrVA4dmATea4EuhOzg0e2x7d55vQnAm12gUFoaDs61ZzXmzgYm69tIw5ORXV6 YFazci9YHM/DA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011z2-O4; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 08/13] pci: dwc: pcie-kirin: place common init code altogether Date: Tue, 2 Feb 2021 14:29:53 +0100 Message-Id: <4a4d899b8be44ffd3b4f431085828dcf22c9244f.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Both Kirin 960 and Kirin 970 need to do ioremap for apb, phy and dbi. So, use a shared code for those. It should be noticed that the dbi remap is now done by dwc core, so it can simply be removed from kirin970_pcie_get_resource(). Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 45 +++++++++++-------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index e1ebe0747978..2bce6e3750d4 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -292,21 +292,27 @@ static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie) kirin_apb_natural_phy_writel(kirin_pcie, val, LANEN_DIG_ASIC_TX_OVRD_IN_1); } +static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, + "apb"); + if (IS_ERR(kirin_pcie->apb_base)) + return PTR_ERR(kirin_pcie->apb_base); + + kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, + "phy"); + if (IS_ERR(kirin_pcie->phy_base)) + return PTR_ERR(kirin_pcie->phy_base); + + return 0; +} + static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; - kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, - "apb"); - if (IS_ERR(kirin_pcie->apb_base)) - return PTR_ERR(kirin_pcie->apb_base); - - kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, - "phy"); - if (IS_ERR(kirin_pcie->phy_base)) - return PTR_ERR(kirin_pcie->phy_base); - kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -331,21 +337,6 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct device *dev = &pdev->dev; int ret; - kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, - "apb"); - if (IS_ERR(kirin_pcie->apb_base)) - return PTR_ERR(kirin_pcie->apb_base); - - kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, - "phy"); - if (IS_ERR(kirin_pcie->phy_base)) - return PTR_ERR(kirin_pcie->phy_base); - - kirin_pcie->pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, - "dbi"); - if (IS_ERR(kirin_pcie->pci->dbi_base)) - return PTR_ERR(kirin_pcie->pci->dbi_base); - kirin970_pcie_get_eyeparam(kirin_pcie); kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, @@ -1141,6 +1132,10 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; + ret = kirin_common_pcie_get_resource(kirin_pcie, pdev); + if (ret) + return ret; + ret = ops->get_resource(kirin_pcie, pdev); if (ret) return ret; From patchwork Tue Feb 2 13:29:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41AFCC433E6 for ; Tue, 2 Feb 2021 13:30:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0076564F51 for ; Tue, 2 Feb 2021 13:30:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbhBBNap (ORCPT ); Tue, 2 Feb 2021 08:30:45 -0500 Received: from mail.kernel.org ([198.145.29.99]:59330 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231666AbhBBNam (ORCPT ); Tue, 2 Feb 2021 08:30:42 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id C7BBC64F45; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=AH432J4B7ZDZZSd0PksUuJcGVmlwemb+J6aFQtCeJ8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=urcf2yeHU1lygxszS/epnxF/w1NsCkpIfUSIzGodkmWwz/CJqrbqu85px6M1tSB+T xHfYq0dIsT0cLXTvypR4U8ZC7VTEpc2jfQQJCBzPe/gebS8atBZiM1TN3bOhSva4aM r02krnYVvuCiu2NKrywlLbIpFMMsWY1yjiANu787bL8Xlx8NY0oFKDAMZOq2xqSwIy Sl37NraJTwaHv4ZY40jfmdBMflvKKule2AxYJJwYIcQJaH26rYwOaHmK1iEgFAMKJx vgcXBLUObG3FHj92rwKoSHt+LixBVAJTVeik6k4aPJdVLwXT7OQ3xcDggAjE2suOAL ZwNtqjK+a9Bew== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011z5-P5; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Liam Girdwood , Lorenzo Pieralisi , Mark Brown , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 09/13] pci: dwc: pcie-kirin: allow to optionally require a regulator Date: Tue, 2 Feb 2021 14:29:54 +0100 Message-Id: <7f4abd1ba9f4b33fe6f66213f56aa4269db74317.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Hikey 970, there's a power supply controlled by Hi6421v600 regulator that turns on the PCI devices on the board. Without that, no PCI hardware would work. As this is device-dependent, such regulator line should be optional. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 2bce6e3750d4..42aea34dff4d 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include "pcie-designware.h" @@ -295,6 +296,22 @@ static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie) static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct regulator *reg; + int ret; + + reg = devm_regulator_get_optional(dev, "pci"); + if (IS_ERR_OR_NULL(reg)) { + if (PTR_ERR(reg) == -EPROBE_DEFER) + return PTR_ERR(reg); + } else { + ret = regulator_enable(reg); + if (ret) { + dev_err(dev, "Failed to enable regulator\n"); + return ret; + } + } + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); if (IS_ERR(kirin_pcie->apb_base)) From patchwork Tue Feb 2 13:29:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B399BC433E0 for ; Tue, 2 Feb 2021 13:31:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BEAC64DDA for ; Tue, 2 Feb 2021 13:31:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232258AbhBBNbm (ORCPT ); Tue, 2 Feb 2021 08:31:42 -0500 Received: from mail.kernel.org ([198.145.29.99]:59326 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231497AbhBBNan (ORCPT ); Tue, 2 Feb 2021 08:30:43 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id CB27D64F51; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=P1//vV/xroxOXJR5AGgK3kzXgaxmA/blRDvzebBehs0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tWe0qKCTLyT4TQ9Sm3MwTBggyxoKebyKgItKTLs1renNkPlyRIpGhiX9QXUjQpSJd 9P2B/BAUYlEyF8VrPI9njuv9t02PXnLwGDyxm2AM7kyvGkN0pKewKw/kWLzm5Mlvzv tV5qJ0Ra6+CtjuXWh+5efxLX4oftI8mJKDFUU/+0k/ldg+02u6KUk6xmeSXeoamZv/ NSnbGY+lVwyqIaTp0imp0ZQESTuzWeo+wWN3I+EWZxWm70tCbi+a4lvKy5UZ3naADl iFocacv/tyvhTLIcF8u3GpJDuUJBCx2DBfMhmGKw+meCZ5XfNWzN13yvV8WJ/o2U/d VZYc0eL/Yl+iQ== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011z7-Ql; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 10/13] pci: dwc: pcie-kirin: allow using multiple reset GPIOs Date: Tue, 2 Feb 2021 14:29:55 +0100 Message-Id: <39d125c8d033ca961bbaa77c9c2b0df3f0bd7ef1.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Hikey 970, the PCI hardware contains a bridge (PEX 8606), an Ethernet controller (RTL8169), a M.2 connector and a mini 1X connector. They work out of the box, but each of them requires its own reset line, which should be initialized when the PCI hardware is reset. So, add support for the DTS to contain multiple reset lines. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 134 +++++++++++------------- 1 file changed, 64 insertions(+), 70 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 42aea34dff4d..faf711366309 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -139,6 +139,7 @@ #define TIME_PHY_PD_MIN 10 #define TIME_PHY_PD_MAX 11 +#define MAX_GPIO_RESETS 4 struct kirin_pcie { struct dw_pcie *pci; void __iomem *apb_base; @@ -151,8 +152,10 @@ struct kirin_pcie { struct clk *phy_ref_clk; struct clk *pcie_aclk; struct clk *pcie_aux_clk; - int gpio_id_reset[4]; + int n_gpio_resets; int gpio_id_clkreq[3]; + int gpio_id_reset[MAX_GPIO_RESETS]; + const char *reset_names[MAX_GPIO_RESETS]; u32 eye_param[5]; }; @@ -297,8 +300,10 @@ static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct regulator *reg; - int ret; + char name[32]; + int ret, i; reg = devm_regulator_get_optional(dev, "pci"); if (IS_ERR_OR_NULL(reg)) { @@ -322,14 +327,47 @@ static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); + kirin_pcie->n_gpio_resets = of_gpio_named_count(np, "reset-gpios"); + if (kirin_pcie->n_gpio_resets > MAX_GPIO_RESETS) { + dev_err(dev, "Too many GPIO resets!\n"); + return -EINVAL; + } + for (i = 0; i < kirin_pcie->n_gpio_resets; i++) { + kirin_pcie->gpio_id_reset[i] = of_get_named_gpio(dev->of_node, + "reset-gpios", i); + if (kirin_pcie->gpio_id_reset[i] < 0) + return kirin_pcie->gpio_id_reset[i]; + + sprintf(name, "pcie_perst_%d", i); + kirin_pcie->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!kirin_pcie->reset_names[i]) + return -ENOMEM; + } + return 0; } +static int kirin_gpio_request(struct kirin_pcie *kirin_pcie, + struct device *dev) +{ + int ret, i; + + for (i = 0; i < kirin_pcie->n_gpio_resets; i++) { + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i], + kirin_pcie->reset_names[i]); + if (ret) + return ret; + } + + + return ret; +} + + static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { - struct device *dev = &pdev->dev; - kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -340,56 +378,18 @@ static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->sysctrl)) return PTR_ERR(kirin_pcie->sysctrl); - kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[0] < 0) - return kirin_pcie->gpio_id_reset[0]; - return 0; } static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) + struct platform_device *pdev) { struct device *dev = &pdev->dev; int ret; kirin970_pcie_get_eyeparam(kirin_pcie); - kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, - "switch,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[0] < 0) - return kirin_pcie->gpio_id_reset[0]; - - kirin_pcie->gpio_id_reset[1] = of_get_named_gpio(dev->of_node, - "eth,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[1] < 0) - return kirin_pcie->gpio_id_reset[1]; - - kirin_pcie->gpio_id_reset[2] = of_get_named_gpio(dev->of_node, - "m_2,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[2] < 0) - return kirin_pcie->gpio_id_reset[2]; - - kirin_pcie->gpio_id_reset[3] = of_get_named_gpio(dev->of_node, - "mini1,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[3] < 0) - return kirin_pcie->gpio_id_reset[3]; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[0], - "pcie_switch_reset"); - if (ret) - return ret; - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[1], - "pcie_eth_reset"); - if (ret) - return ret; - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[2], - "pcie_m_2_reset"); - if (ret) - return ret; - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[3], - "pcie_mini1_reset"); + ret = kirin_gpio_request(kirin_pcie, dev); if (ret) return ret; @@ -849,7 +849,7 @@ static int kirin970_pcie_noc_power(struct kirin_pcie *kirin_pcie, bool enable) static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) { struct device *dev = kirin_pcie->pci->dev; - int ret; + int ret, i; u32 val; /* Power supply for Host */ @@ -901,22 +901,11 @@ static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) /* perst assert Endpoints */ usleep_range(21000, 23000); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); - if (ret) - goto close_clk; - - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[1], 1); - if (ret) - goto close_clk; - - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[2], 1); - if (ret) - goto close_clk; - - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[3], 1); - if (ret) - goto close_clk; - + for (i = 0; i < kirin_pcie->n_gpio_resets; i++) { + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1); + if (ret) + return ret; + } usleep_range(10000, 11000); ret = is_pipe_clk_stable(kirin_pcie); @@ -937,6 +926,7 @@ static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) static int kirin960_pcie_power_on(struct kirin_pcie *kirin_pcie) { + struct device *dev = kirin_pcie->pci->dev; int ret; /* Power supply for Host */ @@ -962,15 +952,19 @@ static int kirin960_pcie_power_on(struct kirin_pcie *kirin_pcie) goto close_clk; /* perst assert Endpoint */ - if (!gpio_request(kirin_pcie->gpio_id_reset[0], "pcie_perst")) { - usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); - if (ret) - goto close_clk; - usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); - - return 0; - } + ret = kirin_gpio_request(kirin_pcie, dev); + if (ret) + goto close_clk; + + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); + if (ret) + goto close_clk; + + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); + + return 0; close_clk: kirin_pcie_clk_ctrl(kirin_pcie, false); From patchwork Tue Feb 2 13:29:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31ABEC433DB for ; Tue, 2 Feb 2021 13:32:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE2AC64F45 for ; Tue, 2 Feb 2021 13:32:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232397AbhBBNbv (ORCPT ); Tue, 2 Feb 2021 08:31:51 -0500 Received: from mail.kernel.org ([198.145.29.99]:59580 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232345AbhBBNb1 (ORCPT ); Tue, 2 Feb 2021 08:31:27 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id DAFFD64EDA; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=erwwnvc97xuvNb/GIafHSr71dHfEPwM5oq3L6s8voRc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H9Cb5xpnVcE+fWV4E2SuBYbqZ1Aeb/4PHUCK++GkCu8iRb0oYQMpvUa0c2LzvUF7d eW+cIuEVY6wbjcuNYUI0gZlrWskMit2+jBfUGwTaABlv/97pO0Sf3Kekcs1UQvDAhC 8RLE6790jLzYOQj9NsDALz3qqs6uPeGnZ+LMWIMSZomHhCQ0G6lQNfDco/hq1Je48S HwJxpZBg725ixI8rESo+bOm+gTxKDVvU+bw0tM/zCIll2WB6gkEyTSUV3TFzdN/p7A yWagAEIhd6X1HNvPXCF/bZFNespphPZFNVQ7l3neuIlPJ5U+hf6saEBQtQ2K+3xEPp bKQau2+0EKu8Q== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011zA-S1; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 11/13] pci: dwc: pcie-kirin: add support for clkreq GPIOs Date: Tue, 2 Feb 2021 14:29:56 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCI hardware on Hikey 970 also need to enable clock lines for PCI bridge, Ethernet and M.2 connector. Those should be enabled during PCI hardware power on logic. Add support for them. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 77 +++++++++++-------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index faf711366309..37b964386d21 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -140,6 +140,8 @@ #define TIME_PHY_PD_MAX 11 #define MAX_GPIO_RESETS 4 +#define MAX_GPIO_CLKREQ 3 + struct kirin_pcie { struct dw_pcie *pci; void __iomem *apb_base; @@ -153,9 +155,11 @@ struct kirin_pcie { struct clk *pcie_aclk; struct clk *pcie_aux_clk; int n_gpio_resets; - int gpio_id_clkreq[3]; + int n_gpio_clkreq; int gpio_id_reset[MAX_GPIO_RESETS]; const char *reset_names[MAX_GPIO_RESETS]; + int gpio_id_clkreq[MAX_GPIO_CLKREQ]; + const char *clkreq_names[MAX_GPIO_CLKREQ]; u32 eye_param[5]; }; @@ -345,6 +349,24 @@ static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, return -ENOMEM; } + kirin_pcie->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios"); + if (kirin_pcie->n_gpio_clkreq > MAX_GPIO_CLKREQ) { + dev_err(dev, "Too many GPIO clock requests!\n"); + return -EINVAL; + } + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + kirin_pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node, + "clkreq-gpios", i); + if (kirin_pcie->gpio_id_clkreq[i] < 0) + return kirin_pcie->gpio_id_clkreq[i]; + + sprintf(name, "pcie_clkreq_%d", i); + kirin_pcie->clkreq_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!kirin_pcie->clkreq_names[i]) + return -ENOMEM; + } + return 0; } @@ -360,6 +382,12 @@ static int kirin_gpio_request(struct kirin_pcie *kirin_pcie, return ret; } + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], + kirin_pcie->clkreq_names[i]); + if (ret) + return ret; + } return ret; } @@ -393,36 +421,6 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (ret) return ret; - kirin_pcie->gpio_id_clkreq[0] = of_get_named_gpio(dev->of_node, - "eth,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[0] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[1] = of_get_named_gpio(dev->of_node, - "m_2,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[1] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[2] = of_get_named_gpio(dev->of_node, - "mini1,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[2] < 0) - return -ENODEV; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[0], - "pcie_eth_clkreq"); - if (ret) - return ret; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[1], - "pcie_m_2_clkreq"); - if (ret) - return ret; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[2], - "pcie_mini1_clkreq"); - if (ret) - return ret; - kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -848,7 +846,6 @@ static int kirin970_pcie_noc_power(struct kirin_pcie *kirin_pcie, bool enable) static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) { - struct device *dev = kirin_pcie->pci->dev; int ret, i; u32 val; @@ -858,17 +855,11 @@ static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); kirin_pcie_oe_enable(kirin_pcie); - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[0], 0); - if (ret) - dev_err(dev, "Failed to pulse eth clkreq signal\n"); - - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[1], 0); - if (ret) - dev_err(dev, "Failed to pulse m.2 clkreq signal\n"); - - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[2], 0); - if (ret) - dev_err(dev, "Failed to pulse mini1 clkreq signal\n"); + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); + if (ret) + return ret; + } ret = kirin_pcie_clk_ctrl(kirin_pcie, true); if (ret) From patchwork Tue Feb 2 13:29:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26713C433DB for ; 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Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 12/13] pci: dwc: pcie-kirin: cleanup kirin970_pcie_get_eyeparam() Date: Tue, 2 Feb 2021 14:29:57 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Cleanup the routine, to let it clearer that eye_param is optional and that, if not specified, the driver will assume the default. While here, also drop the useless debug prints. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 37b964386d21..769110b39302 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -246,21 +246,18 @@ static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, void kirin970_pcie_get_eyeparam(struct kirin_pcie *pcie) { struct device *dev = pcie->pci->dev; - int i; struct device_node *np; + int ret, i; np = dev->of_node; - if (of_property_read_u32_array(np, "eye_param", pcie->eye_param, 5)) { - for (i = 0; i < 5; i++) + ret = of_property_read_u32_array(np, "eye_param", pcie->eye_param, 5); + if (!ret) + return; + + /* There's no optional eye_param property. Set array to default */ + for (i = 0; i < 5; i++) pcie->eye_param[i] = EYEPARAM_NOCFG; - } - - dev_dbg(dev, "eye_param_vboost = [0x%x]\n", pcie->eye_param[0]); - dev_dbg(dev, "eye_param_iboost = [0x%x]\n", pcie->eye_param[1]); - dev_dbg(dev, "eye_param_pre = [0x%x]\n", pcie->eye_param[2]); - dev_dbg(dev, "eye_param_post = [0x%x]\n", pcie->eye_param[3]); - dev_dbg(dev, "eye_param_main = [0x%x]\n", pcie->eye_param[4]); } static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie)