From patchwork Wed Feb 3 04:58:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12063417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42E08C433DB for ; Wed, 3 Feb 2021 04:59:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BAD3A64E2A for ; Wed, 3 Feb 2021 04:59:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BAD3A64E2A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=nuviainc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7AGQ-0002I1-SU for qemu-devel@archiver.kernel.org; Tue, 02 Feb 2021 23:59:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7AFE-00010J-O5 for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:24 -0500 Received: from mail-io1-xd2f.google.com ([2607:f8b0:4864:20::d2f]:37368) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7AFC-0007xv-Nt for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:24 -0500 Received: by mail-io1-xd2f.google.com with SMTP id f8so3410573ion.4 for ; Tue, 02 Feb 2021 20:58:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a5xa/BB8Wpo3hwVUYWTshW0JEh8EkK3TU87MGKXIhA8=; b=BZ8Z+L6pWrcKuYyjORlXxpdKPpl5DNW9BkH9fdG+LAbgeojF3Hch0b917mNRnEEuLp 4pg7rMvY1LX6aTqSPutdMYlwne4SHbiA0m5eP5ItJClWPIQwqlFX17rK/VqTvqlMHoKT ANyJ1+YIa+gk+gs/F1XJJ1pzF8t2lpe9v72CHIchOI+8TWX+gVd/ay1Sj/AepRb0lzmu DUrtdn0eY1lvUW8lJDlLLEt2vc2TK4twJBtDY1PjqS/b92nWYF6yth3tUs4AN8s7XCrp jYtOXei7G12ps9Ose0PLRue86QeoLIzU0AgFAjTkeMqBCHLSUMhv6SLS6DLjhuOM3R6A CvLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a5xa/BB8Wpo3hwVUYWTshW0JEh8EkK3TU87MGKXIhA8=; b=m9+Lr0Pih75pYQGq+nDTRUF13Fb8kIDxJ8djHP1YJJ07qYWEbCCpxKG5VYhAl4QOsf F82NdEpPXsaG9d6Aa36Bl9urcsIrsTSw67P3vStMCOYYN2h/nniQjeyHuHr2mSpG2d82 0hIszF+SMAFKCsf6YUpv2XtRCGKjhTAebGppz9/8RHRk3zWdv1FRsIm4uOtCBROuSGiL 3Wersvs5cUqnLGOP0LfdHs2r2BEzzAXnDceUDqnZgMN/qs+llJrN0HFuHmzlNaAQ22OR KSevHmjVzxlXOgmCK66PQBBPnPLhWK2q9h5rU3BS69t8r5M6hLuEOKIKX/RFy5ZK6CrL 9m5g== X-Gm-Message-State: AOAM533xAKUbGpYsqkOJ8MKJoHzLkufxBecFi46xkW690QPnkjlgSIvs ENk3dAuRDJKpvemBdUu5T9bkpMkb4bQHLjhCXvMFb3pwHvL0uWxnfqlSbTi30l7Gav6uYm1olT0 fp/so7lLTeXr5yIrgkvy+qC9RTBkkO0d47yNd68UroBIVQkaFp65XnLnYadRON5B9NGWX0bk= X-Google-Smtp-Source: ABdhPJzY8VNoPTRShgLXf0FA17VOy71a/D4LAmGtoPuQkb58rXvYqYtwZDM7XICHiBs4dz68Qv+qRw== X-Received: by 2002:a02:7820:: with SMTP id p32mr1435823jac.131.1612328301157; Tue, 02 Feb 2021 20:58:21 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id a21sm529203ioa.34.2021.02.02.20.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 20:58:20 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v4 1/4] target/arm: Add support for FEAT_DIT, Data Independent Timing Date: Tue, 2 Feb 2021 21:58:13 -0700 Message-Id: <20210203045816.10953-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210203045816.10953-1-rebecca@nuviainc.com> References: <20210203045816.10953-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2f; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd2f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add support for FEAT_DIT. DIT (Data Independent Timing) is a required feature for ARMv8.4. Since virtual machine execution is largely nondeterministic and TCG is outside of the security domain, it's implemented as a NOP. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.h | 12 +++++++++++ target/arm/helper.c | 22 ++++++++++++++++++++ target/arm/internals.h | 6 ++++++ target/arm/translate-a64.c | 12 +++++++++++ 4 files changed, 52 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863c0..2e5853928474 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1243,6 +1243,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_DIT (1U << 21) #define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) @@ -1310,6 +1311,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) #define PSTATE_UAO (1U << 23) +#define PSTATE_DIT (1U << 24) #define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) @@ -3876,6 +3878,11 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; } +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; +} + /* * 64-bit feature tests via id registers. */ @@ -4120,6 +4127,11 @@ static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; } +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 47e266d7e64f..0aad6d79dcb1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4419,6 +4419,24 @@ static const ARMCPRegInfo uao_reginfo = { .readfn = aa64_uao_read, .writefn = aa64_uao_write }; +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_DIT; +} + +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); +} + +static const ARMCPRegInfo dit_reginfo = { + .name = "DIT", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, + .type = ARM_CP_NO_RAW, .access = PL0_RW, + .readfn = aa64_dit_read, .writefn = aa64_dit_write +}; + static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -8212,6 +8230,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &uao_reginfo); } + if (cpu_isar_feature(aa64_dit, cpu)) { + define_one_arm_cp_reg(cpu, &dit_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 853fa88fd616..3d11e42d8e1b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1222,6 +1222,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if (isar_feature_aa32_pan(id)) { valid |= CPSR_PAN; } + if (isar_feature_aa32_dit(id)) { + valid |= CPSR_DIT; + } return valid; } @@ -1240,6 +1243,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) if (isar_feature_aa64_uao(id)) { valid |= PSTATE_UAO; } + if (isar_feature_aa64_dit(id)) { + valid |= PSTATE_DIT; + } if (isar_feature_aa64_mte(id)) { valid |= PSTATE_TCO; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ffc060e5d70c..1c4b8d02f3b8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, tcg_temp_free_i32(t1); break; + case 0x1a: /* DIT */ + if (!dc_isar_feature(aa64_dit, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + /* There's no need to rebuild hflags because DIT is a nop */ + break; + case 0x1e: /* DAIFSet */ t1 = tcg_const_i32(crm); gen_helper_msr_i_daifset(cpu_env, t1); From patchwork Wed Feb 3 04:58:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12063419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E56DC433E0 for ; Wed, 3 Feb 2021 04:59:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF2D964F67 for ; Wed, 3 Feb 2021 04:59:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF2D964F67 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=nuviainc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7AGT-0002Kn-3J for qemu-devel@archiver.kernel.org; Tue, 02 Feb 2021 23:59:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7AFF-00011L-Mk for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:25 -0500 Received: from mail-il1-x12d.google.com ([2607:f8b0:4864:20::12d]:35351) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7AFD-0007yb-TS for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:25 -0500 Received: by mail-il1-x12d.google.com with SMTP id g7so20215439iln.2 for ; Tue, 02 Feb 2021 20:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gk0xyCoVAMRqT9GKlFufrmlmpQNpG0K1YUjKkhlKwVg=; b=yYGDBHFS1SqUYiLLHCXFTNALY/JH9hWEnuWKOZ8uLpAez5KXfyarhCTOkGozxLUJVO i1yVjuBAlYDGFZMkl+S6j5fT2xXfEE5pDPUfqwoUuZFK54UUTAx+Ue0XQCFZ5InuWY2/ XOum9nRRk2MG+xtLW7wwatKbo9MbzGCyJCYgD14vut9miQppFnO0euHrJleRTzS60gwq b4DAelsUYY/Gcnf2SBvkxfRQbr9iC8FA8XM1KfMmLqzt0vttOcTY15aTZk0Rs3mCBbjn 8qOhRWMQdNPSGM8IM2vy5ImX2JbtfStNa4ZNzCb8YYcqPYTZw4ovqfQcYxVCwPOV58iO lxoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gk0xyCoVAMRqT9GKlFufrmlmpQNpG0K1YUjKkhlKwVg=; b=CbK3Noje5xHoMc/jqi1FjWqUmZjXmaq3EhUSKq0JaIQsyhD2xy4YaO7wA+c8ifp2BN h5FYZEyjvAC8Lil8BDWz4KCsUsWoQZ3IdBHn0dAFRjkUZkMVUa+DIQxh3FILdjXiS8Ko Q6yb+ewiN2VkMcWmaX4NKy/BqzcKBi44fu/3OWBJTQnZw2zuxAhYoHEVeqLSJQ9CHOkh ZGwzr4VrqpIrMd5CnX1w8a19GK4ASTQwS28ix4TSZ8Z5luCvwIveLKIjSDGS9LDGSpuK nOpqZcd+oht00BPWp5aOMhz55bx0yviUuVSecjtX1BnxL+RHR451e6v5ZyLa5DS+nLFW WL/A== X-Gm-Message-State: AOAM531lVOqAejY7hsCbC91qi6w4DFZXoo2zGbZ2KRw+zG22WJazIXeO 0bvvliqqO7i5Me05uTZElAo5MgzGHT8dUAlczC1OdcIqIr22/s/TII9BZoDvCZT9c+zdZxa4/lV hMfKaceID61XKMw42gYOPIJMszUaiBK8YSfug96Nq/k5jSNkseJakMGpIpK7WlM2UGac48I8= X-Google-Smtp-Source: ABdhPJyPF6Y3iveMrckuXD5M5qgO+7Farni0DfYwEewk5dOnBzvzA1Ucg//AXBdi74QDTPHSenYsbQ== X-Received: by 2002:a05:6e02:1bad:: with SMTP id n13mr1236043ili.260.1612328302460; Tue, 02 Feb 2021 20:58:22 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id a21sm529203ioa.34.2021.02.02.20.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 20:58:21 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v4 2/4] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate Date: Tue, 2 Feb 2021 21:58:14 -0700 Message-Id: <20210203045816.10953-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210203045816.10953-1-rebecca@nuviainc.com> References: <20210203045816.10953-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12d; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x12d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" cpsr has been treated as being the same as spsr, but it isn't. Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate. This allows us to add support for CPSR_DIT, adding helper functions to merge SPSR_ELx to and from CPSR. Signed-off-by: Rebecca Cran --- target/arm/helper-a64.c | 32 +++++++++++++++++--- target/arm/helper.c | 27 ++++++++++++----- target/arm/op_helper.c | 9 +----- 3 files changed, 49 insertions(+), 19 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index c426c23d2c4e..be5d3f6e75cb 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -945,11 +945,31 @@ static int el_from_spsr(uint32_t spsr) } } +static void cpsr_write_from_spsr_elx(CPUARMState *env, + uint32_t val) +{ + uint32_t mask; + + /* Save SPSR_ELx.SS into PSTATE. */ + env->pstate = (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS); + val &= ~PSTATE_SS; + + /* Move DIT to the correct location for CPSR */ + if (val & PSTATE_DIT) { + val &= ~PSTATE_DIT; + val |= CPSR_DIT; + } + + mask = aarch32_cpsr_valid_mask(env->features, \ + &env_archcpu(env)->isar); + cpsr_write(env, val, mask, CPSRWriteRaw); +} + void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); - uint32_t mask, spsr = env->banked_spsr[spsr_idx]; + uint32_t spsr = env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; @@ -998,11 +1018,13 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). */ - mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); - cpsr_write(env, spsr, mask, CPSRWriteRaw); + cpsr_write_from_spsr_elx(env, spsr); if (!arm_singlestep_active(env)) { - env->uncached_cpsr &= ~PSTATE_SS; + env->pstate &= ~PSTATE_SS; + } else { + env->pstate |= PSTATE_SS; } + aarch64_sync_64_to_32(env); if (spsr & CPSR_T) { @@ -1022,6 +1044,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &= ~PSTATE_SS; + } else { + env->pstate |= PSTATE_SS; } aarch64_restore_sp(env, new_el); helper_rebuild_hflags_a64(env, new_el); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0aad6d79dcb1..a31f37e2a257 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9420,6 +9420,21 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[15] = env->pc; } +static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) +{ + uint32_t ret = cpsr_read(env); + + /* Move DIT to the correct location for SPSR_ELx */ + if (ret & CPSR_DIT) { + ret &= ~CPSR_DIT; + ret |= PSTATE_DIT; + } + /* Merge PSTATE.SS into SPSR_ELx */ + ret |= env->pstate & PSTATE_SS; + + return ret; +} + static void take_aarch32_exception(CPUARMState *env, int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) @@ -9433,8 +9448,9 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero it now. */ - env->uncached_cpsr &= ~PSTATE_SS; - env->spsr = cpsr_read(env); + env->pstate &= ~PSTATE_SS; + env->spsr = cpsr_read_for_spsr_elx(env); + /* Clear IT bits. */ env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ @@ -9911,7 +9927,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] = env->pc; } else { - old_mode = cpsr_read(env); + old_mode = cpsr_read_for_spsr_elx(env); env->elr_el[new_el] = env->regs[15]; aarch64_sync_32_to_64(env); @@ -13201,7 +13217,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { uint32_t flags = env->hflags; - uint32_t pstate_for_ss; *cs_base = 0; assert_hflags_rebuild_correctly(env); @@ -13211,7 +13226,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } - pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; @@ -13259,7 +13273,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits); - pstate_for_ss = env->uncached_cpsr; } /* @@ -13272,7 +13285,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && - (pstate_for_ss & PSTATE_SS)) { + (env->pstate & PSTATE_SS)) { flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 5e0f123043b5..65cb37d088f8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) uint32_t HELPER(cpsr_read)(CPUARMState *env) { - /* - * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr. - * This is convenient for populating SPSR_ELx, but must be - * hidden from aarch32 mode, where it is not visible. - * - * TODO: ARMv8.4-DIT -- need to move SS somewhere else. - */ - return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS); + return cpsr_read(env) & ~CPSR_EXEC; } void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) From patchwork Wed Feb 3 04:58:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12063423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61A25C433DB for ; Wed, 3 Feb 2021 05:02:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 053A064E35 for ; Wed, 3 Feb 2021 05:02:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 053A064E35 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=nuviainc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7AIn-0004bf-3m for qemu-devel@archiver.kernel.org; Wed, 03 Feb 2021 00:02:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7AFG-00012Q-Eb for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:26 -0500 Received: from mail-il1-x134.google.com ([2607:f8b0:4864:20::134]:35949) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7AFE-0007zL-Tr for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:26 -0500 Received: by mail-il1-x134.google.com with SMTP id g9so3127575ilc.3 for ; Tue, 02 Feb 2021 20:58:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JAFdn6IbZBNqvP6S0gWLCOyNml8OyzsyVzQVR6rXHRA=; b=md6LZ7fOncCS/eEN+shzt4NvYz35WxI0DyF0VfkNIR+KwHlEW8S8UAYPJxLsCGT3xN Jmo2tVfTRkj1aoj9fTg/Hn1RZCdsjZEKJZFFFKb2X6GZi8dd0R3LRq704cDUi11ojTVM GiKRIlmPOMSyYAe9FHZOgR8xbh81M2ulbldDjuDLP7+cIVXXiCZUQ3hZyZMlz+bksn4c GmUBTSI4pjFVM7u9Jck1mMGdS5J5ioX+9cIRugqt2jaFPEaBr+rTIvPl0Zhi8mr8+JP8 OacaGN2udTQr8ZH1Ynu0whjy2tWJpwyyGfS3WjqsAZcZYQblY+LQQaRJ0cy6tMc6Srez y2BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JAFdn6IbZBNqvP6S0gWLCOyNml8OyzsyVzQVR6rXHRA=; b=j//cgmNdliej3OFxY6BiGEMMqgmPJpvntFjnnNjWpDhpLFi2O2Oa9iokRcXNWMp/DF Xx1C+e9p593ehoIErjwadrteu5tljkCGs00Kp+XHC7lmfZJgfytPWPHrGQ9LsuldCKCE hXLgoqCJt4iOyYxjhz5tuqPfkAGaDn4wY9uERLjiTPub//PXWagGFuEXsQFkcTBCXQ+j eciF/Yldkns7PMxNYkLaxLaq2fs4/Z9IYvvcb/uhXrOzIDFAHLCOSyogNjAqbr4UbwD3 YIybD/H8ZqHAdaG6Ks8f+2qwEkyqvCTHp7B4S94+7TtoIGuR19AhDPl3hO8xXbx15g4K 6yAQ== X-Gm-Message-State: AOAM530RXio/zPiklYUG4rAlqFM5sugz7LWlZQIf1SrrJKLVy/5g3eCB MhEPJYUG07EL1HUBBfmm1VnsUFb+Z7CDX5ATVPBc0rp1QzIqUe9f4MPkCUx8z+LxM/+PJEVB+mI hiaU8mRFLUZbz3GnWGzPN+IN8hs2SKRAZTp6O7wlmWpkMp2YwNyW9M7jVzfFN62cnhwJf4TM= X-Google-Smtp-Source: ABdhPJwfvA/a8Gvzo4+5LvU8pb2NxQx/wmE9li+ZBFRIouoQJ6Cpbxp9DJXIeX5xBhoTAjtuQXpxXQ== X-Received: by 2002:a92:ad0a:: with SMTP id w10mr1194167ilh.235.1612328303614; Tue, 02 Feb 2021 20:58:23 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id a21sm529203ioa.34.2021.02.02.20.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 20:58:23 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v4 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Date: Tue, 2 Feb 2021 21:58:15 -0700 Message-Id: <20210203045816.10953-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210203045816.10953-1-rebecca@nuviainc.com> References: <20210203045816.10953-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::134; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x134.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Enable FEAT_DIT for the "max" AARCH64 CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5e851028c592..9a5cfd4fc632 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -666,6 +666,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; @@ -715,6 +716,10 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = u; + u = cpu->isar.id_pfr0; + u = FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 = u; + u = cpu->isar.id_mmfr3; u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 = u; From patchwork Wed Feb 3 04:58:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12063425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33462C433E0 for ; Wed, 3 Feb 2021 05:02:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C792264F67 for ; Wed, 3 Feb 2021 05:02:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C792264F67 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=nuviainc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:45060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7AIs-0004j5-UR for qemu-devel@archiver.kernel.org; Wed, 03 Feb 2021 00:02:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7AFH-00014v-MD for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:27 -0500 Received: from mail-il1-x12f.google.com ([2607:f8b0:4864:20::12f]:42567) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7AFG-0007za-37 for qemu-devel@nongnu.org; Tue, 02 Feb 2021 23:58:27 -0500 Received: by mail-il1-x12f.google.com with SMTP id z18so21035629ile.9 for ; Tue, 02 Feb 2021 20:58:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vD0CuwlvG3G5Gb/vqP04uDAKpmcFoTl+ttHz7Ug/21o=; b=jTwXvOGeSlv+9fvVjYN1SvW7s9t8/zHbAVKPu6reXITSXK+xBzmkF+annUF2EFW9vl 8v+QbG7fz6/yrXKPRivFylCLF74v/tExYVkMNiDxbsUB+l6G093h2rpKi1mSQV9fbDD4 nrquooQV5xTA9len9Emq9SXbMdHbkXPS7djSlcgvbBUKbwO7pMwNdwqFd++kH7x8gCxN j8Jy5j2QoCxjwjsIHU0+5KrNJ4kEkYE9BRnRwMLow7BPwzkL3ogro953O6Fb4GdYvPh1 iaV0OQKdneBDkaoAMIoiTeravp9luGwuYI4M7q07Rvj2gtZFIrgug4oQfHs1jdEwuEV9 xDQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vD0CuwlvG3G5Gb/vqP04uDAKpmcFoTl+ttHz7Ug/21o=; b=rzINBNK02F0Aui42qVuQFtx7/wQhkr5DCSdfQ7bhTg5zl29Pv/Yo8z3PDrF2UZhWGv xfi1GZDvoHarZA+XgBMVGifo8Rv71WTHCy9uxHgdP48eFwZruZi2aEHjCM06iaPRN4Od +CJ9SbijVhrIE/7QrGnkab+GZWxJ+35+z2scAdcmHXssEEuz49vAQ8zEBTOvy2m5g2A3 qQxzJXjefm9inNyZRXJFmiFb73+jnJt2Ynnnr01QniFfCd4E0gi+YS6CixEsX4YtL59B 5CkVwPJKXrdUcTgUtZZ235OqIh2MzwSQMYgjBh53a22F1gInSdSAYcIfGBnXJ9QwoPLT z45A== X-Gm-Message-State: AOAM532gzU59Z02108oInKwMsMzBjpigLCCH7QC6FiZ3eCMHldDaj0pU Qj6v+bb3AMmzTfrJbl+GbFNJV0Y7fB6R1/nb9WSqfR0AsYVcPFIMy1YRcr+jnByUExEAHojdjmK SPQ5YbFSqdbV4gMw3b3CmWQBHFhIgvFFFwCRKwHJnqWXH/e70DyOnLYNYl9/oU/qnaCIskWQ= X-Google-Smtp-Source: ABdhPJx1ZYiSK4fQ8VyLdGSd48D7C93kyp28s0gwN0vmZzL9n0bpHmH2lJHSrCNJCaPX/Y0D3qbeWQ== X-Received: by 2002:a92:d250:: with SMTP id v16mr1307248ilg.236.1612328304810; Tue, 02 Feb 2021 20:58:24 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id a21sm529203ioa.34.2021.02.02.20.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 20:58:24 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v4 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU Date: Tue, 2 Feb 2021 21:58:16 -0700 Message-Id: <20210203045816.10953-5-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210203045816.10953-1-rebecca@nuviainc.com> References: <20210203045816.10953-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12f; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x12f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Enable FEAT_DIT for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40142ac141e5..c98f44624423 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2197,6 +2197,10 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ cpu->isar.id_mmfr4 = t; + + t = cpu->isar.id_pfr0; + t = FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 = t; } #endif }