From patchwork Thu Feb 4 06:48:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12066399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25B75C433E6 for ; Thu, 4 Feb 2021 06:58:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0D8F64E4D for ; Thu, 4 Feb 2021 06:58:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0D8F64E4D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 131676EC83; Thu, 4 Feb 2021 06:58:40 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 994886EC83; Thu, 4 Feb 2021 06:58:38 +0000 (UTC) IronPort-SDR: WJdadNrG1/8HSirXxCIFM44w9D2D5WoslG2B6SYrbERG/XAoysXuMoL0GPjsmddtw/XlhkVb2I ocHpm6e8Fafg== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160942387" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160942387" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 22:58:38 -0800 IronPort-SDR: lHA3rsA2V8gxbK7PcUNXgGM8MhSmXvQLl5YQrsVcdEVI4CqVy7/j8gDyHCNsRYXPgGfhH36M6b DnvSZrXB8jIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="483086897" Received: from linux-akn.iind.intel.com ([10.223.34.148]) by fmsmga001.fm.intel.com with ESMTP; 03 Feb 2021 22:58:36 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Date: Thu, 4 Feb 2021 12:18:40 +0530 Message-Id: <20210204064842.11595-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> References: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: uma.shankar@intel.com, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. Do not read the registers if DPCD rev < 1.4. Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 Signed-off-by: Ankit Nautiyal Acked-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8c12d5375607..2b83f0f433a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); /* Clear the cached register set to avoid using stale values */ - memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) + return; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, intel_dp->pcon_dsc_dpcd, sizeof(intel_dp->pcon_dsc_dpcd)) < 0) From patchwork Thu Feb 4 06:48:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12066401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB694C433E0 for ; Thu, 4 Feb 2021 06:58:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 64E7F64F47 for ; Thu, 4 Feb 2021 06:58:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 64E7F64F47 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D731F6EC85; Thu, 4 Feb 2021 06:58:41 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD8166ECDA; Thu, 4 Feb 2021 06:58:40 +0000 (UTC) IronPort-SDR: tbXO91treuHq6EfRXaz73+IM/hMXOeeUVBoHQNTka+LfApX7+pZrVtt6RHtixcJZt+yf80qkhg a6CCOtkwd2Fw== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160942389" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160942389" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 22:58:40 -0800 IronPort-SDR: NFMuUp0oMWmCc14/gmh1IY6SX9uvdvPcP94D/v9pD/ADYeOkLA0icBceMVJOOTko13oSi3dANx ovTvXDrUF7Dw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="483087808" Received: from linux-akn.iind.intel.com ([10.223.34.148]) by fmsmga001.fm.intel.com with ESMTP; 03 Feb 2021 22:58:38 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Date: Thu, 4 Feb 2021 12:18:41 +0530 Message-Id: <20210204064842.11595-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> References: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: uma.shankar@intel.com, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Defines FRL training type and link bring up sequence mode as enum. -Fixes the drm_helpers for FRL Training configuration to use these enums. -Modifies the calls to the above drm_helpers in i915/intel_dp as per the above change. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index eedbb48815b7..2ca4ab5af470 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 * @aux: DisplayPort AUX channel * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink - * @concurrent_mode: true if concurrent mode or operation is required, - * false otherwise. + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode) + enum dp_pcon_frl_train_mode frl_mode) { int ret; u8 buf; @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, if (ret < 0) return ret; - if (concurrent_mode) + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) buf |= DP_PCON_ENABLE_CONCURRENT_LINK; else buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 * @aux: DisplayPort AUX channel * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink - * @extended_train_mode : true for Extended Mode, false for Normal Mode. - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting - * from min, and stops when link training is successful. In Extended mode, all - * frl bw selected in the mask are trained by the PCON. + * @frl_type : FRL training type, can be Extended, or Normal. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode) + enum dp_pcon_frl_train_type frl_type) { int ret; u8 buf = max_frl_mask; - if (extended_train_mode) + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; + else + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2b83f0f433a2..1962d6dd8641 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) { -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) -#define PCON_CONCURRENT_MODE (1 > 0) -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) return -ETIMEDOUT; max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, + DP_PCON_FRL_MODE_SEQUENTIAL); if (ret < 0) return ret; - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, + DP_PCON_FRL_TRAIN_NORMAL); if (ret < 0) return ret; ret = drm_dp_pcon_frl_enable(&intel_dp->aux); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index edffd1dcca3e..c3f56e87a5ec 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1646,6 +1646,48 @@ enum dp_content_type { DP_CONTENT_TYPE_GAME = 0x04, }; +/** + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type + * + * This enum is used to select FRL training type for FRL training between + * an HDMI2.1 PCON and an HDMI2.1 sink. + * + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification + * Sec 6.1 Table-3. + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK + * starting from min, and stops when link training is successful. + * In Extended FRL training, all frl bw selected in the mask are trained by the + * PCON. + * + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended + */ +enum dp_pcon_frl_train_type { + DP_PCON_FRL_TRAIN_NORMAL = 0, + DP_PCON_FRL_TRAIN_EXTENDED = 1, +}; + +/** + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode + * + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 + * PCON and an HDMI2.1 sink. + * + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification + * Sec 6.1 Table-3. + * In Concurrent Mode, the FRL link bring up can be done along with DP Link + * training. In Sequential mode, the FRL link bring up is done prior to the + * DP Link training. + * + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode + */ + +enum dp_pcon_frl_train_mode { + DP_PCON_FRL_MODE_SEQUENTIAL = 0, + DP_PCON_FRL_MODE_CONCURRENT = 1, +}; + /** * struct drm_dp_vsc_sdp - drm DP VSC SDP * @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode); + enum dp_pcon_frl_train_mode frl_mode); int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode); + enum dp_pcon_frl_train_type frl_type); int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); From patchwork Thu Feb 4 06:48:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12066403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7C49C433E6 for ; Thu, 4 Feb 2021 06:58:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9914464E4D for ; Thu, 4 Feb 2021 06:58:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9914464E4D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B6ED6ECE0; Thu, 4 Feb 2021 06:58:43 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1C5A6ECDC; Thu, 4 Feb 2021 06:58:42 +0000 (UTC) IronPort-SDR: ndNzaPh9rqJx6kQjqjZ1ZaHsXfS4kXAA2yFYmq33L6bI5XmI5m4mBxrLwqSyuTV8qZX6o6D3Yf p0VHOpYDOlLg== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160942391" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160942391" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 22:58:42 -0800 IronPort-SDR: gpnxIvrqSFg5jTsqxqriIOlhkjYjBK1KhhocfUEwiHMPWE3kXW0FDSAyVh2i594CHnrWWQmTIm QQoNbG/PeAWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="483088290" Received: from linux-akn.iind.intel.com ([10.223.34.148]) by fmsmga001.fm.intel.com with ESMTP; 03 Feb 2021 22:58:40 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Date: Thu, 4 Feb 2021 12:18:42 +0530 Message-Id: <20210204064842.11595-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> References: <20210204064842.11595-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: uma.shankar@intel.com, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Remove code for resetting frl related members from intel_disable_dp, as this is not applicable for older platforms. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1962d6dd8641..9d94bdf5f517 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state, intel_edp_backlight_off(old_conn_state); intel_dp_set_power(intel_dp, DP_SET_POWER_D3); intel_pps_off(intel_dp); - intel_dp->frl.is_trained = false; - intel_dp->frl.trained_rate_gbps = 0; } static void g4x_disable_dp(struct intel_atomic_state *state,