From patchwork Fri Feb 5 06:45:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Almahallawy, Khaled" X-Patchwork-Id: 12069327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C447C433DB for ; Fri, 5 Feb 2021 06:43:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F264464F9B for ; Fri, 5 Feb 2021 06:43:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F264464F9B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 683E86E1A7; Fri, 5 Feb 2021 06:43:47 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3DD5A6E1A7 for ; Fri, 5 Feb 2021 06:43:46 +0000 (UTC) IronPort-SDR: q4QNE6R2W+XcS+8R580T/dytG257r2l10UE76hPxt2hyi2zfV90EpXDSIV4x3BKn9QPF+PRy0B gQNemlX9DG6g== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="168503475" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="168503475" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:43:45 -0800 IronPort-SDR: Ru1J38xmlFJJNnHdL2LL8oGWV1Yhfj6e9fa5RkjSdHTdmZr8jsnLSnafp3xKvkl2sOo+vddZ1B WLkyAOUQ66rQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="508439326" Received: from kialmah1-desk.jf.intel.com ([10.23.15.164]) by orsmga004.jf.intel.com with ESMTP; 04 Feb 2021 22:43:44 -0800 From: Khaled Almahallawy To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Feb 2021 22:45:31 -0800 Message-Id: <20210205064531.3158292-1-khaled.almahallawy@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: Add link rate and lane count to i915_display_info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Link rate and lane count information are more easier and faster to check in i915_display_info than checking kernel logs for people not familiar with i915 in the following scenarios: * Debugging DP tunnel bandwidth usage in Thunderbolt driver. * In USB4 certification, it is a requirement to know which link rate used by monitor to prove that DP tunnel handle up to HBR3 * In PHY Compliance, when the connector propes are not mounted correctly, some display lanes will not show up in the DP Oscilloscope and will fail CTS. Just give the tester an easy way to identify where the problem is. Cc: Imre Deak Cc: Ville Syrjälä CC: José Roberto de Souza Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d62b18d5ecd8..c6161c1e87e9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -990,9 +990,10 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) yesno(crtc_state->hw.active), DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); - seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n", + seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d, link rate = %d, lane count = %d\n", crtc_state->pipe_src_w, crtc_state->pipe_src_h, - yesno(crtc_state->dither), crtc_state->pipe_bpp); + yesno(crtc_state->dither), crtc_state->pipe_bpp, + crtc_state->port_clock, crtc_state->lane_count); intel_scaler_info(m, crtc); }