From patchwork Fri Feb 5 21:46:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F22BEC433E0 for ; Fri, 5 Feb 2021 21:46:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7DED364E37 for ; Fri, 5 Feb 2021 21:46:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7DED364E37 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CF136F4E2; Fri, 5 Feb 2021 21:46:43 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B8FE36F4E2 for ; Fri, 5 Feb 2021 21:46:41 +0000 (UTC) IronPort-SDR: g6ynMcmQQpLy6j/c4UxYHEO4+EePteDLQeq8+Tc35w+Kbk7erzuv5Clu4fB9natHUVsiX13+qk A8sQ5zFhiNPw== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181556731" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181556731" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:46:40 -0800 IronPort-SDR: DJyUuaDlBIhCyyhlSwCBdU0UO/3rR2E3tC+GnA1SiZoenUP4DErAf2YOPTV6WKAMj3MBxtAOXd Di0MAxaSZSQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="358409584" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 05 Feb 2021 13:46:38 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:46:37 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:20 +0200 Message-Id: <20210205214634.19341-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We want to put all DDI clock routing code into one place. Unify the FDI enable sequence to use the standard function instead of hand rolling its own. The disable sequence already uses the normal thing. Cc: Lucas De Marchi Signed-off-by: Ville Syrjälä Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++- drivers/gpu/drm/i915/display/intel_fdi.c | 7 +++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 28877a31adc0..dbef228555a0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -184,7 +184,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, port_name(port)); } -u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) { switch (pll->info->id) { case DPLL_ID_WRPLL1: @@ -1845,8 +1845,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); } -static void intel_ddi_clk_select(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +void intel_ddi_clk_select(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index f9a916cad7e7..e618e1c80252 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -28,7 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, struct intel_encoder *intel_encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state); -u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll); +void intel_ddi_clk_select(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 77df675e607e..dbd6be3342c0 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -565,7 +565,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 temp, i, rx_ctl_val, ddi_pll_sel; + u32 temp, i, rx_ctl_val; int n_entries; intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries); @@ -595,9 +595,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); /* Configure Port Clock Select */ - ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); - intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); - drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); + drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); + intel_ddi_clk_select(encoder, crtc_state); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ From patchwork Fri Feb 5 21:46:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C45AFC433E6 for ; Fri, 5 Feb 2021 21:46:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 672B864D9E for ; Fri, 5 Feb 2021 21:46:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 672B864D9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05F596F4E3; Fri, 5 Feb 2021 21:46:45 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 767E36F4E3 for ; Fri, 5 Feb 2021 21:46:44 +0000 (UTC) IronPort-SDR: keoGO4xMgAaoxkC72tWJhj0gjSDmKFxgj/JdTsr1s0P3LhOdqwerFCxyh4jnqJ46NTg7gMJ13G 2WTBXW2gV6yQ== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="161246654" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="161246654" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:46:44 -0800 IronPort-SDR: GiabJa7XOAtlW0vq2plDuqGqhcYD7G9hF2tr5Lt7dbUEdbSGh8vQi2Jj+LE8E4iIkz/TMFUqfw 1Qh2HsqUgE1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="373697295" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga008.fm.intel.com with SMTP; 05 Feb 2021 13:46:41 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:46:40 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:21 +0200 Message-Id: <20210205214634.19341-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The current code dealing with the clock routing for DDI encoders is a maintenance nightmare. Let's start cleaning it up by allowing the encoder to provide vfuncs for enablign/disabling the clock. We leave them initially unimplemented, falling back to the old if-else approach. v2: Convert the FDI enable sequence Reviewed-by: Lucas De Marchi #v2 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_ddi.h | 4 +-- .../drm/i915/display/intel_display_types.h | 6 ++++ drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- 4 files changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index dbef228555a0..ebfbd68b8e82 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1927,6 +1927,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } } +void intel_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + if (encoder->enable_clock) + encoder->enable_clock(encoder, crtc_state); + else + intel_ddi_clk_select(encoder, crtc_state); +} + +static void intel_ddi_disable_clock(struct intel_encoder *encoder) +{ + if (encoder->disable_clock) + encoder->disable_clock(encoder); + else + intel_ddi_clk_disable(encoder); +} + static void icl_program_mg_dp_mode(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) @@ -2171,7 +2188,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only * configure the PLL to port mapping here. */ - intel_ddi_clk_select(encoder, crtc_state); + intel_ddi_enable_clock(encoder, crtc_state); /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ if (!intel_phy_is_tc(dev_priv, phy) || @@ -2292,7 +2309,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_pps_on(intel_dp); - intel_ddi_clk_select(encoder, crtc_state); + intel_ddi_enable_clock(encoder, crtc_state); if (!intel_phy_is_tc(dev_priv, phy) || dig_port->tc_mode != TC_PORT_TBT_ALT) { @@ -2367,7 +2384,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); - intel_ddi_clk_select(encoder, crtc_state); + intel_ddi_enable_clock(encoder, crtc_state); drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, @@ -2519,7 +2536,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, dig_port->ddi_io_power_domain, fetch_and_zero(&dig_port->ddi_io_wakeref)); - intel_ddi_clk_disable(encoder); + intel_ddi_disable_clock(encoder); } static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, @@ -2542,7 +2559,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, dig_port->ddi_io_power_domain, fetch_and_zero(&dig_port->ddi_io_wakeref)); - intel_ddi_clk_disable(encoder); + intel_ddi_disable_clock(encoder); intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); } @@ -2642,7 +2659,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); intel_disable_ddi_buf(encoder, old_crtc_state); - intel_ddi_clk_disable(encoder); + intel_ddi_disable_clock(encoder); val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index e618e1c80252..1aa0eedbf342 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -28,8 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, struct intel_encoder *intel_encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state); -void intel_ddi_clk_select(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); +void intel_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 307ff4b771f4..3f00c328d188 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -219,6 +219,12 @@ struct intel_encoder { * encoders have been disabled and suspended. */ void (*shutdown)(struct intel_encoder *encoder); + /* + * Enable/disable the clock to the port. + */ + void (*enable_clock)(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); + void (*disable_clock)(struct intel_encoder *encoder); enum hpd_pin hpd_pin; enum intel_display_power_domain power_domain; /* for communication with audio component; protected by av_mutex */ diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index dbd6be3342c0..60b29110099a 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -596,7 +596,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, /* Configure Port Clock Select */ drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); - intel_ddi_clk_select(encoder, crtc_state); + intel_ddi_enable_clock(encoder, crtc_state); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ From patchwork Fri Feb 5 21:46:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DB48C433E0 for ; Fri, 5 Feb 2021 21:46:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1887F64E37 for ; Fri, 5 Feb 2021 21:46:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1887F64E37 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 980936F4E5; Fri, 5 Feb 2021 21:46:48 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B56786F4E5 for ; Fri, 5 Feb 2021 21:46:47 +0000 (UTC) IronPort-SDR: cztx04h7HJoctc+9NTj8rJuXJtJRKhrV6lnw/zCyCI9mNyrJqghc0kzLJcgZo7g00d2jxQXpTW I00hD6tqRQlA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="245563249" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="245563249" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:46:47 -0800 IronPort-SDR: jGhljXbXo10sJdCiLJmT70W3vdN49MNT6ug1tFWKz6iYxFAk5kNbJpIhsuCgzjr1VVvhgCrLGL DXPyYfeV9b6g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394025858" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 05 Feb 2021 13:46:44 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:46:44 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:22 +0200 Message-Id: <20210205214634.19341-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 03/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}() and put it into the new encoder .{enable,disable}_clock() vfuncs. v2: s/dev_priv/i915/ (Lucas) v3: Deal with FDI Reviewed-by: Lucas De Marchi #v2 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crt.c | 2 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++----- drivers/gpu/drm/i915/display/intel_ddi.h | 3 +++ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 077ebc7e6396..91a8a42b4aa2 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -1076,6 +1076,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv) crt->base.enable = hsw_enable_crt; crt->base.disable = hsw_disable_crt; crt->base.post_disable = hsw_post_disable_crt; + crt->base.enable_clock = hsw_ddi_enable_clock; + crt->base.disable_clock = hsw_ddi_disable_clock; } else { if (HAS_PCH_SPLIT(dev_priv)) { crt->base.compute_config = pch_crt_compute_config; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ebfbd68b8e82..806712020530 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1896,9 +1896,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder, intel_de_write(dev_priv, DPLL_CTRL2, val); - } else if (INTEL_GEN(dev_priv) < 9) { - intel_de_write(dev_priv, PORT_CLK_SEL(port), - hsw_pll_to_ddi_pll_sel(pll)); } mutex_unlock(&dev_priv->dpll.lock); @@ -1921,12 +1918,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (IS_GEN9_BC(dev_priv)) { intel_de_write(dev_priv, DPLL_CTRL2, intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); - } else if (INTEL_GEN(dev_priv) < 9) { - intel_de_write(dev_priv, PORT_CLK_SEL(port), - PORT_CLK_SEL_NONE); } } +void hsw_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum port port = encoder->port; + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); +} + +void hsw_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); +} + void intel_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -4073,6 +4088,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + encoder->enable_clock = hsw_ddi_enable_clock; + encoder->disable_clock = hsw_ddi_disable_clock; + } + if (IS_DG1(dev_priv)) encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 1aa0eedbf342..4a0c1d5c85e7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -30,6 +30,9 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state); void intel_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void hsw_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); +void hsw_ddi_disable_clock(struct intel_encoder *encoder); void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, From patchwork Fri Feb 5 21:46:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DE29C433DB for ; Fri, 5 Feb 2021 21:46:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B901464E36 for ; Fri, 5 Feb 2021 21:46:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B901464E36 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FC986F4E6; Fri, 5 Feb 2021 21:46:52 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id C48FE89E69 for ; Fri, 5 Feb 2021 21:46:50 +0000 (UTC) IronPort-SDR: dPuTdH0WzxCsAlC9Bd5cfTHskHycxCmTN1UNpAb2b8auQ403mWZaxHTk1u/IxaShXcTsnKkI70 SJUxFmJ+nDyQ== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="161246667" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="161246667" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:46:50 -0800 IronPort-SDR: dMuqdI5PfMXg0sVNEXtbNgRJuw0wziiNu0+VI6LeTRPkJcHb4kgj8dKNq/nTuHx/7u0iXtH2Rb H4pl8VzuDmPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="434612618" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 05 Feb 2021 13:46:47 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:46:47 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:23 +0200 Message-Id: <20210205214634.19341-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 04/15] drm/i915: Extract skl_ddi_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the DDI clock routing clode for skl/derivatives into the new encoder vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 53 +++++++++++++++++------- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 806712020530..3bd7dd28a4fc 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1885,17 +1885,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder, val = intel_de_read(dev_priv, DPCLKA_CFGCR0); val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); intel_de_write(dev_priv, DPCLKA_CFGCR0, val); - } else if (IS_GEN9_BC(dev_priv)) { - /* DDI -> PLL mapping */ - val = intel_de_read(dev_priv, DPLL_CTRL2); - - val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | - DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); - val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | - DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - - intel_de_write(dev_priv, DPLL_CTRL2, val); - } mutex_unlock(&dev_priv->dpll.lock); @@ -1915,12 +1904,43 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (IS_CANNONLAKE(dev_priv)) { intel_de_write(dev_priv, DPCLKA_CFGCR0, intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); - } else if (IS_GEN9_BC(dev_priv)) { - intel_de_write(dev_priv, DPLL_CTRL2, - intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); } } +static void skl_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum port port = encoder->port; + u32 val; + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + mutex_lock(&i915->dpll.lock); + + val = intel_de_read(i915, DPLL_CTRL2); + + val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | + DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); + val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | + DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); + + intel_de_write(i915, DPLL_CTRL2, val); + + mutex_unlock(&i915->dpll.lock); +} + +static void skl_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + intel_de_write(i915, DPLL_CTRL2, + intel_de_read(i915, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); +} + void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -4088,7 +4108,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (IS_GEN9_BC(dev_priv)) { + encoder->enable_clock = skl_ddi_enable_clock; + encoder->disable_clock = skl_ddi_disable_clock; + } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { encoder->enable_clock = hsw_ddi_enable_clock; encoder->disable_clock = hsw_ddi_disable_clock; } From patchwork Fri Feb 5 21:46:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97A4AC433E6 for ; Fri, 5 Feb 2021 21:47:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D28C64DFD for ; Fri, 5 Feb 2021 21:47:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D28C64DFD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EE106F4E8; Fri, 5 Feb 2021 21:47:10 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47B6E6F4E7 for ; Fri, 5 Feb 2021 21:47:08 +0000 (UTC) IronPort-SDR: CSI4GvwlhszYaCaidqgKET0agoAkZiLSE1Ket7pSoydrkMtew50/yolmy2Zq4zG61VqwhZrlPf aPtwO04FLG3A== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181640643" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181640643" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:06 -0800 IronPort-SDR: h32POK3INxUrV8TOZRCt4hfAAsC98YG8cv0YhvePuK0sww2CwoWDyQ+sVprhfxisNrPsgGj39s p0vk0PsLqRog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="484474565" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 05 Feb 2021 13:46:56 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:46:50 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:24 +0200 Message-Id: <20210205214634.19341-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 05/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the DDI clock routing for CNL into the new vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 62 ++++++++++++++++-------- 1 file changed, 42 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3bd7dd28a4fc..5c6cd71557a4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1851,7 +1851,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; enum phy phy = intel_port_to_phy(dev_priv, port); - u32 val; const struct intel_shared_dpll *pll = crtc_state->shared_dpll; if (drm_WARN_ON(&dev_priv->drm, !pll)) @@ -1870,21 +1869,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder, */ intel_de_write(dev_priv, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); - } else if (IS_CANNONLAKE(dev_priv)) { - /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ - val = intel_de_read(dev_priv, DPCLKA_CFGCR0); - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); - intel_de_write(dev_priv, DPCLKA_CFGCR0, val); - - /* - * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. - * This step and the step before must be done with separate - * register writes. - */ - val = intel_de_read(dev_priv, DPCLKA_CFGCR0); - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); - intel_de_write(dev_priv, DPCLKA_CFGCR0, val); } mutex_unlock(&dev_priv->dpll.lock); @@ -1901,12 +1885,47 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) (IS_JSL_EHL(dev_priv) && port >= PORT_C)) intel_de_write(dev_priv, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); - } else if (IS_CANNONLAKE(dev_priv)) { - intel_de_write(dev_priv, DPCLKA_CFGCR0, - intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } } +static void cnl_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum port port = encoder->port; + u32 val; + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + mutex_lock(&i915->dpll.lock); + + val = intel_de_read(i915, DPCLKA_CFGCR0); + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); + val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); + intel_de_write(i915, DPCLKA_CFGCR0, val); + + /* + * "This step and the step before must be + * done with separate register writes." + */ + val = intel_de_read(i915, DPCLKA_CFGCR0); + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + intel_de_write(i915, DPCLKA_CFGCR0, val); + + mutex_unlock(&i915->dpll.lock); +} + +static void cnl_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + intel_de_write(i915, DPCLKA_CFGCR0, + intel_de_read(i915, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); +} + static void skl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -4108,7 +4127,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_GEN9_BC(dev_priv)) { + if (IS_CANNONLAKE(dev_priv)) { + encoder->enable_clock = cnl_ddi_enable_clock; + encoder->disable_clock = cnl_ddi_disable_clock; + } else if (IS_GEN9_BC(dev_priv)) { encoder->enable_clock = skl_ddi_enable_clock; encoder->disable_clock = skl_ddi_disable_clock; } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { From patchwork Fri Feb 5 21:46:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EE5EC433DB for ; Fri, 5 Feb 2021 21:47:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5F6E64E33 for ; Fri, 5 Feb 2021 21:47:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5F6E64E33 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D8936F4E7; Fri, 5 Feb 2021 21:47:10 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D8D06F4E7 for ; Fri, 5 Feb 2021 21:47:09 +0000 (UTC) IronPort-SDR: 525Ye7FaDUHvBwS4HWRRduhPByG68btEwRj7i7lYkLRe+yhSzw0wSYQJtPuwlHVqu6tYGGBxLW hr3lKgFoApdw== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181556763" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181556763" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:07 -0800 IronPort-SDR: 1Vc2gGBnTPXH8oI+S22b7Sapd1lGah2wkmUdr/phlDuNbxXUlTRMrVkNbuwMvdGvfOjSrtIcO1 Zdn6KGMyXH+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="373527074" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga002.jf.intel.com with SMTP; 05 Feb 2021 13:47:06 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:05 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:25 +0200 Message-Id: <20210205214634.19341-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 06/15] drm/i915: Convert DG1 over to .{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace dg1_{map,unmap}_plls_to_ports() with the appropriate encoder vfuncs. And let's relocate the disable function next to the enable function while at it. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++------------ 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5c6cd71557a4..94df5e897d19 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1597,8 +1597,8 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, return 0; } -static void dg1_map_plls_to_ports(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void dg1_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; @@ -1631,6 +1631,19 @@ static void dg1_map_plls_to_ports(struct intel_encoder *encoder, mutex_unlock(&dev_priv->dpll.lock); } +static void dg1_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + + mutex_lock(&dev_priv->dpll.lock); + + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); + + mutex_unlock(&dev_priv->dpll.lock); +} + static void icl_map_plls_to_ports(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1683,19 +1696,6 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, mutex_unlock(&dev_priv->dpll.lock); } -static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - - mutex_lock(&dev_priv->dpll.lock); - - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, - DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); - - mutex_unlock(&dev_priv->dpll.lock); -} - static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2477,9 +2477,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); - if (IS_DG1(dev_priv)) - dg1_map_plls_to_ports(encoder, crtc_state); - else if (INTEL_GEN(dev_priv) >= 11) + if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11) icl_map_plls_to_ports(encoder, crtc_state); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); @@ -2680,9 +2678,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, intel_ddi_post_disable_dp(state, encoder, old_crtc_state, old_conn_state); - if (IS_DG1(dev_priv)) - dg1_unmap_plls_to_ports(encoder); - else if (INTEL_GEN(dev_priv) >= 11) + if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11) icl_unmap_plls_to_ports(encoder); if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) @@ -4127,7 +4123,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_CANNONLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + encoder->enable_clock = dg1_ddi_enable_clock; + encoder->disable_clock = dg1_ddi_disable_clock; + } else if (IS_CANNONLAKE(dev_priv)) { encoder->enable_clock = cnl_ddi_enable_clock; encoder->disable_clock = cnl_ddi_disable_clock; } else if (IS_GEN9_BC(dev_priv)) { From patchwork Fri Feb 5 21:46:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A580FC433E6 for ; Fri, 5 Feb 2021 21:47:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 420D664E37 for ; Fri, 5 Feb 2021 21:47:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 420D664E37 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB5276F4EB; Fri, 5 Feb 2021 21:47:17 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 713C26F4EA for ; Fri, 5 Feb 2021 21:47:16 +0000 (UTC) IronPort-SDR: F5Fdbp25T2cZtkDov4gyUhGjeJNyukcEtO8VfAx0clQ9KFm8eULqwmVYa4GoU2prFzBH2M73so YSx/9KC6Lmfg== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181556773" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181556773" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:10 -0800 IronPort-SDR: y2ZcGN3CeaTIEHVdTaoBj7+mDCbV5YMELmr4N1IQVlthOf9GGz3P22eraw3Ke8tkxtRU6QicWL y54DqVMRjvbg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="416386495" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga002.fm.intel.com with SMTP; 05 Feb 2021 13:47:09 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:08 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:26 +0200 Message-Id: <20210205214634.19341-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 07/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä For ICL+ we have several styles of clock routing for DDIs: 1) TC DDI + TC PHY -> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}() and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports() 2) ICL/TGL combo DDI + combo PHY -> just need the stuff from icl_{map,unmap}_plls_to_ports() 3) JSL/EHL TC DDI + combo PHY -> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and the full combo style clock selection from icl_{map,unmap}_plls_to_ports() 4) ADLS/RKL -> these use both TC and combo DDIs with combo PHYs, however they always use the full combo style clock selection as per icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all, thus get treated the same as 2) We extract all that from the current mess in the following way: 1) icl_ddi_tc_{enable,disable}_clock() 2) icl_ddi_combo_{enable,disable}_clock() 3) jsl_ddi_tc_{enable,disable}_clock() 4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 163 ++++++++++++++--------- 1 file changed, 102 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 94df5e897d19..d6f94a1e320e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1644,8 +1644,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder) mutex_unlock(&dev_priv->dpll.lock); } -static void icl_map_plls_to_ports(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; @@ -1673,22 +1673,20 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, drm_WARN_ON(&dev_priv->drm, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); - if (intel_phy_is_combo(dev_priv, phy)) { - /* - * Even though this register references DDIs, note that we - * want to pass the PHY rather than the port (DDI). For - * ICL, port=phy in all cases so it doesn't matter, but for - * EHL the bspec notes the following: - * - * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA - * Clock Select chooses the PLL for both DDIA and DDID and - * drives port A in all cases." - */ - val &= ~mask; - val |= sel; - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); - } + /* + * Even though this register references DDIs, note that we + * want to pass the PHY rather than the port (DDI). For + * ICL, port=phy in all cases so it doesn't matter, but for + * EHL the bspec notes the following: + * + * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA + * Clock Select chooses the PLL for both DDIA and DDID and + * drives port A in all cases." + */ + val &= ~mask; + val |= sel; + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); intel_de_write(dev_priv, reg, val); @@ -1696,7 +1694,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, mutex_unlock(&dev_priv->dpll.lock); } -static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) +static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); @@ -1845,47 +1843,71 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); } -void intel_ddi_clk_select(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + /* + * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. + * MG does not exist, but the programming is required to ungate DDIC and DDID." + */ + intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); + + icl_ddi_combo_enable_clock(encoder, crtc_state); +} + +static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + icl_ddi_combo_disable_clock(encoder); + + intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); +} + +static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); + enum port port = encoder->port; - if (drm_WARN_ON(&dev_priv->drm, !pll)) + if (drm_WARN_ON(&i915->drm, !pll)) return; - mutex_lock(&dev_priv->dpll.lock); - - if (INTEL_GEN(dev_priv) >= 11) { - if (!intel_phy_is_combo(dev_priv, phy)) - intel_de_write(dev_priv, DDI_CLK_SEL(port), - icl_pll_to_ddi_clk_sel(encoder, crtc_state)); - else if (IS_JSL_EHL(dev_priv) && port >= PORT_C) - /* - * MG does not exist but the programming is required - * to ungate DDIC and DDID - */ - intel_de_write(dev_priv, DDI_CLK_SEL(port), - DDI_CLK_SEL_MG); - } - - mutex_unlock(&dev_priv->dpll.lock); + intel_de_write(i915, DDI_CLK_SEL(port), + icl_pll_to_ddi_clk_sel(encoder, crtc_state)); + + mutex_lock(&i915->dpll.lock); + + intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, + ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); + + mutex_unlock(&i915->dpll.lock); } -static void intel_ddi_clk_disable(struct intel_encoder *encoder) +static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); - - if (INTEL_GEN(dev_priv) >= 11) { - if (!intel_phy_is_combo(dev_priv, phy) || - (IS_JSL_EHL(dev_priv) && port >= PORT_C)) - intel_de_write(dev_priv, DDI_CLK_SEL(port), - DDI_CLK_SEL_NONE); - } + + mutex_lock(&i915->dpll.lock); + + intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, + 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); + + mutex_unlock(&i915->dpll.lock); + + intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } static void cnl_ddi_enable_clock(struct intel_encoder *encoder, @@ -1986,16 +2008,12 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder, { if (encoder->enable_clock) encoder->enable_clock(encoder, crtc_state); - else - intel_ddi_clk_select(encoder, crtc_state); } static void intel_ddi_disable_clock(struct intel_encoder *encoder) { if (encoder->disable_clock) encoder->disable_clock(encoder); - else - intel_ddi_clk_disable(encoder); } static void @@ -2477,9 +2495,6 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); - if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11) - icl_map_plls_to_ports(encoder, crtc_state); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { @@ -2678,9 +2693,6 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, intel_ddi_post_disable_dp(state, encoder, old_crtc_state, old_conn_state); - if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11) - icl_unmap_plls_to_ports(encoder); - if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) intel_display_power_put(dev_priv, intel_ddi_main_link_aux_domain(dig_port), @@ -4019,6 +4031,16 @@ static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } +static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) +{ + if (INTEL_GEN(i915) >= 12) + return port >= PORT_TC1; + else if (INTEL_GEN(i915) >= 11) + return port >= PORT_C; + else + return false; +} + #define port_tc_name(port) ((port) - PORT_TC1 + '1') #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') @@ -4123,9 +4145,28 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) { + encoder->enable_clock = icl_ddi_combo_enable_clock; + encoder->disable_clock = icl_ddi_combo_disable_clock; + } else if (IS_DG1(dev_priv)) { encoder->enable_clock = dg1_ddi_enable_clock; encoder->disable_clock = dg1_ddi_disable_clock; + } else if (IS_JSL_EHL(dev_priv)) { + if (intel_ddi_is_tc(dev_priv, port)) { + encoder->enable_clock = jsl_ddi_tc_enable_clock; + encoder->disable_clock = jsl_ddi_tc_disable_clock; + } else { + encoder->enable_clock = icl_ddi_combo_enable_clock; + encoder->disable_clock = icl_ddi_combo_disable_clock; + } + } else if (INTEL_GEN(dev_priv) >= 11) { + if (intel_ddi_is_tc(dev_priv, port)) { + encoder->enable_clock = icl_ddi_tc_enable_clock; + encoder->disable_clock = icl_ddi_tc_disable_clock; + } else { + encoder->enable_clock = icl_ddi_combo_enable_clock; + encoder->disable_clock = icl_ddi_combo_disable_clock; + } } else if (IS_CANNONLAKE(dev_priv)) { encoder->enable_clock = cnl_ddi_enable_clock; encoder->disable_clock = cnl_ddi_disable_clock; From patchwork Fri Feb 5 21:46:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12070997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 023AEC433E0 for ; Fri, 5 Feb 2021 21:47:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B826C64DFD for ; Fri, 5 Feb 2021 21:47:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B826C64DFD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 43C616F4E9; Fri, 5 Feb 2021 21:47:16 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id EAD0D6F4E9 for ; Fri, 5 Feb 2021 21:47:14 +0000 (UTC) IronPort-SDR: k8PssKhPHwe6lJY0xbHTSsbBpMH1zVb8llnOvmsDyubtdmP4uhd+oC24kiRRo65//in56EE/An VmGs7rAuqORw== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="245563282" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="245563282" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:14 -0800 IronPort-SDR: UeSyAbakjuKkaBV0Td1Ok8fSjkR+Mv8XsoDodMOiGt0Kwg3f4z8n6r+pDqwxQqwR8+UBUfEZJx 5W8NKMi0q8VA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="416154473" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by FMSMGA003.fm.intel.com with SMTP; 05 Feb 2021 13:47:12 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:11 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:27 +0200 Message-Id: <20210205214634.19341-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 08/15] drm/i915: Use intel_de_rmw() for DDI clock routing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The DDI clock routing programming is riddled with shared registers, forcing us to do a lot of RMW. Switch over to intel_de_rmw() to make that a bit less obnoxious. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 77 +++++++++--------------- 1 file changed, 28 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d6f94a1e320e..0cb20163fb1f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1603,7 +1603,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 val; /* * If we fail this, something went very wrong: first 2 PLLs should be @@ -1616,17 +1615,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); - drm_WARN_ON(&dev_priv->drm, - (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0); + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy)); - val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); - intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); - - val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0); mutex_unlock(&dev_priv->dpll.lock); } @@ -1638,8 +1632,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder) mutex_lock(&dev_priv->dpll.lock); - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, - DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), + 0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); mutex_unlock(&dev_priv->dpll.lock); } @@ -1650,7 +1644,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 val, mask, sel; + u32 mask, sel; i915_reg_t reg; if (IS_ALDERLAKE_S(dev_priv)) { @@ -1669,10 +1663,6 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, reg); - drm_WARN_ON(&dev_priv->drm, - (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); - /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -1683,13 +1673,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~mask; - val |= sel; - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); + intel_de_rmw(dev_priv, reg, mask, sel); - val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, reg, val); + intel_de_rmw(dev_priv, reg, + icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0); mutex_unlock(&dev_priv->dpll.lock); } @@ -1698,7 +1685,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 val; i915_reg_t reg; mutex_lock(&dev_priv->dpll.lock); @@ -1708,10 +1694,10 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) else reg = ICL_DPCLKA_CFGCR0; - val = intel_de_read(dev_priv, reg); - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); + mutex_lock(&dev_priv->dpll.lock); - intel_de_write(dev_priv, reg, val); + intel_de_rmw(dev_priv, reg, + 0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); mutex_unlock(&dev_priv->dpll.lock); } @@ -1916,25 +1902,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - u32 val; if (drm_WARN_ON(&i915->drm, !pll)) return; mutex_lock(&i915->dpll.lock); - val = intel_de_read(i915, DPCLKA_CFGCR0); - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); - intel_de_write(i915, DPCLKA_CFGCR0, val); + intel_de_rmw(i915, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), + DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port)); /* * "This step and the step before must be * done with separate register writes." */ - val = intel_de_read(i915, DPCLKA_CFGCR0); - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); - intel_de_write(i915, DPCLKA_CFGCR0, val); + intel_de_rmw(i915, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0); mutex_unlock(&i915->dpll.lock); } @@ -1944,8 +1927,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_write(i915, DPCLKA_CFGCR0, - intel_de_read(i915, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); + intel_de_rmw(i915, DPCLKA_CFGCR0, + 0, DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@ -1954,21 +1937,17 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - u32 val; if (drm_WARN_ON(&i915->drm, !pll)) return; mutex_lock(&i915->dpll.lock); - val = intel_de_read(i915, DPLL_CTRL2); - - val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | - DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); - val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | - DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - - intel_de_write(i915, DPLL_CTRL2, val); + intel_de_rmw(i915, DPLL_CTRL2, + DPLL_CTRL2_DDI_CLK_OFF(port) | + DPLL_CTRL2_DDI_CLK_SEL_MASK(port), + DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | + DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); mutex_unlock(&i915->dpll.lock); } @@ -1978,8 +1957,8 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_write(i915, DPLL_CTRL2, - intel_de_read(i915, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); + intel_de_rmw(i915, DPLL_CTRL2, + 0, DPLL_CTRL2_DDI_CLK_OFF(port)); } void hsw_ddi_enable_clock(struct intel_encoder *encoder, From patchwork Fri Feb 5 21:46:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 842BEC433DB for ; Fri, 5 Feb 2021 21:47:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2AA2D64FCA for ; Fri, 5 Feb 2021 21:47:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2AA2D64FCA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B559D6F4EA; Fri, 5 Feb 2021 21:47:19 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 51F2D6F4EA for ; Fri, 5 Feb 2021 21:47:18 +0000 (UTC) IronPort-SDR: nDjy5HSWL9Q2o37Q/7uP3FitDfv1VC/U9V9oW/+rCYo3aQ45GlzvqWIwCdH+F2bTfSK4KfqLp2 H1+l3SIGNZEA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="178933145" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="178933145" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:17 -0800 IronPort-SDR: POGMad7SqtNm/MnMnR5jFCPudeoEU5LaGLLGvjUeWOatuws1JjZ/0905mA03r3f+gIZAzXACZG 673u775CDfkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="360562275" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 05 Feb 2021 13:47:14 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:14 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:28 +0200 Message-Id: <20210205214634.19341-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 09/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The current code attempts to protect the RMWs into global clock routing registers with a mutex, but forgets to do so in a few places. Let's remedy that. Note that at the moment we serialize all modesets onto single wq, so this shouldn't actually matter. But maybe one day we wish to attempt parallel modesets again... Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 0cb20163fb1f..bd1eac282033 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1927,8 +1927,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; + mutex_lock(&i915->dpll.lock); + intel_de_rmw(i915, DPCLKA_CFGCR0, 0, DPCLKA_CFGCR0_DDI_CLK_OFF(port)); + + mutex_unlock(&i915->dpll.lock); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@ -1957,8 +1961,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; + mutex_lock(&i915->dpll.lock); + intel_de_rmw(i915, DPLL_CTRL2, 0, DPLL_CTRL2_DDI_CLK_OFF(port)); + + mutex_unlock(&i915->dpll.lock); } void hsw_ddi_enable_clock(struct intel_encoder *encoder, From patchwork Fri Feb 5 21:46:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88F32C433E0 for ; Fri, 5 Feb 2021 21:47:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 203C764FCF for ; Fri, 5 Feb 2021 21:47:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 203C764FCF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C21096F4EE; Fri, 5 Feb 2021 21:47:22 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EC686F4EC for ; Fri, 5 Feb 2021 21:47:21 +0000 (UTC) IronPort-SDR: uJlLmLqX4Y4qLcskKTkgibSCNAMNNDKw2L0w5OtrifUE1JRo4VZoWfBM+65o6rJYU5FMECoVH2 V7Edz3scMo4g== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="169167471" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="169167471" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:20 -0800 IronPort-SDR: mW5CUwRfkAYYKzsVGpJMlFuRrWtVSwIxbJOe+uNIZXIAkC28dZO+TGRBqBl7TglIO9vsb9jP27 y4d5FgpRGkIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="397616716" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 05 Feb 2021 13:47:18 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:17 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:29 +0200 Message-Id: <20210205214634.19341-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 10/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The other DDI .enable_clock() functions are trying to protect us against pll==NULL. A bit tempted to throw out all the WARNs as just unnecessary noise, but I guess they might have some use when poking around the shared_dpll code (not sure it wouldn't oops elsewhere though). So let's unify it all and sprinkle in the missing WARNs for icl/dg1. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bd1eac282033..c98bdf456958 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1604,6 +1604,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + if (drm_WARN_ON(&dev_priv->drm, !pll)) + return; + /* * If we fail this, something went very wrong: first 2 PLLs should be * used by first 2 phys and last 2 PLLs by last phys @@ -1661,6 +1664,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); } + if (drm_WARN_ON(&dev_priv->drm, !pll)) + return; + mutex_lock(&dev_priv->dpll.lock); /* From patchwork Fri Feb 5 21:46:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 638D0C433E0 for ; Fri, 5 Feb 2021 21:47:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2525B64FCE for ; Fri, 5 Feb 2021 21:47:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2525B64FCE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B71C76F4EC; Fri, 5 Feb 2021 21:47:25 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id E41116F4EC for ; Fri, 5 Feb 2021 21:47:24 +0000 (UTC) IronPort-SDR: TwSjU58Y1QhASjbTFgadw1bmMHplZSSj1KfFEiRS7OIEXKgYqVQ2kOlQUJWZqd6PTmTI7U+j84 y5Vd7JncihQg== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181556806" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181556806" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:23 -0800 IronPort-SDR: VPiCjUEvffDzFYwWW5Nn8X4hulCgPBWNB+yrxlTZFqzvUOSIbU05hkIueEXsmk0GS4RZ9/3Z/V 7E0xBGLk3yrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="358409709" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 05 Feb 2021 13:47:21 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:20 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:30 +0200 Message-Id: <20210205214634.19341-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 11/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä All the DPCLKA_CFGCR handling follows a common pattern. Let's extract that to a small helper that just takes a few parameters each caller can customize. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 108 +++++++++-------------- 1 file changed, 44 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c98bdf456958..8b7ef5f3ba03 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1597,11 +1597,37 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, return 0; } +static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, + u32 clk_sel_mask, u32 clk_sel, u32 clk_off) +{ + mutex_lock(&i915->dpll.lock); + + intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); + + /* + * "This step and the step before must be + * done with separate register writes." + */ + intel_de_rmw(i915, reg, clk_off, 0); + + mutex_unlock(&i915->dpll.lock); +} + +static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, + u32 clk_off) +{ + mutex_lock(&i915->dpll.lock); + + intel_de_rmw(i915, reg, 0, clk_off); + + mutex_unlock(&i915->dpll.lock); +} + static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (drm_WARN_ON(&dev_priv->drm, !pll)) @@ -1616,16 +1642,10 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) return; - mutex_lock(&dev_priv->dpll.lock); - - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), - DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), - DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy)); - - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), - DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0); - - mutex_unlock(&dev_priv->dpll.lock); + _cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static void dg1_ddi_disable_clock(struct intel_encoder *encoder) @@ -1633,19 +1653,15 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - mutex_lock(&dev_priv->dpll.lock); - - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), - 0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); - - mutex_unlock(&dev_priv->dpll.lock); + _cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); u32 mask, sel; i915_reg_t reg; @@ -1667,24 +1683,8 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, !pll)) return; - mutex_lock(&dev_priv->dpll.lock); - - /* - * Even though this register references DDIs, note that we - * want to pass the PHY rather than the port (DDI). For - * ICL, port=phy in all cases so it doesn't matter, but for - * EHL the bspec notes the following: - * - * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA - * Clock Select chooses the PLL for both DDIA and DDID and - * drives port A in all cases." - */ - intel_de_rmw(dev_priv, reg, mask, sel); - - intel_de_rmw(dev_priv, reg, - icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0); - - mutex_unlock(&dev_priv->dpll.lock); + _cnl_ddi_enable_clock(dev_priv, reg, mask, sel, + icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); } static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) @@ -1693,19 +1693,13 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) enum phy phy = intel_port_to_phy(dev_priv, encoder->port); i915_reg_t reg; - mutex_lock(&dev_priv->dpll.lock); - if (IS_ALDERLAKE_S(dev_priv)) reg = ADLS_DPCLKA_CFGCR(phy); else reg = ICL_DPCLKA_CFGCR0; - mutex_lock(&dev_priv->dpll.lock); - - intel_de_rmw(dev_priv, reg, - 0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); - - mutex_unlock(&dev_priv->dpll.lock); + _cnl_ddi_disable_clock(dev_priv, reg, + icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); } static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv, @@ -1912,20 +1906,10 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder, if (drm_WARN_ON(&i915->drm, !pll)) return; - mutex_lock(&i915->dpll.lock); - - intel_de_rmw(i915, DPCLKA_CFGCR0, - DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), - DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port)); - - /* - * "This step and the step before must be - * done with separate register writes." - */ - intel_de_rmw(i915, DPCLKA_CFGCR0, - DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0); - - mutex_unlock(&i915->dpll.lock); + _cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), + DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port), + DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } static void cnl_ddi_disable_clock(struct intel_encoder *encoder) @@ -1933,12 +1917,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; - mutex_lock(&i915->dpll.lock); - - intel_de_rmw(i915, DPCLKA_CFGCR0, - 0, DPCLKA_CFGCR0_DDI_CLK_OFF(port)); - - mutex_unlock(&i915->dpll.lock); + _cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, From patchwork Fri Feb 5 21:46:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC58FC433DB for ; Fri, 5 Feb 2021 21:47:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85B7864FCF for ; Fri, 5 Feb 2021 21:47:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85B7864FCF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 036996F4ED; Fri, 5 Feb 2021 21:47:28 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2098F6F4ED for ; Fri, 5 Feb 2021 21:47:27 +0000 (UTC) IronPort-SDR: JA/XQecTWdaa8jN7mOgUo+jD+RFikXRq8zU4WnJj+qvQ+AAIHWmSxtvLwgpoU3BmvogGnCigRl L4sbJ1a3TaQg== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="161246703" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="161246703" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:26 -0800 IronPort-SDR: iFzDM0gzMT7shyl1X1bBSiq9v5yJ8r618jYgJObZ8mXLNtMrcRgRgqFhOEplDG+oGDkcim+rMC irfVEI+tSk8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="373697577" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga008.fm.intel.com with SMTP; 05 Feb 2021 13:47:24 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:23 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:31 +0200 Message-Id: <20210205214634.19341-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 12/15] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Since .{enable,disable}_clock() are already vfuncs it's a bit silly to have if-ladders inside them. Just provide specialized version for adl-s and rkl so we don't need any of that. v2: s/dev_priv/i915/ (Lucas) Fix typos in platform names (Lucas) Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 91 ++++++++++++++++-------- 1 file changed, 62 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8b7ef5f3ba03..89962e412f18 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1623,6 +1623,56 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg mutex_unlock(&i915->dpll.lock); } +static void adls_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum phy phy = intel_port_to_phy(i915, encoder->port); + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + _cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), + ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), + pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), + ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); +} + +static void adls_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + _cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), + ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); +} + +static void rkl_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum phy phy = intel_port_to_phy(i915, encoder->port); + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, + RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), + RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); +} + +static void rkl_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, + RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); +} + static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1663,43 +1713,23 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 mask, sel; - i915_reg_t reg; - - if (IS_ALDERLAKE_S(dev_priv)) { - reg = ADLS_DPCLKA_CFGCR(phy); - mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); - sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); - } else if (IS_ROCKETLAKE(dev_priv)) { - reg = ICL_DPCLKA_CFGCR0; - mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } else { - reg = ICL_DPCLKA_CFGCR0; - mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } if (drm_WARN_ON(&dev_priv->drm, !pll)) return; - _cnl_ddi_enable_clock(dev_priv, reg, mask, sel, - icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); + _cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0, + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), + ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - i915_reg_t reg; - if (IS_ALDERLAKE_S(dev_priv)) - reg = ADLS_DPCLKA_CFGCR(phy); - else - reg = ICL_DPCLKA_CFGCR0; - - _cnl_ddi_disable_clock(dev_priv, reg, - icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); + _cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0, + ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv, @@ -4118,9 +4148,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_ALDERLAKE_S(dev_priv) || IS_ROCKETLAKE(dev_priv)) { - encoder->enable_clock = icl_ddi_combo_enable_clock; - encoder->disable_clock = icl_ddi_combo_disable_clock; + if (IS_ALDERLAKE_S(dev_priv)) { + encoder->enable_clock = adls_ddi_enable_clock; + encoder->disable_clock = adls_ddi_disable_clock; + } else if (IS_ROCKETLAKE(dev_priv)) { + encoder->enable_clock = rkl_ddi_enable_clock; + encoder->disable_clock = rkl_ddi_disable_clock; } else if (IS_DG1(dev_priv)) { encoder->enable_clock = dg1_ddi_enable_clock; encoder->disable_clock = dg1_ddi_disable_clock; From patchwork Fri Feb 5 21:46:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8260EC433DB for ; Fri, 5 Feb 2021 21:47:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3123F64FCF for ; Fri, 5 Feb 2021 21:47:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3123F64FCF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD0D76F4F0; Fri, 5 Feb 2021 21:47:31 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 953366F4F7 for ; Fri, 5 Feb 2021 21:47:30 +0000 (UTC) IronPort-SDR: gk/umngvVkTWXCV3917RLR7ZUWIefEs8gADCFPLiXsmAARc+QQg8BceQVj+/urF7FZwH7alNZk bcISB+H6BH8A== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="161246707" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="161246707" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:30 -0800 IronPort-SDR: I7bamG4u9lDkoSd74hMlXamRd8Z63D8RgA7PpSxMQHpwG330rQfSfKamYETVxnCAJVcnbVGRZn 4Sh05ql2/02A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394026128" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 05 Feb 2021 13:47:28 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:26 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:32 +0200 Message-Id: <20210205214634.19341-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 13/15] drm/i915: Use .disable_clock() for pll sanitation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Instead of every new platform having yet another masive copy of the whole PLL sanitation code, let's just reuse the .disable_clock() hook for this purpose. We do need to plug this into the ICL+ DSI code for that, but fortunately it already has a suitable function we can use. We do lose the debug message though on account of not bothering to check if the clock is actually enabled or not before turning it off. We could introduce yet another vfunc to query the current state, but not sure it's worth the hassle? Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/icl_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 92 +----------------------- 2 files changed, 3 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 9d245a689323..a7edfaa09035 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1940,6 +1940,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) encoder->pipe_mask = ~0; encoder->power_domain = POWER_DOMAIN_PORT_DSI; encoder->get_power_domains = gen11_dsi_get_power_domains; + encoder->disable_clock = gen11_dsi_gate_clocks; /* register DSI connector with DRM subsystem */ drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 89962e412f18..967871c2bf1e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1580,23 +1580,6 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); } -static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, - enum phy phy) -{ - if (IS_ROCKETLAKE(dev_priv)) { - return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - } else if (intel_phy_is_combo(dev_priv, phy)) { - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - } else if (intel_phy_is_tc(dev_priv, phy)) { - enum tc_port tc_port = intel_port_to_tc(dev_priv, - (enum port)phy); - - return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); - } - - return 0; -} - static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) { @@ -1732,75 +1715,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv, - u32 port_mask, bool ddi_clk_needed) -{ - enum port port; - u32 val; - - for_each_port_masked(port, port_mask) { - enum phy phy = intel_port_to_phy(dev_priv, port); - bool ddi_clk_off; - - val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); - ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - - if (ddi_clk_needed == !ddi_clk_off) - continue; - - /* - * Punt on the case now where clock is gated, but it would - * be needed by the port. Something else is really broken then. - */ - if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) - continue; - - drm_notice(&dev_priv->drm, - "PHY %c is disabled with an ungated DDI clock, gate it\n", - phy_name(phy)); - val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); - } -} - -static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, - u32 port_mask, bool ddi_clk_needed) -{ - enum port port; - bool ddi_clk_off; - u32 val; - i915_reg_t reg; - - for_each_port_masked(port, port_mask) { - enum phy phy = intel_port_to_phy(dev_priv, port); - - if (IS_ALDERLAKE_S(dev_priv)) - reg = ADLS_DPCLKA_CFGCR(phy); - else - reg = ICL_DPCLKA_CFGCR0; - - val = intel_de_read(dev_priv, reg); - ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, - phy); - - if (ddi_clk_needed == !ddi_clk_off) - continue; - - /* - * Punt on the case now where clock is gated, but it would - * be needed by the port. Something else is really broken then. - */ - if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) - continue; - - drm_notice(&dev_priv->drm, - "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", - phy_name(phy)); - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, reg, val); - } -} - void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1853,10 +1767,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) ddi_clk_needed = false; } - if (IS_DG1(dev_priv)) - dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); - else - icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); + if (!ddi_clk_needed && encoder->disable_clock) + encoder->disable_clock(encoder); } static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, From patchwork Fri Feb 5 21:46:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C947C433E6 for ; Fri, 5 Feb 2021 21:47:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3787464FCE for ; Fri, 5 Feb 2021 21:47:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3787464FCE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBBC86F4F2; Fri, 5 Feb 2021 21:47:35 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C3396F4F2 for ; Fri, 5 Feb 2021 21:47:33 +0000 (UTC) IronPort-SDR: qCbkMgJu8amTGfCmsQkM8ibpRv3hjeL4Yxt/eWuRETMOeCQ8+uW0iwYKO1v7KcOkOJvt+/8zLW SkqdIT5R4YxA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="169167489" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="169167489" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:33 -0800 IronPort-SDR: frZ/VWhDHefHixuV6hSQOk3bhgDxKO1cDkJUEdpyZBDH12jUmSIgwidMcGoToO9tuOaFCncoLc Fi12LmJzUwPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="434612902" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 05 Feb 2021 13:47:31 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:30 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:33 +0200 Message-Id: <20210205214634.19341-15-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 14/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move icl_sanitize_encoder_pll_mapping() out from the middle of the .{enable,disable}_clock() functions. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 112 +++++++++++------------ 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 967871c2bf1e..d4b9410110fd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1715,62 +1715,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 port_mask; - bool ddi_clk_needed; - - /* - * In case of DP MST, we sanitize the primary encoder only, not the - * virtual ones. - */ - if (encoder->type == INTEL_OUTPUT_DP_MST) - return; - - if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { - u8 pipe_mask; - bool is_mst; - - intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); - /* - * In the unlikely case that BIOS enables DP in MST mode, just - * warn since our MST HW readout is incomplete. - */ - if (drm_WARN_ON(&dev_priv->drm, is_mst)) - return; - } - - port_mask = BIT(encoder->port); - ddi_clk_needed = encoder->base.crtc; - - if (encoder->type == INTEL_OUTPUT_DSI) { - struct intel_encoder *other_encoder; - - port_mask = intel_dsi_encoder_ports(encoder); - /* - * Sanity check that we haven't incorrectly registered another - * encoder using any of the ports of this DSI encoder. - */ - for_each_intel_encoder(&dev_priv->drm, other_encoder) { - if (other_encoder == encoder) - continue; - - if (drm_WARN_ON(&dev_priv->drm, - port_mask & BIT(other_encoder->port))) - return; - } - /* - * For DSI we keep the ddi clocks gated - * except during enable/disable sequence. - */ - ddi_clk_needed = false; - } - - if (!ddi_clk_needed && encoder->disable_clock) - encoder->disable_clock(encoder); -} - static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1931,6 +1875,62 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder) encoder->disable_clock(encoder); } +void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + u32 port_mask; + bool ddi_clk_needed; + + /* + * In case of DP MST, we sanitize the primary encoder only, not the + * virtual ones. + */ + if (encoder->type == INTEL_OUTPUT_DP_MST) + return; + + if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { + u8 pipe_mask; + bool is_mst; + + intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); + /* + * In the unlikely case that BIOS enables DP in MST mode, just + * warn since our MST HW readout is incomplete. + */ + if (drm_WARN_ON(&dev_priv->drm, is_mst)) + return; + } + + port_mask = BIT(encoder->port); + ddi_clk_needed = encoder->base.crtc; + + if (encoder->type == INTEL_OUTPUT_DSI) { + struct intel_encoder *other_encoder; + + port_mask = intel_dsi_encoder_ports(encoder); + /* + * Sanity check that we haven't incorrectly registered another + * encoder using any of the ports of this DSI encoder. + */ + for_each_intel_encoder(&dev_priv->drm, other_encoder) { + if (other_encoder == encoder) + continue; + + if (drm_WARN_ON(&dev_priv->drm, + port_mask & BIT(other_encoder->port))) + return; + } + /* + * For DSI we keep the ddi clocks gated + * except during enable/disable sequence. + */ + ddi_clk_needed = false; + } + + if (!ddi_clk_needed && encoder->disable_clock) + encoder->disable_clock(encoder); +} + static void icl_program_mg_dp_mode(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) From patchwork Fri Feb 5 21:46:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B023C433E0 for ; Fri, 5 Feb 2021 21:47:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10CE364FCF for ; Fri, 5 Feb 2021 21:47:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10CE364FCF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 93D716F4F1; Fri, 5 Feb 2021 21:47:46 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id C9BF56F4F3 for ; Fri, 5 Feb 2021 21:47:44 +0000 (UTC) IronPort-SDR: J/uEC+NthmsgY7bWkYQIZfu05O44y6CRmShEUMZK61rUnbVQ8Aioy3FEzSDaS7aeSYJAkSmZ3S 0jk92WXADuFA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="180716627" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="180716627" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:39 -0800 IronPort-SDR: ZWk+IRuwIvjRQyuxRI9vbS6CCht8zUX3OoCUxL/PaFftI+fYAAUSA4nTpLLDl4ZLws77L64/JF GrzNTiU/uIuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="484474681" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 05 Feb 2021 13:47:37 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:33 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:34 +0200 Message-Id: <20210205214634.19341-16-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 15/15] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Convert the remaining 'dev_priv's to 'i915's in the DDI clock routing functions. Cc: Lucas De Marchi Signed-off-by: Ville Syrjälä Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_ddi.c | 38 ++++++++++++------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d4b9410110fd..0f0e68c99589 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1659,23 +1659,23 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder) static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + enum phy phy = intel_port_to_phy(i915, encoder->port); - if (drm_WARN_ON(&dev_priv->drm, !pll)) + if (drm_WARN_ON(&i915->drm, !pll)) return; /* * If we fail this, something went very wrong: first 2 PLLs should be * used by first 2 phys and last 2 PLLs by last phys */ - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(&i915->drm, (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) return; - _cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy), + _cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1683,24 +1683,24 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, static void dg1_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); - _cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy), + _cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + enum phy phy = intel_port_to_phy(i915, encoder->port); - if (drm_WARN_ON(&dev_priv->drm, !pll)) + if (drm_WARN_ON(&i915->drm, !pll)) return; - _cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0, + _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1708,10 +1708,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); - _cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0, + _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1877,7 +1877,7 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder) void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); u32 port_mask; bool ddi_clk_needed; @@ -1897,7 +1897,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * In the unlikely case that BIOS enables DP in MST mode, just * warn since our MST HW readout is incomplete. */ - if (drm_WARN_ON(&dev_priv->drm, is_mst)) + if (drm_WARN_ON(&i915->drm, is_mst)) return; } @@ -1912,11 +1912,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * Sanity check that we haven't incorrectly registered another * encoder using any of the ports of this DSI encoder. */ - for_each_intel_encoder(&dev_priv->drm, other_encoder) { + for_each_intel_encoder(&i915->drm, other_encoder) { if (other_encoder == encoder) continue; - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(&i915->drm, port_mask & BIT(other_encoder->port))) return; }