From patchwork Sat Feb 6 02:09:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73751C433E0 for ; Sat, 6 Feb 2021 02:10:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2274A65006 for ; Sat, 6 Feb 2021 02:10:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2274A65006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB16E6E3B7; Sat, 6 Feb 2021 02:10:35 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC2A66E3B7 for ; Sat, 6 Feb 2021 02:10:34 +0000 (UTC) IronPort-SDR: ttZifcu8MwFqyhwoEBUkuM9N8gVh2OJrR+fBySm8zup86R7ZeEAAwbyyuhxMm2LSPW1jY3EOZl 8z2C5mCua4Nw== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577449" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577449" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:34 -0800 IronPort-SDR: y8F14SktODfNv4djSwsBeZhhib43AysMWkkFLjvCY6T7rA0GUaWLGdcSQpfFZ1K0zjCCvPHXHn AauCBDdk0FRw== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141238" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:34 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:12 -0800 Message-Id: <20210206020925.36729-2-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This will be used for communication between the i915 driver and the mei one. Defining it in a stand-alone patch to avoid circualr dependedencies between the patches modifying the 2 drivers. Split out from an original patch from Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio --- include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 ++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 include/drm/i915_pxp_tee_interface.h diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h index 55c3b123581b..c1e2a43d2d1e 100644 --- a/include/drm/i915_component.h +++ b/include/drm/i915_component.h @@ -29,6 +29,7 @@ enum i915_component_type { I915_COMPONENT_AUDIO = 1, I915_COMPONENT_HDCP, + I915_COMPONENT_PXP }; /* MAX_PORT is the number of port diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h new file mode 100644 index 000000000000..0efd14702b4b --- /dev/null +++ b/include/drm/i915_pxp_tee_interface.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + * + * Authors: + * Vitaly Lubart + */ + +#ifndef _I915_PXP_TEE_INTERFACE_H_ +#define _I915_PXP_TEE_INTERFACE_H_ + +#include +#include + +/** + * struct i915_pxp_component_ops - ops for PXP services. + * @owner: Module providing the ops + * @send: sends data to PXP + * @receive: receives data from PXP + */ +struct i915_pxp_component_ops { + /** + * @owner: owner of the module provding the ops + */ + struct module *owner; + + int (*send)(struct device *dev, const void *message, size_t size); + int (*recv)(struct device *dev, void *buffer, size_t size); +}; + +/** + * struct i915_pxp_component_master - Used for communication between i915 + * and TEE drivers for the PXP services + * @tee_dev: device that provide the PXP service from TEE Bus. + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver. + */ +struct i915_pxp_comp_master { + struct device *tee_dev; + const struct i915_pxp_component_ops *ops; + + /* To protect the above members. */ + struct mutex mutex; +}; + +#endif /* _I915_TEE_PXP_INTERFACE_H_ */ From patchwork Sat Feb 6 02:09:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E20FC433DB for ; Sat, 6 Feb 2021 02:10:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDEA865006 for ; Sat, 6 Feb 2021 02:10:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CDEA865006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56E4D6E3C6; Sat, 6 Feb 2021 02:10:37 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id E0CC46E3C6 for ; Sat, 6 Feb 2021 02:10:35 +0000 (UTC) IronPort-SDR: J1UsytUcIIojjBwsMJsiSxlFswcCBVhnMe8Yjn685cuLe0i/n+pO7ZouZSHXfPcHqRwppAI4OL NlXWvqw1wZ4A== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577450" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577450" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:35 -0800 IronPort-SDR: Jk/viJG8CMqCBqxdjcVbZzL3OIamg8mqA4NUpxP/a2ljJvoD7QS0Qzy2YdCOtikno//X27Go2l L6AttR3LSGDw== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141261" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:35 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:13 -0800 Message-Id: <20210206020925.36729-3-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomas Winkler , Vitaly Lubart Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Vitaly Lubart Export PAVP client to work with i915_cp driver, for binding it uses kernel component framework. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 ++ drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++ drivers/misc/mei/pxp/mei_pxp.h | 18 +++ 6 files changed, 271 insertions(+) create mode 100644 drivers/misc/mei/pxp/Kconfig create mode 100644 drivers/misc/mei/pxp/Makefile create mode 100644 drivers/misc/mei/pxp/mei_pxp.c create mode 100644 drivers/misc/mei/pxp/mei_pxp.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index f5fd5b786607..0e0bcd0da852 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -47,3 +47,5 @@ config INTEL_MEI_TXE Intel Bay Trail source "drivers/misc/mei/hdcp/Kconfig" +source "drivers/misc/mei/pxp/Kconfig" + diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index f1c76f7ee804..d8e5165917f2 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o CFLAGS_mei-trace.o = -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/ +obj-$(CONFIG_INTEL_MEI_PXP) += pxp/ diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig new file mode 100644 index 000000000000..4029b96afc04 --- /dev/null +++ b/drivers/misc/mei/pxp/Kconfig @@ -0,0 +1,13 @@ + +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +config INTEL_MEI_PXP + tristate "Intel PXP services of ME Interface" + select INTEL_MEI_ME + depends on DRM_I915 + help + MEI Support for PXP Services on Intel platforms. + + Enables the ME FW services required for PXP support through + I915 display driver of Intel. diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile new file mode 100644 index 000000000000..0329950d5794 --- /dev/null +++ b/drivers/misc/mei/pxp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +# Makefile - PXP client driver for Intel MEI Bus Driver. + +obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c new file mode 100644 index 000000000000..bd31fce1e6ba --- /dev/null +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2020 Intel Corporation + */ + +/** + * DOC: MEI_PXP Client Driver + * + * The mei_pxp driver acts as a translation layer between PXP + * protocol implementer (I915) and ME FW by translating PXP + * negotiation messages to ME FW command payloads and vice versa. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mei_pxp.h" + +/** + * mei_pxp_send_message() - Sends a PXP message to ME FW. + * @dev: device corresponding to the mei_cl_device + * @message: a message buffer to send + * @size: size of the message + * Return: 0 on Success, <0 on Failure + */ +static int +mei_pxp_send_message(struct device *dev, const void *message, size_t size) +{ + struct mei_cl_device *cldev; + ssize_t byte; + + if (!dev || !message) + return -EINVAL; + + cldev = to_mei_cl_device(dev); + + /* temporary drop const qualifier till the API is fixed */ + byte = mei_cldev_send(cldev, (u8 *)message, size); + if (byte < 0) { + dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte); + return byte; + } + + return 0; +} + +/** + * mei_pxp_receive_message() - Receives a PXP message from ME FW. + * @dev: device corresponding to the mei_cl_device + * @buffer: a message buffer to contain the received message + * @size: size of the buffer + * Return: bytes sent on Success, <0 on Failure + */ +static int +mei_pxp_receive_message(struct device *dev, void *buffer, size_t size) +{ + struct mei_cl_device *cldev; + ssize_t byte; + + if (!dev || !buffer) + return -EINVAL; + + cldev = to_mei_cl_device(dev); + + byte = mei_cldev_recv(cldev, buffer, size); + if (byte < 0) { + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte); + return byte; + } + + return byte; +} + +static const struct i915_pxp_component_ops mei_pxp_ops = { + .owner = THIS_MODULE, + .send = mei_pxp_send_message, + .recv = mei_pxp_receive_message, +}; + +static int mei_component_master_bind(struct device *dev) +{ + struct mei_cl_device *cldev = to_mei_cl_device(dev); + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + int ret; + + dev_dbg(dev, "%s\n", __func__); + comp_master->ops = &mei_pxp_ops; + comp_master->tee_dev = dev; + ret = component_bind_all(dev, comp_master); + if (ret < 0) + return ret; + + return 0; +} + +static void mei_component_master_unbind(struct device *dev) +{ + struct mei_cl_device *cldev = to_mei_cl_device(dev); + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + + dev_dbg(dev, "%s\n", __func__); + component_unbind_all(dev, comp_master); +} + +static const struct component_master_ops mei_component_master_ops = { + .bind = mei_component_master_bind, + .unbind = mei_component_master_unbind, +}; + +/** + * mei_pxp_component_match - compare function for matching mei pxp. + * + * The function checks if the driver is i915, the subcomponent is PXP + * and the grand parent of pxp and the parent of i915 are the same + * PCH device. + * + * @dev: master device + * @subcomponent: subcomponent to match (I915_COMPONENT_PXP) + * @data: compare data (mei pxp device) + * + * Return: + * * 1 - if components match + * * 0 - otherwise + */ +static int mei_pxp_component_match(struct device *dev, int subcomponent, + void *data) +{ + struct device *base = data; + + if (subcomponent != I915_COMPONENT_PXP) + return 0; + + if (strcmp(dev->driver->name, "i915") == 0) { + base = base->parent; + if (!base) + return 0; + + base = base->parent; + dev = dev->parent; + return (base && dev && dev == base); + } + + return 0; +} + +static int mei_pxp_probe(struct mei_cl_device *cldev, + const struct mei_cl_device_id *id) +{ + struct i915_pxp_comp_master *comp_master; + struct component_match *master_match; + int ret; + + ret = mei_cldev_enable(cldev); + if (ret < 0) { + dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret); + goto enable_err_exit; + } + + comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL); + if (!comp_master) { + ret = -ENOMEM; + goto err_exit; + } + + master_match = NULL; + component_match_add_typed(&cldev->dev, &master_match, + mei_pxp_component_match, &cldev->dev); + if (IS_ERR_OR_NULL(master_match)) { + ret = -ENOMEM; + goto err_exit; + } + + mei_cldev_set_drvdata(cldev, comp_master); + ret = component_master_add_with_match(&cldev->dev, + &mei_component_master_ops, + master_match); + if (ret < 0) { + dev_err(&cldev->dev, "Master comp add failed %d\n", ret); + goto err_exit; + } + + return 0; + +err_exit: + mei_cldev_set_drvdata(cldev, NULL); + kfree(comp_master); + mei_cldev_disable(cldev); +enable_err_exit: + return ret; +} + +static int mei_pxp_remove(struct mei_cl_device *cldev) +{ + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + + component_master_del(&cldev->dev, &mei_component_master_ops); + kfree(comp_master); + mei_cldev_set_drvdata(cldev, NULL); + + return mei_cldev_disable(cldev); +} + +/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/ +#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \ + 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1) + +static struct mei_cl_device_id mei_pxp_tbl[] = { + { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(mei, mei_pxp_tbl); + +static struct mei_cl_driver mei_pxp_driver = { + .id_table = mei_pxp_tbl, + .name = KBUILD_MODNAME, + .probe = mei_pxp_probe, + .remove = mei_pxp_remove, +}; + +module_mei_cl_driver(mei_pxp_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MEI PXP"); diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h new file mode 100644 index 000000000000..e7b15373fefd --- /dev/null +++ b/drivers/misc/mei/pxp/mei_pxp.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright © 2020 Intel Corporation + * + * Authors: + * Vitaly Lubart + */ + +#ifndef __MEI_PXP_H__ +#define __MEI_PXP_H__ + +/* me_pxp_status: Enumeration of all PXP Status Codes */ +enum me_pxp_status { + ME_PXP_STATUS_SUCCESS = 0x0000, + +}; + +#endif /* __MEI_PXP_H__ */ From patchwork Sat Feb 6 02:09:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26CECC433E6 for ; Sat, 6 Feb 2021 02:10:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E240D65006 for ; Sat, 6 Feb 2021 02:10:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E240D65006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72A886F54C; Sat, 6 Feb 2021 02:10:39 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 836E26E3C6 for ; Sat, 6 Feb 2021 02:10:36 +0000 (UTC) IronPort-SDR: G9OUUEvK5P5z5nG0a9NfM5x72TDPPguf8QzGIssvl0Pa3cKgRINFpBO+vdFfLoliVpcvZk3Zlq aekOJ9c1DL7Q== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577451" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577451" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:36 -0800 IronPort-SDR: DKSdvd5JZdAzR54N+z5l+yrR20HL5yzmSdgUp1pYJeXb9pjdd2M69txxvWKZajdu+7QDaZDskN 1YUvycoEEM4w== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141283" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:36 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:14 -0800 Message-Id: <20210206020925.36729-4-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Ahead of the PXP implementation, define the relevant define flag and kconfig option. Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/Kconfig | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 1e1cb245fca7..c55e58bdbe0b 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -130,6 +130,17 @@ config DRM_I915_GVT_KVMGT Choose this option if you want to enable KVMGT support for Intel GVT-g. +config DRM_I915_PXP + bool "Enable Intel PXP support for Intel Gen12+ platform" + depends on DRM_I915 + depends on INTEL_MEI && INTEL_MEI_PXP + default y + help + PXP (Protected Xe Path) is an i915 component, available on GEN12+ + GPUs, that helps to establish the hardware protected session and + manage the status of the alive software session, as well as its life + cycle. + menu "drm/i915 Debugging" depends on DRM_I915 depends on EXPERT diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a2fd7e5039b3..fe1ff025f961 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1779,6 +1779,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) #define HAS_VRR(i915) (INTEL_GEN(i915) >= 12) +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \ + INTEL_INFO(dev_priv)->has_pxp) && \ + VDBOX_MASK(&dev_priv->gt) + /* Only valid when HAS_DISPLAY() is true */ #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index e6ca1023ffcf..54891f7655e4 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -127,6 +127,7 @@ enum intel_ppgtt_type { func(has_logical_ring_elsq); \ func(has_master_unit_irq); \ func(has_pooled_eu); \ + func(has_pxp); \ func(has_rc6); \ func(has_rc6p); \ func(has_rps); \ From patchwork Sat Feb 6 02:09:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C6A7C433E6 for ; Sat, 6 Feb 2021 02:10:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB8CE65006 for ; Sat, 6 Feb 2021 02:10:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB8CE65006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E1A9D6F549; Sat, 6 Feb 2021 02:10:38 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B26B6E3D3 for ; Sat, 6 Feb 2021 02:10:37 +0000 (UTC) IronPort-SDR: MNJj4eKyTHWY107QS5ZAbui7O1vMeyiM9ZyB5Q54A8pYVV6w4jUcC3LF/ckiWLvxoa4ghuH8u9 KHSynW79jiDA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577454" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577454" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:37 -0800 IronPort-SDR: mC6Di11E+TOQwM7LIEk1HyImWk0eDhnCwmtN7zNXxJd0KhMjHAepX8wndQr0/VYbfI7EQf/94P L/O+SZaMhkfA== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141306" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:37 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:15 -0800 Message-Id: <20210206020925.36729-5-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The context is required to send the session termination commands to the VCS, which will be implemented in a follow-up patch. We can also use the presence of the context as a check of pxp initialization completion. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Makefile | 4 ++ drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 61 ++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 +++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++ 6 files changed, 123 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index ce01634d4ea7..e2677e8c03e8 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -268,6 +268,10 @@ i915-y += \ i915-y += i915_perf.o +# Protected execution platform (PXP) support +i915-$(CONFIG_DRM_I915_PXP) += \ + pxp/intel_pxp.o + # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o i915-$(CONFIG_DRM_I915_SELFTEST) += \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ca76f93bc03d..daf61db620d6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -20,6 +20,7 @@ #include "intel_uncore.h" #include "intel_pm.h" #include "shmem_utils.h" +#include "pxp/intel_pxp.h" void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) { @@ -624,6 +625,8 @@ int intel_gt_init(struct intel_gt *gt) if (err) goto err_gt; + intel_pxp_init(>->pxp); + goto out_fw; err_gt: __intel_gt_disable(gt); @@ -658,6 +661,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt) intel_rps_driver_unregister(>->rps); + intel_pxp_fini(>->pxp); + /* * Upon unregistering the device to prevent any new users, cancel * all in-flight requests so that we can quickly unbind the active diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 626af37c7790..324d267eee15 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -23,6 +23,7 @@ #include "intel_rc6_types.h" #include "intel_rps_types.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_types.h" struct drm_i915_private; struct i915_ggtt; @@ -145,6 +146,8 @@ struct intel_gt { /* Slice/subslice/EU info */ struct sseu_dev_info sseu; } info; + + struct intel_pxp pxp; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c new file mode 100644 index 000000000000..4ddc8a71a3e7 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ +#include "intel_pxp.h" +#include "gt/intel_context.h" +#include "i915_drv.h" + +static int create_vcs_context(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + struct intel_context *ce = NULL; + int i; + + /* + * Find the first VCS engine present. We're guaranteed there is one + * if we're in this function due to the check in has_pxp + */ + for (i = 0; i < I915_MAX_VCS && !ce; i++) + if (HAS_ENGINE(gt, _VCS(i))) + ce = intel_context_create(gt->engine[_VCS(i)]); + + if (IS_ERR(ce)) { + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n"); + return PTR_ERR(ce); + } + + pxp->ce = ce; + + return 0; +} + +static void destroy_vcs_context(struct intel_pxp *pxp) +{ + intel_context_put(fetch_and_zero(&pxp->ce)); +} + +void intel_pxp_init(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + int ret; + + if (!HAS_PXP(gt->i915)) + return; + + ret = create_vcs_context(pxp); + if (ret) + return; + + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); + + return; +} + +void intel_pxp_fini(struct intel_pxp *pxp) +{ + if (!intel_pxp_is_enabled(pxp)) + return; + + destroy_vcs_context(pxp); +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h new file mode 100644 index 000000000000..e2acd06402cd --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_H__ +#define __INTEL_PXP_H__ + +#include "gt/intel_gt_types.h" +#include "intel_pxp_types.h" + +static inline struct intel_gt *pxp_to_gt(struct intel_pxp *pxp) +{ + return container_of(pxp, struct intel_gt, pxp); +} + +static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp) +{ + return pxp->ce; +} + +#ifdef CONFIG_DRM_I915_PXP +void intel_pxp_init(struct intel_pxp *pxp); +void intel_pxp_fini(struct intel_pxp *pxp); +#else +static inline void intel_pxp_init(struct intel_pxp *pxp) +{ +} + +static inline void intel_pxp_fini(struct intel_pxp *pxp) +{ +} +#endif + +#endif /* __INTEL_PXP_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h new file mode 100644 index 000000000000..bd12c520e60a --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_TYPES_H__ +#define __INTEL_PXP_TYPES_H__ + +struct intel_context; + +struct intel_pxp { + struct intel_context *ce; +}; + +#endif /* __INTEL_PXP_TYPES_H__ */ From patchwork Sat Feb 6 02:09:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20413C433E0 for ; Sat, 6 Feb 2021 02:10:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D8FCC6501C for ; Sat, 6 Feb 2021 02:10:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D8FCC6501C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3D1D6F542; Sat, 6 Feb 2021 02:10:38 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7389D6E3D3 for ; Sat, 6 Feb 2021 02:10:38 +0000 (UTC) IronPort-SDR: SnGjr+VJzcAOO3KgeckKrpyK+CYOsbvfA06IpS42jVEFPr7lZN3UTQpLrMeRxryUmR/G8ea3JV BI9bd3J9YbsA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577457" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577457" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:38 -0800 IronPort-SDR: YXY0BiZr2M3o2wL2QqSyM2gn4+uZUJFuJfcgoR7lDYmszjhDutFVWhhZE72cbt8zdwkXKw6lJs M4q0UEC7fe0g== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141332" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:37 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:16 -0800 Message-Id: <20210206020925.36729-6-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Z , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set the KCR init during the boot time, which is required by hardware, to allow us doing further protection operation such as sending commands to GPU or TEE. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 +++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 4ddc8a71a3e7..950daee5b907 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -6,6 +6,24 @@ #include "gt/intel_context.h" #include "i915_drv.h" +/* KCR register definitions */ +#define KCR_INIT _MMIO(0x320f0) + +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) + +static void kcr_pxp_enable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + +static void kcr_pxp_disable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + static int create_vcs_context(struct intel_pxp *pxp) { struct intel_gt *gt = pxp_to_gt(pxp); @@ -43,19 +61,28 @@ void intel_pxp_init(struct intel_pxp *pxp) if (!HAS_PXP(gt->i915)) return; + kcr_pxp_enable(gt); + ret = create_vcs_context(pxp); if (ret) - return; + goto out_kcr; drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); return; + +out_kcr: + kcr_pxp_disable(gt); } void intel_pxp_fini(struct intel_pxp *pxp) { + struct intel_gt *gt = pxp_to_gt(pxp); + if (!intel_pxp_is_enabled(pxp)) return; destroy_vcs_context(pxp); + + kcr_pxp_disable(gt); } From patchwork Sat Feb 6 02:09:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 098BDC433DB for ; Sat, 6 Feb 2021 02:10:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C504E65006 for ; Sat, 6 Feb 2021 02:10:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C504E65006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 490366E3D3; Sat, 6 Feb 2021 02:10:47 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E95C6F54D for ; Sat, 6 Feb 2021 02:10:39 +0000 (UTC) IronPort-SDR: 7NBUVu8sDL0GPdllBCLfenLLTkY2hNF6zW65Iod4v2qIP7eq7AUEiNuZJEAJjzznLg+N5YG9eH zsHe3CHsMiIg== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577458" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577458" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:39 -0800 IronPort-SDR: mSWp2rkQXeQ1hUOztDtblH/DF96QFP+Z0QUVTY7Ihcwu3THOgJefu14rRPGwwJM3FhTj094+Wt flGAdInx9A4A== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141364" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:39 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:17 -0800 Message-Id: <20210206020925.36729-7-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Huang, Sean Z" , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Huang, Sean Z" Implement the funcs to create the TEE channel, so kernel can send the TEE commands directly to TEE for creating the arbitrary (default) session. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 86 ++++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 ++++ 6 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index e2677e8c03e8..f0ba95a2e4fc 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -270,7 +270,8 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ - pxp/intel_pxp.o + pxp/intel_pxp.o \ + pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 41eea02a9285..d1344eb6c849 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -325,6 +325,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) mutex_init(&dev_priv->wm.wm_mutex); mutex_init(&dev_priv->pps_mutex); mutex_init(&dev_priv->hdcp_comp_mutex); + mutex_init(&dev_priv->pxp_tee_comp_mutex); i915_memcpy_init_early(dev_priv); intel_runtime_pm_init_early(&dev_priv->runtime_pm); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fe1ff025f961..779eb38add40 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1205,6 +1205,12 @@ struct drm_i915_private { /* Mutex to protect the above hdcp component related values. */ struct mutex hdcp_comp_mutex; + struct i915_pxp_comp_master *pxp_tee_master; + bool pxp_tee_comp_added; + + /* Mutex to protect the above pxp_tee component related values. */ + struct mutex pxp_tee_comp_mutex; + I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) /* diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 950daee5b907..3f3eeadb7931 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -3,6 +3,7 @@ * Copyright(c) 2020 Intel Corporation. */ #include "intel_pxp.h" +#include "intel_pxp_tee.h" #include "gt/intel_context.h" #include "i915_drv.h" @@ -67,10 +68,16 @@ void intel_pxp_init(struct intel_pxp *pxp) if (ret) goto out_kcr; + ret = intel_pxp_tee_component_init(pxp); + if (ret) + goto out_context; + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); return; +out_context: + destroy_vcs_context(pxp); out_kcr: kcr_pxp_disable(gt); } @@ -82,7 +89,10 @@ void intel_pxp_fini(struct intel_pxp *pxp) if (!intel_pxp_is_enabled(pxp)) return; + intel_pxp_tee_component_fini(pxp); + destroy_vcs_context(pxp); kcr_pxp_disable(gt); + } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c new file mode 100644 index 000000000000..1d2b8c346161 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include +#include "drm/i915_pxp_tee_interface.h" +#include "drm/i915_component.h" +#include "i915_drv.h" +#include "intel_pxp.h" +#include "intel_pxp_tee.h" + +/** + * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee + * @i915_kdev: pointer to i915 kernel device + * @tee_kdev: pointer to tee kernel device + * @data: pointer to pxp_tee_master containing the function pointers + * + * This bind function is called during the system boot or resume from system sleep. + * + * Return: return 0 if successful. + */ +static int i915_pxp_tee_component_bind(struct device *i915_kdev, + struct device *tee_kdev, void *data) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_master = (struct i915_pxp_comp_master *)data; + i915->pxp_tee_master->tee_dev = tee_kdev; + mutex_unlock(&i915->pxp_tee_comp_mutex); + + return 0; +} + +static void i915_pxp_tee_component_unbind(struct device *i915_kdev, + struct device *tee_kdev, void *data) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_master = NULL; + mutex_unlock(&i915->pxp_tee_comp_mutex); +} + +static const struct component_ops i915_pxp_tee_component_ops = { + .bind = i915_pxp_tee_component_bind, + .unbind = i915_pxp_tee_component_unbind, +}; + +int intel_pxp_tee_component_init(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = pxp_to_gt(pxp); + struct drm_i915_private *i915 = gt->i915; + + ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops, + I915_COMPONENT_PXP); + if (ret < 0) { + drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret); + return ret; + } + + mutex_lock(&i915->pxp_tee_comp_mutex); + i915->pxp_tee_comp_added = true; + mutex_unlock(&i915->pxp_tee_comp_mutex); + + return 0; +} + +void intel_pxp_tee_component_fini(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + struct drm_i915_private *i915 = gt->i915; + + mutex_lock(&i915->pxp_tee_comp_mutex); + if (!i915->pxp_tee_comp_added) { + mutex_unlock(&i915->pxp_tee_comp_mutex); + return; + } + + i915->pxp_tee_comp_added = false; + mutex_unlock(&i915->pxp_tee_comp_mutex); + + component_del(i915->drm.dev, &i915_pxp_tee_component_ops); +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h new file mode 100644 index 000000000000..23d050a5d3e7 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_TEE_H__ +#define __INTEL_PXP_TEE_H__ + +#include "intel_pxp.h" + +int intel_pxp_tee_component_init(struct intel_pxp *pxp); +void intel_pxp_tee_component_fini(struct intel_pxp *pxp); + +#endif /* __INTEL_PXP_TEE_H__ */ From patchwork Sat Feb 6 02:09:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DC81C433DB for ; Sat, 6 Feb 2021 02:10:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E60C565006 for ; Sat, 6 Feb 2021 02:10:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E60C565006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EAD786F54D; Sat, 6 Feb 2021 02:10:41 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6694D6F54D for ; Sat, 6 Feb 2021 02:10:40 +0000 (UTC) IronPort-SDR: AMiervS9yFl+M4fk0W62YvdzxBmXLMyCodpykjb3cbFXe87FP7vRp1kalk5ljpZceiJtMyxH3d eBfEIwXY62/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577461" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577461" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:40 -0800 IronPort-SDR: Ha7JWSruoQxQn1LqkQAO7YH0M2eO29TeixZe04KvmoSRqrV0Ljst2tcN3Qym8ox2oji4LEv9Ks 4AilldhG7MwA== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141390" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:39 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:18 -0800 Message-Id: <20210206020925.36729-8-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Huang, Sean Z" , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Huang, Sean Z" Create the arbitrary session, with the fixed session id 0xf, after system boot, for the case that application allocates the protected buffer without establishing any protection session. Because the hardware requires at least one alive session for protected buffer creation. This arbitrary session will need to be re-created after teardown or power event because hardware encryption key won't be valid after such cases. The session ID is exposed as part of the uapi so it can be used as part of userspace commands. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 82 +++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 16 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 104 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++ include/uapi/drm/i915_drm.h | 4 + 8 files changed, 218 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f0ba95a2e4fc..8519abcf6515 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -271,6 +271,7 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ + pxp/intel_pxp_session.o \ pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 3f3eeadb7931..916187a0e566 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -62,6 +62,8 @@ void intel_pxp_init(struct intel_pxp *pxp) if (!HAS_PXP(gt->i915)) return; + mutex_init(&pxp->mutex); + kcr_pxp_enable(gt); ret = create_vcs_context(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c new file mode 100644 index 000000000000..1ee608341b7a --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "drm/i915_drm.h" +#include "i915_drv.h" + +#include "intel_pxp.h" +#include "intel_pxp_session.h" +#include "intel_pxp_tee.h" +#include "intel_pxp_types.h" + +#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */ + +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */ + +static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + intel_wakeref_t wakeref; + u32 sip = 0; + + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) + sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP); + + return sip & BIT(id); +} + +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp) +{ + return intel_pxp_session_is_in_play(pxp, ARB_SESSION); +} + +static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + intel_wakeref_t wakeref; + u32 mask = BIT(id); + int ret; + + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) + ret = intel_wait_for_register(gt->uncore, + GEN12_KCR_SIP, + mask, + in_play ? mask : 0, + 100); + + return ret; +} + +int intel_pxp_create_arb_session(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + int ret; + + lockdep_assert_held(&pxp->mutex); + + pxp->arb_is_in_play = false; + + if (intel_pxp_session_is_in_play(pxp, ARB_SESSION)) { + drm_err(>->i915->drm, "arb session already in play at creation time\n"); + pxp->arb_is_in_play = true; + return -EEXIST; + } + + ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION); + if (ret) { + drm_err(>->i915->drm, "tee cmd for arb session creation failed\n"); + return ret; + } + + ret = pxp_wait_for_session_state(pxp, ARB_SESSION, true); + if (ret) { + drm_err(>->i915->drm, "arb session failed to go in play\n"); + return ret; + } + + pxp->arb_is_in_play = true; + + return 0; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h new file mode 100644 index 000000000000..6fc4a2370c44 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_SESSION_H__ +#define __INTEL_PXP_SESSION_H__ + +#include + +struct intel_pxp; + +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp); +int intel_pxp_create_arb_session(struct intel_pxp *pxp); + +#endif /* __INTEL_PXP_SESSION_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 1d2b8c346161..700709f323f7 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -8,8 +8,68 @@ #include "drm/i915_component.h" #include "i915_drv.h" #include "intel_pxp.h" +#include "intel_pxp_session.h" #include "intel_pxp_tee.h" +#define PXP_TEE_APIVER 0x40002 +#define PXP_TEE_ARB_CMDID 0x1e +#define PXP_TEE_ARB_PROTECTION_MODE 0x2 + +/* PXP TEE message header */ +struct pxp_tee_cmd_header { + u32 api_version; + u32 command_id; + u32 status; + /* Length of the message (excluding the header) */ + u32 buffer_len; +} __packed; + +/* PXP TEE message input to create a arbitrary session */ +struct pxp_tee_create_arb_in { + struct pxp_tee_cmd_header header; + u32 protection_mode; + u32 session_id; +} __packed; + +/* PXP TEE message output to create a arbitrary session */ +struct pxp_tee_create_arb_out { + struct pxp_tee_cmd_header header; +} __packed; + +static int intel_pxp_tee_io_message(struct intel_pxp *pxp, + void *msg_in, u32 msg_in_size, + void *msg_out, u32 msg_out_max_size, + u32 *msg_out_rcv_size) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master; + int ret; + + lockdep_assert_held(&i915->pxp_tee_comp_mutex); + + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size); + if (ret) { + drm_err(&i915->drm, "Failed to send TEE message\n"); + return ret; + } + + ret = pxp_tee_master->ops->recv(pxp_tee_master->tee_dev, msg_out, msg_out_max_size); + if (ret < 0) { + drm_err(&i915->drm, "Failed to receive TEE message\n"); + return ret; + } + + if (ret > msg_out_max_size) { + drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n"); + return -ENOSPC; + } + + if (msg_out_rcv_size) + *msg_out_rcv_size = ret; + + return 0; +} + /** * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee * @i915_kdev: pointer to i915 kernel device @@ -23,13 +83,28 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, struct device *tee_kdev, void *data) { + int ret = 0; struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_pxp *pxp = &i915->gt.pxp; mutex_lock(&i915->pxp_tee_comp_mutex); i915->pxp_tee_master = (struct i915_pxp_comp_master *)data; i915->pxp_tee_master->tee_dev = tee_kdev; mutex_unlock(&i915->pxp_tee_comp_mutex); + mutex_lock(&pxp->mutex); + + /* Create arb session only if tee is ready, during system boot or sleep/resume */ + if (!intel_pxp_arb_session_is_in_play(pxp)) + ret = intel_pxp_create_arb_session(pxp); + + mutex_unlock(&pxp->mutex); + + if (ret) { + drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret); + return ret; + } + return 0; } @@ -84,3 +159,32 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp) component_del(i915->drm.dev, &i915_pxp_tee_component_ops); } + +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, + int arb_session_id) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct pxp_tee_create_arb_in msg_in = {0}; + struct pxp_tee_create_arb_out msg_out = {0}; + int ret; + + msg_in.header.api_version = PXP_TEE_APIVER; + msg_in.header.command_id = PXP_TEE_ARB_CMDID; + msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); + msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE; + msg_in.session_id = arb_session_id; + + mutex_lock(&i915->pxp_tee_comp_mutex); + + ret = intel_pxp_tee_io_message(pxp, + &msg_in, sizeof(msg_in), + &msg_out, sizeof(msg_out), + NULL); + + mutex_unlock(&i915->pxp_tee_comp_mutex); + + if (ret) + drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret); + + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h index 23d050a5d3e7..c136053ce340 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -11,4 +11,7 @@ int intel_pxp_tee_component_init(struct intel_pxp *pxp); void intel_pxp_tee_component_fini(struct intel_pxp *pxp); +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, + int arb_session_id); + #endif /* __INTEL_PXP_TEE_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index bd12c520e60a..30a6013b5d95 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -6,10 +6,16 @@ #ifndef __INTEL_PXP_TYPES_H__ #define __INTEL_PXP_TYPES_H__ +#include +#include + struct intel_context; struct intel_pxp { struct intel_context *ce; + + struct mutex mutex; + bool arb_is_in_play; }; #endif /* __INTEL_PXP_TYPES_H__ */ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 1987e2ea79a3..56c6bfe6c2d0 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2376,6 +2376,10 @@ struct drm_i915_query_perf_config { __u8 data[]; }; + +/* ID of the protected content session managed by i915 when PXP is active */ +#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf + #if defined(__cplusplus) } #endif From patchwork Sat Feb 6 02:09:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CBE1C433E6 for ; Sat, 6 Feb 2021 02:10:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEECF6501C for ; Sat, 6 Feb 2021 02:10:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EEECF6501C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 051436F54E; Sat, 6 Feb 2021 02:10:44 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47FD06F54D for ; Sat, 6 Feb 2021 02:10:41 +0000 (UTC) IronPort-SDR: wKp37URBlHuGvTUc3GQI91ntWrrNCvWXXiCvXjPk2EBvY60lLnmWLlFPZIx0CXclcaJ8Vm183E hyfWJZnDLPNg== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577464" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577464" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:41 -0800 IronPort-SDR: FuoFjfYFtHmr36yu07Fb3iHWYqVbGPpiakt9VofC8+mTC5SAZq1edKY3a9L5imJNWuTIW8hlvr Pd4q+u3emJbA== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141415" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:40 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:19 -0800 Message-Id: <20210206020925.36729-9-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Huang, Sean Z" , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Huang, Sean Z" Teardown is triggered when the display topology changes and no long meets the secure playback requirement, and hardware trashes all the encryption keys for display. Additionally, we want to emit a teardown operation to make sure we're clean on boot and resume Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 40 ++++ drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +- 6 files changed, 288 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 8519abcf6515..9698fec810ae 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -271,6 +271,7 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ + pxp/intel_pxp_cmd.o \ pxp/intel_pxp_session.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c new file mode 100644 index 000000000000..3e2c3580cb1b --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "intel_pxp.h" +#include "intel_pxp_session.h" +#include "gt/intel_context.h" +#include "gt/intel_engine_pm.h" +#include "gt/intel_gpu_commands.h" +#include "gt/intel_gt_buffer_pool.h" + +/* PXP GPU command definitions */ + +/* MI_SET_APPID */ +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0) + +/* MI_FLUSH_DW */ +#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22) + +/* MI_WAIT */ +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9) +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8) + +/* CRYPTO_KEY_EXCHANGE */ +#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16)) + +static struct i915_vma *intel_pxp_get_batch(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, + u32 size) +{ + struct intel_gt_buffer_pool_node *pool; + struct i915_vma *batch; + int err; + + intel_engine_pm_get(ce->engine); + +retry: + err = intel_context_pin_ww(ce, ww); + if (err) + goto out; + + pool = intel_gt_get_buffer_pool(ce->engine->gt, size, I915_MAP_WC); + if (IS_ERR(pool)) { + err = PTR_ERR(pool); + goto out_ctx; + } + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto out_put; + } + + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out_put; + + err = i915_gem_object_lock(pool->obj, ww); + if (err) + goto out_unpin; + + batch->private = pool; + + return batch; + +out_unpin: + i915_vma_unpin(batch); +out_put: + intel_gt_buffer_pool_put(pool); +out_ctx: + intel_context_unpin(ce); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(ww); + if (!err) + goto retry; + } + intel_engine_pm_put(ce->engine); + return ERR_PTR(err); +} + +static void intel_pxp_put_batch(struct intel_context *ce, + struct i915_vma *batch) +{ + i915_vma_unpin(batch); + intel_gt_buffer_pool_put(batch->private); + intel_context_unpin(ce); + intel_engine_pm_put(ce->engine); +} + +static int intel_pxp_submit_batch(struct intel_context *ce, + struct i915_vma *batch) +{ + struct i915_request *rq; + int err; + + rq = i915_request_create(ce); + if (IS_ERR(rq)) + return PTR_ERR(rq); + + err = i915_request_await_object(rq, batch->obj, false); + if (!err) + err = i915_vma_move_to_active(batch, rq, 0); + if (err) + goto out_rq; + + err = intel_gt_buffer_pool_mark_active(batch->private, rq); + if (err) + goto out_rq; + + if (ce->engine->emit_init_breadcrumb) { + err = ce->engine->emit_init_breadcrumb(rq); + if (err) + goto out_rq; + } + + err = ce->engine->emit_bb_start(rq, batch->node.start, + batch->node.size, 0); + if (err) + goto out_rq; + +out_rq: + i915_request_get(rq); + + if (unlikely(err)) + i915_request_set_error_once(rq, err); + + i915_request_add(rq); + + if (!err && i915_request_wait(rq, 0, HZ / 5) < 0) + err = -ETIME; + + i915_request_put(rq); + + return err; +} + +/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */ +#define MFX_WAIT_PXP \ + MFX_WAIT | \ + MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \ + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG; + +static u32 *pxp_emit_session_selection(u32 *cmd, u32 idx) +{ + *cmd++ = MFX_WAIT_PXP; + + /* pxp off */ + *cmd++ = MI_FLUSH_DW; + *cmd++ = 0; + *cmd++ = 0; + + /* select session */ + *cmd++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx); + + *cmd++ = MFX_WAIT_PXP; + + /* pxp on */ + *cmd++ = MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE; + *cmd++ = 0; + *cmd++ = 0; + + *cmd++ = MFX_WAIT_PXP; + + return cmd; +} + +static u32 *pxp_emit_inline_termination(u32 *cmd) +{ + /* session inline termination */ + *cmd++ = CRYPTO_KEY_EXCHANGE; + *cmd++ = 0; + + return cmd; +} + +static u32 *pxp_emit_batch_end(u32 *cmd) +{ + /* wait for cmds to go through */ + *cmd++ = MFX_WAIT_PXP; + + *cmd++ = MI_BATCH_BUFFER_END; + + return cmd; +} + +int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id) +{ + struct i915_vma *batch; + struct i915_gem_ww_ctx ww; + u32 *cmd; + int err; + + if (!intel_pxp_is_enabled(pxp)) + return 0; + + i915_gem_ww_ctx_init(&ww, false); + + batch = intel_pxp_get_batch(pxp->ce, &ww, PAGE_SIZE); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto out_ww; + } + + cmd = i915_gem_object_pin_map(batch->obj, I915_MAP_WC); + if (IS_ERR(cmd)) { + err = PTR_ERR(cmd); + goto out_batch; + } + + cmd = pxp_emit_session_selection(cmd, id); + cmd = pxp_emit_inline_termination(cmd); + cmd = pxp_emit_batch_end(cmd); + + i915_gem_object_flush_map(batch->obj); + i915_gem_object_unpin_map(batch->obj); + + err = intel_pxp_submit_batch(pxp->ce, batch); + +out_batch: + intel_pxp_put_batch(pxp->ce, batch); +out_ww: + i915_gem_ww_ctx_fini(&ww); + return err; +} + diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h new file mode 100644 index 000000000000..7c33b66f0812 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_CMD_H__ +#define __INTEL_PXP_CMD_H__ + +#include + +struct intel_pxp; + +int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 idx); + +#endif /* __INTEL_PXP_CMD_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c index 1ee608341b7a..fe733cc69f27 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -7,6 +7,7 @@ #include "i915_drv.h" #include "intel_pxp.h" +#include "intel_pxp_cmd.h" #include "intel_pxp_session.h" #include "intel_pxp_tee.h" #include "intel_pxp_types.h" @@ -15,6 +16,9 @@ #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */ +/* PXP global terminate register for session termination */ +#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8) + static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id) { struct intel_gt *gt = pxp_to_gt(pxp); @@ -80,3 +84,39 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp) return 0; } + +/** + * intel_pxp_arb_terminate_session_with_global_terminate - Terminate the arb hw session. + * @pxp: pointer to pxp struct. + * + * This function is NOT intended to be called from the ioctl, and need to be protected by + * mutex to ensure no SIP change during the call. + * + * Return: status. 0 means terminate is successful. + */ +int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = pxp_to_gt(pxp); + + lockdep_assert_held(&pxp->mutex); + + /* terminate the hw sessions */ + ret = intel_pxp_submit_session_termination(pxp, ARB_SESSION); + if (ret) { + drm_err(>->i915->drm, "Failed to submit session termination\n"); + return ret; + } + + pxp->arb_is_in_play = false; + + ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false); + if (ret) { + drm_err(>->i915->drm, "Session state did not clear\n"); + return ret; + } + + intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1); + + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h index 6fc4a2370c44..07c97df7a509 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h @@ -12,5 +12,6 @@ struct intel_pxp; bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp); int intel_pxp_create_arb_session(struct intel_pxp *pxp); +int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp); #endif /* __INTEL_PXP_SESSION_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 700709f323f7..dd7161f176f1 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -95,7 +95,10 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, mutex_lock(&pxp->mutex); /* Create arb session only if tee is ready, during system boot or sleep/resume */ - if (!intel_pxp_arb_session_is_in_play(pxp)) + if (intel_pxp_arb_session_is_in_play(pxp)) + ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp); + + if (!ret) ret = intel_pxp_create_arb_session(pxp); mutex_unlock(&pxp->mutex); From patchwork Sat Feb 6 02:09:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CD4AC433E0 for ; Sat, 6 Feb 2021 02:10:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3415465006 for ; Sat, 6 Feb 2021 02:10:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3415465006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5D9B6F54F; Sat, 6 Feb 2021 02:10:43 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D1DC6F54E for ; Sat, 6 Feb 2021 02:10:42 +0000 (UTC) IronPort-SDR: i/+cmqHXkmfDXPnnSmfXmuety2xW2l5tKS7iKWuthEJpXpctbeB01+fMtbolnKUIXd1C5SBlDD t4q/l+vUYGgA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577465" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577465" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:41 -0800 IronPort-SDR: fSYWae7VQ6GrfFhiA72zEf6TrC4dA5chWi5m5/8GqJs8/RL/G1zjdLUxDudg/ZVgLcLdsc1mka 5SkvdMhh+34w== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141429" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:41 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:20 -0800 Message-Id: <20210206020925.36729-10-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 09/14] drm/i915/pxp: Implement PXP irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Huang, Sean Z" , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Huang, Sean Z" The HW will generate a teardown interrupt when session termination is required, which requires i915 to submit a terminating batch. Once the HW is done with the termination it will generate another interrupt, at which point it is safe to re-create the session. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 + drivers/gpu/drm/i915/pxp/intel_pxp.h | 9 ++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 145 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9 +- drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 7 + 10 files changed, 219 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 9698fec810ae..f45275c0034e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -272,6 +272,7 @@ i915-y += i915_perf.o i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ pxp/intel_pxp_cmd.o \ + pxp/intel_pxp_irq.o \ pxp/intel_pxp_session.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index d29126c458ba..0d3585efe2b8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -13,6 +13,7 @@ #include "intel_lrc_reg.h" #include "intel_uncore.h" #include "intel_rps.h" +#include "pxp/intel_pxp_irq.h" static void guc_irq_handler(struct intel_guc *guc, u16 iir) { @@ -64,6 +65,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, if (instance == OTHER_GTPM_INSTANCE) return gen11_rps_irq_handler(>->rps, iir); + if (instance == OTHER_KCR_INSTANCE) + return intel_pxp_irq_handler(>->pxp, iir); + WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", instance, iir); } @@ -190,6 +194,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); + + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0); + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0); } void gen11_gt_irq_postinstall(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 224ad897af34..0dcc04c7d2d8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7958,6 +7958,7 @@ enum { /* irq instances for OTHER_CLASS */ #define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE 1 +#define OTHER_KCR_INSTANCE 4 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 916187a0e566..f6317ce645c7 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -2,7 +2,9 @@ /* * Copyright(c) 2020 Intel Corporation. */ +#include #include "intel_pxp.h" +#include "intel_pxp_irq.h" #include "intel_pxp_tee.h" #include "gt/intel_context.h" #include "i915_drv.h" @@ -70,6 +72,9 @@ void intel_pxp_init(struct intel_pxp *pxp) if (ret) goto out_kcr; + intel_pxp_irq_init(pxp); + intel_pxp_irq_enable(pxp); + ret = intel_pxp_tee_component_init(pxp); if (ret) goto out_context; @@ -91,6 +96,8 @@ void intel_pxp_fini(struct intel_pxp *pxp) if (!intel_pxp_is_enabled(pxp)) return; + intel_pxp_irq_disable(pxp); + intel_pxp_tee_component_fini(pxp); destroy_vcs_context(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index e2acd06402cd..dce7b1a23850 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -9,6 +9,15 @@ #include "gt/intel_gt_types.h" #include "intel_pxp_types.h" +#define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1) +#define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2) +#define GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT BIT(3) + +#define GEN12_PXP_INTERRUPTS \ + (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | \ + GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT | \ + GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT) + static inline struct intel_gt *pxp_to_gt(struct intel_pxp *pxp) { return container_of(pxp, struct intel_gt, pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c new file mode 100644 index 000000000000..5ca0218a27d8 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ +#include +#include "intel_pxp.h" +#include "intel_pxp_irq.h" +#include "intel_pxp_session.h" +#include "gt/intel_gt_irq.h" +#include "i915_irq.h" +#include "i915_reg.h" + +static int pxp_terminate(struct intel_pxp *pxp) +{ + int ret = 0; + + mutex_lock(&pxp->mutex); + + pxp->global_state_attacked = true; + + ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp); + + mutex_unlock(&pxp->mutex); + + return ret; +} + +static int pxp_terminate_complete(struct intel_pxp *pxp) +{ + int ret = 0; + + mutex_lock(&pxp->mutex); + + pxp->termination_in_progress = false; + + if (pxp->global_state_attacked) { + pxp->global_state_attacked = false; + + /* Re-create the arb session after teardown handle complete */ + ret = intel_pxp_create_arb_session(pxp); + } + + mutex_unlock(&pxp->mutex); + return ret; +} + +static void intel_pxp_irq_work(struct work_struct *work) +{ + struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work); + struct intel_gt *gt = pxp_to_gt(pxp); + u32 events = 0; + + spin_lock_irq(>->irq_lock); + events = fetch_and_zero(&pxp->current_events); + spin_unlock_irq(>->irq_lock); + + if (!events) + return; + + if (events & (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | + GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT)) + pxp_terminate(pxp); + + if (events & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT) + pxp_terminate_complete(pxp); + + /* + * we expect the terminate complete to arrive quickly after emitting + * the terminate, so check back on it + */ + if (pxp->irq_enabled) + queue_work(system_unbound_wq, &pxp->irq_work); +} + +/** + * intel_pxp_irq_handler - Handles PXP interrupts. + * @pxp: pointer to pxp struct + * @iir: interrupt vector + */ +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + + if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) + return; + + lockdep_assert_held(>->irq_lock); + + if (unlikely(!iir)) + return; + + pxp->current_events |= iir; + queue_work(system_unbound_wq, &pxp->irq_work); +} + +static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts) +{ + struct intel_uncore *uncore = gt->uncore; + const u32 mask = interrupts << 16; + + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, mask); + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~mask); +} + +static inline void pxp_irq_reset(struct intel_gt *gt) +{ + spin_lock_irq(>->irq_lock); + gen11_gt_reset_one_iir(gt, 0, GEN11_KCR); + spin_unlock_irq(>->irq_lock); +} + +void intel_pxp_irq_init(struct intel_pxp *pxp) +{ + INIT_WORK(&pxp->irq_work, intel_pxp_irq_work); +} + +void intel_pxp_irq_enable(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + + spin_lock_irq(>->irq_lock); + if (!pxp->irq_enabled) { + WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR)); + __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS); + pxp->irq_enabled = true; + } + spin_unlock_irq(>->irq_lock); +} + +void intel_pxp_irq_disable(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + + spin_lock_irq(>->irq_lock); + + pxp->irq_enabled = false; + __pxp_set_interrupts(gt, 0); + + spin_unlock_irq(>->irq_lock); + intel_synchronize_irq(gt->i915); + + pxp_irq_reset(gt); + + flush_work(&pxp->irq_work); +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h new file mode 100644 index 000000000000..7a875831636d --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_IRQ_H__ +#define __INTEL_PXP_IRQ_H__ + +#include + +struct intel_pxp; + +#ifdef CONFIG_DRM_I915_PXP +void intel_pxp_irq_init(struct intel_pxp *pxp); +void intel_pxp_irq_enable(struct intel_pxp *pxp); +void intel_pxp_irq_disable(struct intel_pxp *pxp); +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); +#else +void intel_pxp_irq_init(struct intel_pxp *pxp) +{ +} +void intel_pxp_irq_enable(struct intel_pxp *pxp) +{ +} +void intel_pxp_irq_disable(struct intel_pxp *pxp) +{ +} +static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) +{ +} +#endif + +#endif /* __INTEL_PXP_IRQ_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c index fe733cc69f27..d0cb35a8b991 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -117,6 +117,7 @@ int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp) } intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1); + pxp->termination_in_progress = true; return ret; } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index dd7161f176f1..f52150aca02b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -95,9 +95,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, mutex_lock(&pxp->mutex); /* Create arb session only if tee is ready, during system boot or sleep/resume */ - if (intel_pxp_arb_session_is_in_play(pxp)) + if (intel_pxp_arb_session_is_in_play(pxp)) { ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp); + if (!ret) { + mutex_unlock(&pxp->mutex); + ret = wait_for(!pxp->termination_in_progress, 10); + mutex_lock(&pxp->mutex); + } + } + if (!ret) ret = intel_pxp_create_arb_session(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index 30a6013b5d95..51915f7b1521 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -8,6 +8,7 @@ #include #include +#include struct intel_context; @@ -16,6 +17,12 @@ struct intel_pxp { struct mutex mutex; bool arb_is_in_play; + bool termination_in_progress; + bool global_state_attacked; + + struct work_struct irq_work; + bool irq_enabled; + u32 current_events; /* protected with gt->irq_lock */ }; #endif /* __INTEL_PXP_TYPES_H__ */ From patchwork Sat Feb 6 02:09:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EB7CC433DB for ; Sat, 6 Feb 2021 02:10:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 434BB65006 for ; Sat, 6 Feb 2021 02:10:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 434BB65006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8906E6F557; Sat, 6 Feb 2021 02:10:52 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF4906F54E for ; Sat, 6 Feb 2021 02:10:42 +0000 (UTC) IronPort-SDR: iKIVJaGCZPjLUOKHNvaW7MUcjtiCF7gd8LpHZ/O+N0UFtnqiowGsCIvt/nj1yQN1Nrm7LuZ3Tl DePXdZQyE5hw== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577468" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577468" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:42 -0800 IronPort-SDR: SOnwxF5aGDTOsj0/nC7hbjlFVuj6qsuOLC7Vg9wVnyt2G26pUe8Hm/3hnCUbJ8uXBNqlrtHGih 9oQrIcJCjjgA== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141448" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:42 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:21 -0800 Message-Id: <20210206020925.36729-11-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Huang, Sean Z" , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Huang, Sean Z" During the power event S3+ sleep/resume, hardware will lose all the encryption keys for every hardware session, even though the software session state was marked as alive after resume. So to handle such case, PXP should unconditionally terminate the hardware sessions and cleanup all the software states after the power cycle. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++ drivers/gpu/drm/i915/i915_drv.c | 4 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 10 ++- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 94 ++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 36 +++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 + 7 files changed, 148 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f45275c0034e..51c56889cfeb 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -273,6 +273,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ pxp/intel_pxp_cmd.o \ pxp/intel_pxp_irq.o \ + pxp/intel_pxp_pm.o \ pxp/intel_pxp_session.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 0bd303d2823e..160a60e701dc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -19,6 +19,7 @@ #include "intel_rc6.h" #include "intel_rps.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_pm.h" static void user_forcewake(struct intel_gt *gt, bool suspend) { @@ -260,6 +261,8 @@ int intel_gt_resume(struct intel_gt *gt) intel_uc_resume(>->uc); + intel_pxp_pm_resume(>->pxp); + user_forcewake(gt, false); out_fw: @@ -294,6 +297,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt) user_forcewake(gt, true); wait_for_suspend(gt); + intel_pxp_pm_prepare_suspend(>->pxp); intel_uc_suspend(>->uc); } @@ -355,6 +359,8 @@ int intel_gt_runtime_resume(struct intel_gt *gt) intel_gt_init_swizzling(gt); intel_ggtt_restore_fences(gt->ggtt); + intel_pxp_runtime_resume(>->pxp); + return intel_uc_runtime_resume(>->uc); } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index d1344eb6c849..172fd97de5eb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -70,6 +70,8 @@ #include "gt/intel_gt_pm.h" #include "gt/intel_rc6.h" +#include "pxp/intel_pxp_pm.h" + #include "i915_debugfs.h" #include "i915_drm_client.h" #include "i915_drv.h" @@ -1364,6 +1366,8 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_power_domains_resume(dev_priv); + intel_pxp_pm_resume_early(&dev_priv->gt.pxp); + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index 5ca0218a27d8..c20990f8943c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -119,11 +119,13 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp) struct intel_gt *gt = pxp_to_gt(pxp); spin_lock_irq(>->irq_lock); - if (!pxp->irq_enabled) { + + if (!pxp->irq_enabled) WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR)); - __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS); - pxp->irq_enabled = true; - } + + __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS); + pxp->irq_enabled = true; + spin_unlock_irq(>->irq_lock); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c new file mode 100644 index 000000000000..f227634c2956 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include "intel_pxp.h" +#include "intel_pxp_irq.h" +#include "intel_pxp_pm.h" +#include "intel_pxp_session.h" + +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ + if (!intel_pxp_is_enabled(pxp)) + return; + + mutex_lock(&pxp->mutex); + + /* Mark PXP ops as disabled */ + pxp->global_state_in_suspend = true; + + mutex_unlock(&pxp->mutex); + + intel_pxp_irq_disable(pxp); +} + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ + if (!intel_pxp_is_enabled(pxp)) + return; + + mutex_lock(&pxp->mutex); + + /* reset the attacked flag even if there was a pending */ + if (pxp->global_state_in_suspend) + pxp->global_state_attacked = false; + + mutex_unlock(&pxp->mutex); +} + +int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + int ret = 0; + struct intel_gt *gt = pxp_to_gt(pxp); + + if (!intel_pxp_is_enabled(pxp)) + return 0; + + intel_pxp_irq_enable(pxp); + + mutex_lock(&pxp->mutex); + + /* Re-enable PXP ops */ + if (pxp->global_state_in_suspend) { + /* + * Note: we won't re-create the session as part of the irq + * generated by this termination because + * pxp->global_state_attacked is not set. The session + * will be recreated as part of the mei component re-binding. + */ + ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp); + if (ret) { + drm_err(>->i915->drm, + "Failed to terminate the arb session on resume\n"); + goto end; + } + + pxp->global_state_in_suspend = false; + } + +end: + mutex_unlock(&pxp->mutex); + + if (!ret) { + ret = wait_for(!pxp->termination_in_progress, 10); + if (ret) { + drm_err(>->i915->drm, + "Didn't recevive the PXP termination irq\n"); + } + } + + return ret; +} + +void intel_pxp_runtime_resume(struct intel_pxp *pxp) +{ + if (!intel_pxp_is_enabled(pxp)) + return; + + /* interrupts are reset in the rpm resume path, so turn them back on */ + intel_pxp_irq_enable(pxp); + + return; +} + diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h new file mode 100644 index 000000000000..0150f28c0940 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_PM_H__ +#define __INTEL_PXP_PM_H__ + +#include "i915_drv.h" + +#ifdef CONFIG_DRM_I915_PXP +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp); + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp); +int intel_pxp_pm_resume(struct intel_pxp *pxp); +void intel_pxp_runtime_resume(struct intel_pxp *pxp); +#else +static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ +} + +static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ +} + +static inline int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + return 0; +} + +static inline void intel_pxp_runtime_resume(struct intel_pxp *pxp) +{ +} +#endif + +#endif /* __INTEL_PXP_PM_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index 51915f7b1521..5e400fb3cd15 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -19,6 +19,7 @@ struct intel_pxp { bool arb_is_in_play; bool termination_in_progress; bool global_state_attacked; + bool global_state_in_suspend; struct work_struct irq_work; bool irq_enabled; From patchwork Sat Feb 6 02:09:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B6AAC433E0 for ; Sat, 6 Feb 2021 02:10:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4031865006 for ; Sat, 6 Feb 2021 02:10:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4031865006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2B5B6F554; Sat, 6 Feb 2021 02:10:48 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id A10806F54E for ; Sat, 6 Feb 2021 02:10:43 +0000 (UTC) IronPort-SDR: tUNsapVnGg85C49mm5YXy0+JOhBPkdz1dAHqygK7MhpV8OQqv3peWiClEo6VUh7p+Douayhlpb QkOJ+GrgNChw== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577469" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577469" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:43 -0800 IronPort-SDR: /5Wx74dH5lRZjUy2T3B5yIwAeZbwsD/7YS9aLOLo+B57YvP8+juCZjc37FZbdRNzG04En0/reh uagaemf9syVQ== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141461" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:43 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:22 -0800 Message-Id: <20210206020925.36729-12-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 11/14] drm/i915/uapi: introduce drm_i915_gem_create_ext X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bommu Krishnaiah , Matthew Auld Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Bommu Krishnaiah Same old gem_create but with now with extensions support. This is needed to support various upcoming usecases. For now we use the extensions mechanism to support PAVP. Signed-off-by: Bommu Krishnaiah Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Matthew Auld Cc: Telukuntla Sreedhar --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.c | 2 +- include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++ 3 files changed, 88 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 45d60e3d98e3..3ad3413c459f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -7,6 +7,7 @@ #include "gem/i915_gem_region.h" #include "i915_drv.h" +#include "i915_user_extensions.h" static int i915_gem_create(struct drm_file *file, @@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file, &args->size, &args->handle); } +struct create_ext { + struct drm_i915_private *i915; +}; + +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) +{ + if (!(args->param & I915_OBJECT_PARAM)) { + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n"); + return -EINVAL; + } + + return -EINVAL; +} + +static int create_setparam(struct i915_user_extension __user *base, void *data) +{ + struct drm_i915_gem_create_ext_setparam ext; + + if (copy_from_user(&ext, base, sizeof(ext))) + return -EFAULT; + + return __create_setparam(&ext.param, data); +} + +static const i915_user_extension_fn create_extensions[] = { + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam, +}; + /** * Creates a new mm object and returns a handle to it. * @dev: drm device pointer @@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_i915_private *i915 = to_i915(dev); - struct drm_i915_gem_create *args = data; + struct create_ext ext_data = { .i915 = i915 }; + struct drm_i915_gem_create_ext *args = data; + int ret; i915_gem_flush_free_objects(i915); + ret = i915_user_extensions(u64_to_user_ptr(args->extensions), + create_extensions, + ARRAY_SIZE(create_extensions), + &ext_data); + if (ret) + return ret; + return i915_gem_create(file, intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM), diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 172fd97de5eb..d69fce617e8b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1753,7 +1753,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 56c6bfe6c2d0..c5ed7680c252 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) @@ -729,6 +730,27 @@ struct drm_i915_gem_create { __u32 pad; }; +struct drm_i915_gem_create_ext { + /** + * Requested size for the object. + * + * The (page-aligned) allocated size for the object will be returned. + */ + __u64 size; + /** + * Returned handle for the object. + * + * Object handles are nonzero. + */ + __u32 handle; + __u32 pad; +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0) +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \ + (-(I915_GEM_CREATE_EXT_SETPARAM << 1)) + __u64 extensions; + +}; + struct drm_i915_gem_pread { /** Handle for the object being read. */ __u32 handle; @@ -1699,6 +1721,31 @@ struct drm_i915_gem_context_param { __u64 value; }; +struct drm_i915_gem_object_param { + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */ + __u32 handle; + + /* Data pointer size */ + __u32 size; + +/* + * I915_OBJECT_PARAM: + * + * Select object namespace for the param. + */ +#define I915_OBJECT_PARAM (1ull << 32) + + __u64 param; + + /* Data value or pointer */ + __u64 data; +}; + +struct drm_i915_gem_create_ext_setparam { + struct i915_user_extension base; + struct drm_i915_gem_object_param param; +}; + /** * Context SSEU programming * From patchwork Sat Feb 6 02:09:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80A34C433E9 for ; Sat, 6 Feb 2021 02:10:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4616C65006 for ; Sat, 6 Feb 2021 02:10:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4616C65006 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6C5F6F552; Sat, 6 Feb 2021 02:10:45 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8BFC96F553 for ; Sat, 6 Feb 2021 02:10:44 +0000 (UTC) IronPort-SDR: pvMxrnbEQJMVShzfmHWzI6Mjif7XP7ag9CGiD8svLxHuG3JK1BxxPmM2h4TWWVAaHRxYS9DC/2 wh7FMQ7Q9aGA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577470" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577470" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:44 -0800 IronPort-SDR: Lrdx5yTe5yGnlRCZCVb+z11Dk4miaRcItcyDvqojoZGu8AGUnBUjvJ9omib20Ze7Rjj9SmXbpr gGmhBxON9RCQ== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141480" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:43 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:23 -0800 Message-Id: <20210206020925.36729-13-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huang Sean Z , Kondapally Kalyan , Bommu Krishnaiah Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Bommu Krishnaiah This api allow user mode to create Protected buffer and context creation. Only contexts created with the flag set are allowed to operate on protected buffers. We only allow setting the flags at creation time; the context flag also requires the context to be marked as unrecoverable. This is a rework + squash of the original code by Bommu Krishnaiah. I've authorship unchanged since significant chunks have not been modified. Signed-off-by: Bommu Krishnaiah Signed-off-by: Daniele Ceraolo Spurio Cc: Telukuntla Sreedhar Cc: Kondapally Kalyan Cc: Gupta Anshuman Cc: Huang Sean Z --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++++ .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 + drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 +++++++++++++-- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +++++ .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 10 ++++++ include/uapi/drm/i915_drm.h | 19 +++++++++++ 8 files changed, 108 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index ecacfae8412d..d3d9b4578ba8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -76,6 +76,8 @@ #include "gt/intel_gpu_commands.h" #include "gt/intel_ring.h" +#include "pxp/intel_pxp.h" + #include "i915_drm_client.h" #include "i915_gem_context.h" #include "i915_globals.h" @@ -2006,6 +2008,27 @@ static int set_priority(struct i915_gem_context *ctx, return 0; } +static int set_protected(struct i915_gem_context *ctx, + const struct drm_i915_gem_context_param *args) +{ + int ret = 0; + + if (ctx->client) /* can't change this after creation! */ + ret = -EEXIST; + else if (args->size) + ret = -EINVAL; + else if (i915_gem_context_is_recoverable(ctx)) + ret = -EPERM; + else if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp)) + ret = -ENODEV; + else if (args->value) + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags); + else + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags); + + return ret; +} + static int ctx_setparam(struct drm_i915_file_private *fpriv, struct i915_gem_context *ctx, struct drm_i915_gem_context_param *args) @@ -2045,6 +2068,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv, case I915_CONTEXT_PARAM_RECOVERABLE: if (args->size) ret = -EINVAL; + else if (i915_gem_context_can_use_protected_content(ctx)) + ret = -EPERM; else if (args->value) i915_gem_context_set_recoverable(ctx); else @@ -2075,6 +2100,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv, ret = set_ringsize(ctx, args); break; + case I915_CONTEXT_PARAM_PROTECTED_CONTENT: + ret = set_protected(ctx, args); + break; + case I915_CONTEXT_PARAM_BAN_PERIOD: default: ret = -EINVAL; @@ -2532,6 +2561,11 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, ret = get_ringsize(ctx, args); break; + case I915_CONTEXT_PARAM_PROTECTED_CONTENT: + args->size = 0; + args->value = i915_gem_context_can_use_protected_content(ctx); + break; + case I915_CONTEXT_PARAM_BAN_PERIOD: default: ret = -EINVAL; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h index b5c908f3f4f2..473bce972bb2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h @@ -108,6 +108,12 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx) clear_bit(CONTEXT_USER_ENGINES, &ctx->flags); } +static inline bool +i915_gem_context_can_use_protected_content(const struct i915_gem_context *ctx) +{ + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags); +} + /* i915_gem_context.c */ void i915_gem_init__contexts(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h index 085f6a3735e8..1cab741983c9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h @@ -130,6 +130,7 @@ struct i915_gem_context { #define UCONTEXT_BANNABLE 2 #define UCONTEXT_RECOVERABLE 3 #define UCONTEXT_PERSISTENCE 4 +#define UCONTEXT_PROTECTED 5 /** * @flags: small set of booleans diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 3ad3413c459f..ac246b814a3a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -5,6 +5,7 @@ #include "gem/i915_gem_ioctls.h" #include "gem/i915_gem_region.h" +#include "pxp/intel_pxp.h" #include "i915_drv.h" #include "i915_user_extensions.h" @@ -13,7 +14,8 @@ static int i915_gem_create(struct drm_file *file, struct intel_memory_region *mr, u64 *size_p, - u32 *handle_p) + u32 *handle_p, + u64 user_flags) { struct drm_i915_gem_object *obj; u32 handle; @@ -35,6 +37,8 @@ i915_gem_create(struct drm_file *file, GEM_BUG_ON(size != obj->base.size); + obj->user_flags = user_flags; + ret = drm_gem_handle_create(file, &obj->base, &handle); /* drop reference from allocate - handle holds it now */ i915_gem_object_put(obj); @@ -89,11 +93,12 @@ i915_gem_dumb_create(struct drm_file *file, return i915_gem_create(file, intel_memory_region_by_type(to_i915(dev), mem_type), - &args->size, &args->handle); + &args->size, &args->handle, 0); } struct create_ext { struct drm_i915_private *i915; + unsigned long user_flags; }; static int __create_setparam(struct drm_i915_gem_object_param *args, @@ -104,6 +109,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args, return -EINVAL; } + switch (lower_32_bits(args->param)) { + case I915_PARAM_PROTECTED_CONTENT: + if (args->size) { + return -EINVAL; + } else if (args->data) { + ext_data->user_flags = args->data; + return 0; + } + break; + } + return -EINVAL; } @@ -145,8 +161,13 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, if (ret) return ret; + if (ext_data.user_flags & I915_BO_PROTECTED) { + if (!intel_pxp_is_enabled(&i915->gt.pxp)) + return -EINVAL; + } + return i915_gem_create(file, intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM), - &args->size, &args->handle); + &args->size, &args->handle, ext_data.user_flags); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index fe170186dd42..42e75d21f4d0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -20,6 +20,7 @@ #include "gt/intel_gt_buffer_pool.h" #include "gt/intel_gt_pm.h" #include "gt/intel_ring.h" +#include "pxp/intel_pxp.h" #include "i915_drv.h" #include "i915_gem_clflush.h" @@ -498,6 +499,14 @@ eb_validate_vma(struct i915_execbuffer *eb, entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK))) return -EINVAL; + + if (vma->obj->user_flags & I915_BO_PROTECTED) { + if (!intel_pxp_is_active(&vma->vm->gt->pxp)) + return -ENODEV; + if (!i915_gem_context_can_use_protected_content(eb->gem_context)) + return -EINVAL; + } + /* pad_to_size was once a reserved field, so sanitize it */ if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) { if (unlikely(offset_in_page(entry->pad_to_size))) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 0a1fdbac882e..9629b6b2e3d6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -167,6 +167,11 @@ struct drm_i915_gem_object { } mmo; I915_SELFTEST_DECLARE(struct list_head st_link); + /** + * @user_flags: small set of booleans set by the user + */ + unsigned long user_flags; +#define I915_BO_PROTECTED BIT(0) unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index dce7b1a23850..e5b5ae16b068 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -28,6 +28,16 @@ static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp) return pxp->ce; } +/* + * Note: the HW state can change at any point due to user actions, so keep that + * in mind when using the below check. + */ +static inline bool intel_pxp_is_active(struct intel_pxp *pxp) +{ + return intel_pxp_is_enabled(pxp) && pxp->arb_is_in_play && + !pxp->global_state_in_suspend; +} + #ifdef CONFIG_DRM_I915_PXP void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index c5ed7680c252..982b7ec6da48 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param { * Default is 16 KiB. */ #define I915_CONTEXT_PARAM_RINGSIZE 0xc + +/* + * I915_CONTEXT_PARAM_PROTECTED_CONTENT: + * + * Enable usage of protected context with the context. This flag can only be + * set at context creation time and, when set to true, must be preceded by + * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false. + */ +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd /* Must be kept compact -- no holes and well documented */ __u64 value; @@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param { */ #define I915_OBJECT_PARAM (1ull << 32) +/* + * I915_PARAM_PROTECTED_CONTENT: + * + * If set to true (1) buffer contents is expected to be protected by + * PAVP encryption and requires decryption for scan out and processing. + * Protected buffers can only be used in PAVP protected contexts. + * A protected buffer may become invalid as a result of PAVP teardown. + */ +#define I915_PARAM_PROTECTED_CONTENT 0x1 + __u64 param; /* Data value or pointer */ From patchwork Sat Feb 6 02:09:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26173C433E0 for ; Sat, 6 Feb 2021 02:10:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3B406501C for ; Sat, 6 Feb 2021 02:10:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3B406501C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 226356F555; Sat, 6 Feb 2021 02:10:52 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 220736F551 for ; Sat, 6 Feb 2021 02:10:45 +0000 (UTC) IronPort-SDR: widjDqYCxbkMgbvwgTVVKNXWFLDtoMYriU7gs4plZxjijp2bsspG4arwZV874JjJBt74qEdkj1 2xYOWRcG34SA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577474" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577474" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:44 -0800 IronPort-SDR: eGcFK2lb5rPpUFzaoFnhhIll+ts2zsbcALKruHJlzl4tFsUSARBizFpb7sY4z4aUb+mvZV7iJC OXE7nJRGmNoQ== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141492" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:44 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:24 -0800 Message-Id: <20210206020925.36729-14-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 13/14] drm/i915/pxp: Add plane decryption support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huang Sean Z , Gaurav Kumar , Bommu Krishnaiah Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anshuman Gupta Add support to enable/disable PLANE_SURF Decryption Request bit. It requires only to enable plane decryption support when following condition met. 1. PXP session is enabled. 2. Buffer object is protected. v2: - Used gen fb obj user_flags instead gem_object_metadata. [Krishna] v3: - intel_pxp_gem_object_status() API changes. v4: use intel_pxp_is_active (Daniele) Cc: Bommu Krishnaiah Cc: Huang Sean Z Cc: Gaurav Kumar Signed-off-by: Anshuman Gupta Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 402030251c64..77156d38c7e3 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -39,6 +39,8 @@ #include #include +#include "pxp/intel_pxp.h" + #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" @@ -738,6 +740,11 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj) +{ + return obj->user_flags & I915_BO_PROTECTED ? true : false; +} + static void skl_plane_async_flip(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -778,6 +785,7 @@ skl_program_plane(struct intel_plane *plane, u32 surf_addr = plane_state->color_plane[color_plane].offset; u32 stride = skl_plane_stride(plane_state, color_plane); const struct drm_framebuffer *fb = plane_state->hw.fb; + const struct drm_i915_gem_object *obj = intel_fb_obj(fb); int aux_plane = intel_main_to_aux_plane(fb, color_plane); int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -788,7 +796,7 @@ skl_program_plane(struct intel_plane *plane, u8 alpha = plane_state->hw.alpha >> 8; u32 plane_color_ctl = 0, aux_dist = 0; unsigned long irqflags; - u32 keymsk, keymax; + u32 keymsk, keymax, plane_surf; u32 plane_ctl = plane_state->ctl; plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -868,8 +876,15 @@ skl_program_plane(struct intel_plane *plane, * the control register just before the surface register. */ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr; + + if (intel_pxp_is_active(&dev_priv->gt.pxp) && + intel_fb_obj_protected(obj)) + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED; + else + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED; + + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0dcc04c7d2d8..6cb1283b4eed 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7223,6 +7223,7 @@ enum { #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2) #define _PLANE_OFFSET_1_B 0x711a4 #define _PLANE_OFFSET_2_B 0x712a4 From patchwork Sat Feb 6 02:09:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2F66C433E6 for ; Sat, 6 Feb 2021 02:10:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C65F6501C for ; Sat, 6 Feb 2021 02:10:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C65F6501C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A6E9D6F553; Sat, 6 Feb 2021 02:10:48 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B191B6F551 for ; Sat, 6 Feb 2021 02:10:45 +0000 (UTC) IronPort-SDR: +qOOJwvl2lhZTSFz6g6NOGxFcIHtrODlAZmrIq0LMSa+JP12SOTjJNAddbRf9ogFlfW8JJr3sP t5TGMcmhRpeA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577475" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577475" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:45 -0800 IronPort-SDR: alSrjagDrFcrHGUazS6zwk305YCtsMZ6sLFcRb1PuzfxTZ/7Rtd8CZiBF/j73XhhFoQgXiaaZA QLr5gqq1CGrA== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141504" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:45 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:25 -0800 Message-Id: <20210206020925.36729-15-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 14/14] drm/i915/pxp: enable PXP for integrated Gen12 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Note that discrete cards can support PXP as well, but we haven't tested on those yet so keeping it disabled for now. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6cff7cf0f17b..aa5644206e38 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -880,6 +880,7 @@ static const struct intel_device_info jsl_info = { }, \ TGL_CURSOR_OFFSETS, \ .has_global_mocs = 1, \ + .has_pxp = 1, \ .display.has_dsb = 1 static const struct intel_device_info tgl_info = { @@ -909,6 +910,7 @@ static const struct intel_device_info rkl_info = { .memory_regions = REGION_SMEM | REGION_LMEM, \ .has_master_unit_irq = 1, \ .has_llc = 0, \ + .has_pxp = 0, \ .has_snoop = 1, \ .is_dgfx = 1