From patchwork Wed Feb 10 13:34:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12080869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED753C433E0 for ; Wed, 10 Feb 2021 13:37:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B3E4F64E77 for ; Wed, 10 Feb 2021 13:37:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231731AbhBJNh1 (ORCPT ); Wed, 10 Feb 2021 08:37:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231709AbhBJNhR (ORCPT ); Wed, 10 Feb 2021 08:37:17 -0500 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1593C061756 for ; Wed, 10 Feb 2021 05:36:35 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id c18so2825041ljd.9 for ; Wed, 10 Feb 2021 05:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aEjgbQ4louFcHEKPjuOPOwDLbEqUCZLI98DdvpgiOt0=; b=ZAPNNRkjIckBGyYA/DFh+fSTljsaVhNN0TgvkVI9WTzP8+PTJR11eGfJNnC1BgBX0d hK5wVMRfHi6eEhP9RncbyzA1gCx0Zmy1slL+1IUZai6qkVfkuj8FviSgUgQyPTsFQ1ii D2uVyMHHyfRv7fo6r0BRzO2zt2nt6Q8LlqnVPyV8f/SMThJMRHS4zt6re4uBn6wsza/d CzM393UNWEL/CikFVMUsCdzKaS9882E5RLw7zq0g0GaG5ufMZuZ0d/+2Cka6+4P4P2B1 oy4CwuIhJoBWfdp2FwcrY91rYLR7/H5AAvLtx9vHTt/q1tLkw+EHx2svZ4fomL2mAe95 34OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aEjgbQ4louFcHEKPjuOPOwDLbEqUCZLI98DdvpgiOt0=; b=MlW+Nf/vYXS9kx7YWL2URi995sm6962SqdVsDUMtcczj2K4nmPBr3gf7CnTpaLU0ug 7n7vd+c9J8I+m4THkkLJ1lWxUHBDQ+qnlUSbbcqvOH6ww2jqBAzmVhnU08BIvmbcKDl/ jOV7w1a0Uzc7SMGVhvKhvf+F14Bxx+dGET9QVke925Kl14jfXP4fF3LT+YdyE30PBrCM KwK9ogkmXMY5QhSmqJ505uEwRdeXz8htm8m4PkRum1vvOiYsQYSMYYsPfA3dakCLKhIM 7S24JjBt8KcfO3xCk9AB06duGZop4SXNRDRqqV5Ep6dcz9W1mXTXo5fCl4t5JX03yESH /OxA== X-Gm-Message-State: AOAM531JSK/1xoQr1gYr74153O/eldvu3hkJEBUHzsnJtN2OuBBZRhpL tuItJyRkOu9dqXv1hNbjBeW02g== X-Google-Smtp-Source: ABdhPJy/tAWYBf3Tbi8LWU+VCJ1yqSO1Ggw788EIUFQkb1WE61Ol5aZnbqVutH/We7I0XGY5PTSqVw== X-Received: by 2002:a2e:3019:: with SMTP id w25mr2019432ljw.430.1612964194425; Wed, 10 Feb 2021 05:36:34 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id c8sm332629lfb.168.2021.02.10.05.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 05:36:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v4 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Date: Wed, 10 Feb 2021 16:34:55 +0300 Message-Id: <20210210133458.1201066-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> References: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As discussed on linux-arm-msm list, start splitting sm8250 pinctrl settings into generic and board-specific parts. The first part to receive such treatment is the spi, so split spi pinconf to the board device tree. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 6 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 300 +++++------------------ 2 files changed, 66 insertions(+), 240 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2f0528d01299..443206f64061 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1352,3 +1352,9 @@ &vamacro { vdd-micb-supply = <&vreg_s4a_1p8>; qcom,dmic-sample-rate = <600000>; }; + +/* PINCTRL - additions to nodes defined in sm8250.dtsi */ +&qup_spi0_default { + drive-strength = <6>; + bias-disable; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..51d103671759 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2984,303 +2984,123 @@ config { }; qup_spi0_default: qup-spi0-default { - mux { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "qup0"; }; qup_spi1_default: qup-spi1-default { - mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup1"; }; qup_spi2_default: qup-spi2-default { - mux { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio115", "gpio116", + "gpio117", "gpio118"; + function = "qup2"; }; qup_spi3_default: qup-spi3-default { - mux { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio119", "gpio120", + "gpio121", "gpio122"; + function = "qup3"; }; qup_spi4_default: qup-spi4-default { - mux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "qup4"; }; qup_spi5_default: qup-spi5-default { - mux { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "qup5"; }; qup_spi6_default: qup-spi6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "qup6"; }; qup_spi7_default: qup-spi7-default { - mux { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup7"; }; qup_spi8_default: qup-spi8-default { - mux { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup8"; }; qup_spi9_default: qup-spi9-default { - mux { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio125", "gpio126", + "gpio127", "gpio128"; + function = "qup9"; }; qup_spi10_default: qup-spi10-default { - mux { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio129", "gpio130", + "gpio131", "gpio132"; + function = "qup10"; }; qup_spi11_default: qup-spi11-default { - mux { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "qup11"; }; qup_spi12_default: qup-spi12-default { - mux { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup12"; }; qup_spi13_default: qup-spi13-default { - mux { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup13"; }; qup_spi14_default: qup-spi14-default { - mux { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup14"; }; qup_spi15_default: qup-spi15-default { - mux { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup15"; }; qup_spi16_default: qup-spi16-default { - mux { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup16"; }; qup_spi17_default: qup-spi17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup17"; }; qup_spi18_default: qup-spi18-default { - mux { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "qup18"; }; qup_spi19_default: qup-spi19-default { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup19"; }; qup_uart2_default: qup-uart2-default { From patchwork Wed Feb 10 13:34:56 2021 Content-Type: text/plain; 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Wed, 10 Feb 2021 05:36:38 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v4 2/4] arm64: dts: qcom: sm8250: further split of spi pinctrl config Date: Wed, 10 Feb 2021 16:34:56 +0300 Message-Id: <20210210133458.1201066-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> References: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split "default" device tree nodes into common "data-clk" nodes and "cs" nodes which might differ from board to board depending on how the slave chips are wired. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 9 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 220 ++++++++++++++--------- 2 files changed, 148 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 443206f64061..638231f48388 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -952,6 +952,8 @@ codec { /* CAN */ &spi0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; can@0 { compatible = "microchip,mcp2518fd"; @@ -1354,7 +1356,12 @@ &vamacro { }; /* PINCTRL - additions to nodes defined in sm8250.dtsi */ -&qup_spi0_default { +&qup_spi0_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi0_data_clk { drive-strength = <6>; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 51d103671759..5571324641f0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -548,8 +548,6 @@ spi14: spi@880000 { reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -576,8 +574,6 @@ spi15: spi@884000 { reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -604,8 +600,6 @@ spi16: spi@888000 { reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -632,8 +626,6 @@ spi17: spi@88c000 { reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -673,8 +665,6 @@ spi18: spi@890000 { reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -714,8 +704,6 @@ spi19: spi@894000 { reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -755,8 +743,6 @@ spi0: spi@980000 { reg = <0 0x00980000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -783,8 +769,6 @@ spi1: spi@984000 { reg = <0 0x00984000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -811,8 +795,6 @@ spi2: spi@988000 { reg = <0 0x00988000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -852,8 +834,6 @@ spi3: spi@98c000 { reg = <0 0x0098c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -880,8 +860,6 @@ spi4: spi@990000 { reg = <0 0x00990000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -908,8 +886,6 @@ spi5: spi@994000 { reg = <0 0x00994000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -936,8 +912,6 @@ spi6: spi@998000 { reg = <0 0x00998000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -977,8 +951,6 @@ spi7: spi@99c000 { reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1018,8 +990,6 @@ spi8: spi@a80000 { reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1046,8 +1016,6 @@ spi9: spi@a84000 { reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1074,8 +1042,6 @@ spi10: spi@a88000 { reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1102,8 +1068,6 @@ spi11: spi@a8c000 { reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1130,8 +1094,6 @@ spi12: spi@a90000 { reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1171,8 +1133,6 @@ spi13: spi@a94000 { reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -2983,123 +2943,223 @@ config { }; }; - qup_spi0_default: qup-spi0-default { + qup_spi0_cs: qup-spi0-cs { + pins = "gpio31"; + function = "qup0"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio28", "gpio29", - "gpio30", "gpio31"; + "gpio30"; function = "qup0"; }; - qup_spi1_default: qup-spi1-default { + qup_spi1_cs: qup-spi1-cs { + pins = "gpio7"; + function = "qup1"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk { pins = "gpio4", "gpio5", - "gpio6", "gpio7"; + "gpio6"; function = "qup1"; }; - qup_spi2_default: qup-spi2-default { + qup_spi2_cs: qup-spi2-cs { + pins = "gpio118"; + function = "qup2"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { pins = "gpio115", "gpio116", - "gpio117", "gpio118"; + "gpio117"; function = "qup2"; }; - qup_spi3_default: qup-spi3-default { + qup_spi3_cs: qup-spi3-cs { + pins = "gpio122"; + function = "qup3"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { pins = "gpio119", "gpio120", - "gpio121", "gpio122"; + "gpio121"; function = "qup3"; }; - qup_spi4_default: qup-spi4-default { + qup_spi4_cs: qup-spi4-cs { + pins = "gpio11"; + function = "qup4"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { pins = "gpio8", "gpio9", - "gpio10", "gpio11"; + "gpio10"; function = "qup4"; }; - qup_spi5_default: qup-spi5-default { + qup_spi5_cs: qup-spi5-cs { + pins = "gpio15"; + function = "qup5"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { pins = "gpio12", "gpio13", - "gpio14", "gpio15"; + "gpio14"; function = "qup5"; }; - qup_spi6_default: qup-spi6-default { + qup_spi6_cs: qup-spi6-cs { + pins = "gpio19"; + function = "qup6"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { pins = "gpio16", "gpio17", - "gpio18", "gpio19"; + "gpio18"; function = "qup6"; }; - qup_spi7_default: qup-spi7-default { + qup_spi7_cs: qup-spi7-cs { + pins = "gpio23"; + function = "qup7"; + }; + + qup_spi7_data_clk: qup-spi7-data-clk { pins = "gpio20", "gpio21", - "gpio22", "gpio23"; + "gpio22"; function = "qup7"; }; - qup_spi8_default: qup-spi8-default { + qup_spi8_cs: qup-spi8-cs { + pins = "gpio27"; + function = "qup8"; + }; + + qup_spi8_data_clk: qup-spi8-data-clk { pins = "gpio24", "gpio25", - "gpio26", "gpio27"; + "gpio26"; function = "qup8"; }; - qup_spi9_default: qup-spi9-default { + qup_spi9_cs: qup-spi9-cs { + pins = "gpio128"; + function = "qup9"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { pins = "gpio125", "gpio126", - "gpio127", "gpio128"; + "gpio127"; function = "qup9"; }; - qup_spi10_default: qup-spi10-default { + qup_spi10_cs: qup-spi10-cs { + pins = "gpio132"; + function = "qup10"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { pins = "gpio129", "gpio130", - "gpio131", "gpio132"; + "gpio131"; function = "qup10"; }; - qup_spi11_default: qup-spi11-default { + qup_spi11_cs: qup-spi11-cs { + pins = "gpio63"; + function = "qup11"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { pins = "gpio60", "gpio61", - "gpio62", "gpio63"; + "gpio62"; function = "qup11"; }; - qup_spi12_default: qup-spi12-default { + qup_spi12_cs: qup-spi12-cs { + pins = "gpio35"; + function = "qup12"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { pins = "gpio32", "gpio33", - "gpio34", "gpio35"; + "gpio34"; function = "qup12"; }; - qup_spi13_default: qup-spi13-default { + qup_spi13_cs: qup-spi13-cs { + pins = "gpio39"; + function = "qup13"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { pins = "gpio36", "gpio37", - "gpio38", "gpio39"; + "gpio38"; function = "qup13"; }; - qup_spi14_default: qup-spi14-default { + qup_spi14_cs: qup-spi14-cs { + pins = "gpio43"; + function = "qup14"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { pins = "gpio40", "gpio41", - "gpio42", "gpio43"; + "gpio42"; function = "qup14"; }; - qup_spi15_default: qup-spi15-default { + qup_spi15_cs: qup-spi15-cs { + pins = "gpio47"; + function = "qup15"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { pins = "gpio44", "gpio45", - "gpio46", "gpio47"; + "gpio46"; function = "qup15"; }; - qup_spi16_default: qup-spi16-default { + qup_spi16_cs: qup-spi16-cs { + pins = "gpio51"; + function = "qup16"; + }; + + qup_spi16_data_clk: qup-spi16-data-clk { pins = "gpio48", "gpio49", - "gpio50", "gpio51"; + "gpio50"; function = "qup16"; }; - qup_spi17_default: qup-spi17-default { + qup_spi17_cs: qup-spi17-cs { + pins = "gpio55"; + function = "qup17"; + }; + + qup_spi17_data_clk: qup-spi17-data-clk { pins = "gpio52", "gpio53", - "gpio54", "gpio55"; + "gpio54"; function = "qup17"; }; - qup_spi18_default: qup-spi18-default { + qup_spi18_cs: qup-spi18-cs { + pins = "gpio59"; + function = "qup18"; + }; + + qup_spi18_data_clk: qup-spi18-data-clk { pins = "gpio56", "gpio57", - "gpio58", "gpio59"; + "gpio58"; function = "qup18"; }; - qup_spi19_default: qup-spi19-default { + qup_spi19_cs: qup-spi19-cs { + pins = "gpio3"; + function = "qup19"; + }; + + qup_spi19_data_clk: qup-spi19-data-clk { pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + "gpio2"; function = "qup19"; }; From patchwork Wed Feb 10 13:34:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12080873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C3A9C433E0 for ; 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Wed, 10 Feb 2021 05:36:42 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id c8sm332629lfb.168.2021.02.10.05.36.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 05:36:41 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v4 3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS Date: Wed, 10 Feb 2021 16:34:57 +0300 Message-Id: <20210210133458.1201066-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> References: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Provide pinctrl entries for SPI controllers using the same CS pin but in GPIO mode. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 5571324641f0..aa6bad0b33ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2948,6 +2948,11 @@ qup_spi0_cs: qup-spi0-cs { function = "qup0"; }; + qup_spi0_cs_gpio: qup-spi0-cs-gpio { + pins = "gpio31"; + function = "gpio"; + }; + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio28", "gpio29", "gpio30"; @@ -2959,6 +2964,11 @@ qup_spi1_cs: qup-spi1-cs { function = "qup1"; }; + qup_spi1_cs_gpio: qup-spi1-cs-gpio { + pins = "gpio7"; + function = "gpio"; + }; + qup_spi1_data_clk: qup-spi1-data-clk { pins = "gpio4", "gpio5", "gpio6"; @@ -2970,6 +2980,11 @@ qup_spi2_cs: qup-spi2-cs { function = "qup2"; }; + qup_spi2_cs_gpio: qup-spi2-cs-gpio { + pins = "gpio118"; + function = "gpio"; + }; + qup_spi2_data_clk: qup-spi2-data-clk { pins = "gpio115", "gpio116", "gpio117"; @@ -2981,6 +2996,11 @@ qup_spi3_cs: qup-spi3-cs { function = "qup3"; }; + qup_spi3_cs_gpio: qup-spi3-cs-gpio { + pins = "gpio122"; + function = "gpio"; + }; + qup_spi3_data_clk: qup-spi3-data-clk { pins = "gpio119", "gpio120", "gpio121"; @@ -2992,6 +3012,11 @@ qup_spi4_cs: qup-spi4-cs { function = "qup4"; }; + qup_spi4_cs_gpio: qup-spi4-cs-gpio { + pins = "gpio11"; + function = "gpio"; + }; + qup_spi4_data_clk: qup-spi4-data-clk { pins = "gpio8", "gpio9", "gpio10"; @@ -3003,6 +3028,11 @@ qup_spi5_cs: qup-spi5-cs { function = "qup5"; }; + qup_spi5_cs_gpio: qup-spi5-cs-gpio { + pins = "gpio15"; + function = "gpio"; + }; + qup_spi5_data_clk: qup-spi5-data-clk { pins = "gpio12", "gpio13", "gpio14"; @@ -3014,6 +3044,11 @@ qup_spi6_cs: qup-spi6-cs { function = "qup6"; }; + qup_spi6_cs_gpio: qup-spi6-cs-gpio { + pins = "gpio19"; + function = "gpio"; + }; + qup_spi6_data_clk: qup-spi6-data-clk { pins = "gpio16", "gpio17", "gpio18"; @@ -3025,6 +3060,11 @@ qup_spi7_cs: qup-spi7-cs { function = "qup7"; }; + qup_spi7_cs_gpio: qup-spi7-cs-gpio { + pins = "gpio23"; + function = "gpio"; + }; + qup_spi7_data_clk: qup-spi7-data-clk { pins = "gpio20", "gpio21", "gpio22"; @@ -3036,6 +3076,11 @@ qup_spi8_cs: qup-spi8-cs { function = "qup8"; }; + qup_spi8_cs_gpio: qup-spi8-cs-gpio { + pins = "gpio27"; + function = "gpio"; + }; + qup_spi8_data_clk: qup-spi8-data-clk { pins = "gpio24", "gpio25", "gpio26"; @@ -3047,6 +3092,11 @@ qup_spi9_cs: qup-spi9-cs { function = "qup9"; }; + qup_spi9_cs_gpio: qup-spi9-cs-gpio { + pins = "gpio128"; + function = "gpio"; + }; + qup_spi9_data_clk: qup-spi9-data-clk { pins = "gpio125", "gpio126", "gpio127"; @@ -3058,6 +3108,11 @@ qup_spi10_cs: qup-spi10-cs { function = "qup10"; }; + qup_spi10_cs_gpio: qup-spi10-cs-gpio { + pins = "gpio132"; + function = "gpio"; + }; + qup_spi10_data_clk: qup-spi10-data-clk { pins = "gpio129", "gpio130", "gpio131"; @@ -3069,6 +3124,11 @@ qup_spi11_cs: qup-spi11-cs { function = "qup11"; }; + qup_spi11_cs_gpio: qup-spi11-cs-gpio { + pins = "gpio63"; + function = "gpio"; + }; + qup_spi11_data_clk: qup-spi11-data-clk { pins = "gpio60", "gpio61", "gpio62"; @@ -3080,6 +3140,11 @@ qup_spi12_cs: qup-spi12-cs { function = "qup12"; }; + qup_spi12_cs_gpio: qup-spi12-cs-gpio { + pins = "gpio35"; + function = "gpio"; + }; + qup_spi12_data_clk: qup-spi12-data-clk { pins = "gpio32", "gpio33", "gpio34"; @@ -3091,6 +3156,11 @@ qup_spi13_cs: qup-spi13-cs { function = "qup13"; }; + qup_spi13_cs_gpio: qup-spi13-cs-gpio { + pins = "gpio39"; + function = "gpio"; + }; + qup_spi13_data_clk: qup-spi13-data-clk { pins = "gpio36", "gpio37", "gpio38"; @@ -3102,6 +3172,11 @@ qup_spi14_cs: qup-spi14-cs { function = "qup14"; }; + qup_spi14_cs_gpio: qup-spi14-cs-gpio { + pins = "gpio43"; + function = "gpio"; + }; + qup_spi14_data_clk: qup-spi14-data-clk { pins = "gpio40", "gpio41", "gpio42"; @@ -3113,6 +3188,11 @@ qup_spi15_cs: qup-spi15-cs { function = "qup15"; }; + qup_spi15_cs_gpio: qup-spi15-cs-gpio { + pins = "gpio47"; + function = "gpio"; + }; + qup_spi15_data_clk: qup-spi15-data-clk { pins = "gpio44", "gpio45", "gpio46"; @@ -3124,6 +3204,11 @@ qup_spi16_cs: qup-spi16-cs { function = "qup16"; }; + qup_spi16_cs_gpio: qup-spi16-cs-gpio { + pins = "gpio51"; + function = "gpio"; + }; + qup_spi16_data_clk: qup-spi16-data-clk { pins = "gpio48", "gpio49", "gpio50"; @@ -3135,6 +3220,11 @@ qup_spi17_cs: qup-spi17-cs { function = "qup17"; }; + qup_spi17_cs_gpio: qup-spi17-cs-gpio { + pins = "gpio55"; + function = "gpio"; + }; + qup_spi17_data_clk: qup-spi17-data-clk { pins = "gpio52", "gpio53", "gpio54"; @@ -3146,6 +3236,11 @@ qup_spi18_cs: qup-spi18-cs { function = "qup18"; }; + qup_spi18_cs_gpio: qup-spi18-cs-gpio { + pins = "gpio59"; + function = "gpio"; + }; + qup_spi18_data_clk: qup-spi18-data-clk { pins = "gpio56", "gpio57", "gpio58"; @@ -3157,6 +3252,11 @@ qup_spi19_cs: qup-spi19-cs { function = "qup19"; }; + qup_spi19_cs_gpio: qup-spi19-cs-gpio { + pins = "gpio3"; + function = "gpio"; + }; + qup_spi19_data_clk: qup-spi19-data-clk { pins = "gpio0", "gpio1", "gpio2"; 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Wed, 10 Feb 2021 05:36:47 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v4 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS Date: Wed, 10 Feb 2021 16:34:58 +0300 Message-Id: <20210210133458.1201066-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> References: <20210210133458.1201066-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On the GENI SPI controller is is not very efficient if the chip select line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 638231f48388..f18c703d024a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -953,7 +953,8 @@ codec { &spi0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2518fd"; @@ -1356,7 +1357,7 @@ &vamacro { }; /* PINCTRL - additions to nodes defined in sm8250.dtsi */ -&qup_spi0_cs { +&qup_spi0_cs_gpio { drive-strength = <6>; bias-disable; };