From patchwork Wed Feb 10 18:55:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 12081631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 604D4C433E0 for ; Wed, 10 Feb 2021 18:56:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 159CE60C41 for ; Wed, 10 Feb 2021 18:56:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 159CE60C41 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qMTUMA26S58B87LP/QyJmLh/KzcT+EcZHosBTU8JdVM=; b=F3HbicYvfkQPAKqHNfu2XOgf6 NWOhT6kdQyRViWAMmlJnsZZu/e7nDJ5/DtrNqnBQL5Y0NCRjMwjvBwgVKSJYLkHksgMBl88CzMMz9 fbB3tB6IYNJa0XKNuQsJZlDkKcLXLWiBxcHrzy4YEKoFjeWJV3cEwHC7aMjtn5ikbWKQgoWbpzz3h /s9Y36hi3FfPR+BX59gAu6V6/w1sMijt10QRASrQf354LaU57hEx0tAzEPYRhKR03c/Y+ai24Z+CJ +Yn2f79aDpnxcb0/7Gtldk7GoPc9sHU/r25ZnJ/FXLTLfzHTb7JUjZ8X/JFJathvyGRDchVWDrV2z q36Kbm7jA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9ueV-0001m4-Lk; Wed, 10 Feb 2021 18:55:51 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9ueR-0001kb-5n for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2021 18:55:48 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id C57AA64E2E; Wed, 10 Feb 2021 18:55:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612983346; bh=WPn3FnII9y1zOCkNwPUqBpfLuu67gBwkRyG3OURqgF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Otn+Z9oqTklghtv/HpjyklE5QeNV7DwZOdXcryeCqc5Ho9JOjHwlw+NryN2bC2OiO 6Czvo40IXAv3U+XHwGXo4sNw42VTXQZB34iikf1zuHVF3lveYWxQPsr3yXOEc+prqz EIMIMRjkxiLJSU671ZefwDOXJJT1sa64KIvrJBUzkR7CPwsDiQiYoECKF2GE0llpO1 q9/fL7PiGbhzABpckvWpPOiKe/hIp/U++LC8iBUPDDxz6EcOJFl5SkI5ub8zArZMt5 q3TKnate0qY9fpkQk8oc2wfAd2KY0dZ4RTwJ1B85jKsCzJhc8Bm3WavNjq619W13y/ 2N8dPUOhdNF2A== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/3] ARM: cache-v7: add missing ISB after cache level selection Date: Wed, 10 Feb 2021 19:55:30 +0100 Message-Id: <20210210185532.8425-2-ardb@kernel.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210185532.8425-1-ardb@kernel.org> References: <20210210185532.8425-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_135547_562144_70AF2FEB X-CRM114-Status: GOOD ( 10.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A write to CCSELR needs to complete before its results can be observed via CCSIDR. So add a ISB to ensure that this is the case. Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/mm/cache-v7.S | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index dc8f152f3556..307f381eee71 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -38,9 +38,10 @@ icache_size: * procedures. */ ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR + isb + mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR movw r1, #0x7fff and r2, r1, r0, lsr #13 From patchwork Wed Feb 10 18:55:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 12081635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D50C433E6 for ; Wed, 10 Feb 2021 18:57:00 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53BED60C41 for ; Wed, 10 Feb 2021 18:57:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53BED60C41 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IhcfEWJNu1z6OnpiCcOofvsJnRka9RyytKJokHFKG70=; b=ZIF8YnYOuqsAJ3Mde7IqfhSaN UEqXu+5s2vOJ2M2v+QsJwzHBNGTjq2uxYVb0A/jB071SsVJ1zt1N76oDUi/l1TrSMCmGvl5jxVuUz cZNv7OCB6/+YP7jguTef3jA7P7FGtugJpPDbj8CnFbQEvTP7N2hf4hjxtZcxk2QUjaX3txUsN1dZ4 lRvT6Eax9/YfYiReSvNFi6cq30qRsXty+RgpiCioHHkXoEzoO2FdQf9+9ZNu23iZV1hgF+RF2XCP+ khJqSWzU53Iu03L+DDq9/MwCfJP++27c2maFe+mIhxEz2ELp3XXvZr8Otcf11Y0pR5MoP35doIaBH z+qtsym6A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9uea-0001nJ-Ed; Wed, 10 Feb 2021 18:55:56 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9ueT-0001lF-7t for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2021 18:55:50 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1AF0264E3B; Wed, 10 Feb 2021 18:55:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612983348; bh=81PR4MCGDuJyKoWR2LSx0GWPA1ftrT/kJVfSHoylZwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hhlRzL962xx/nTdw+Uy7Elb2i2YR9vRmtNIxG9Iih/GFwYFEKKwoMNf62Uazg3Zd2 bpI+IqyInHNzb9gX3JZe7kE2VmG5MjM9W7poSk7ERdOTW56NApsHhv3IQgKgKaczNj Y0anIVuV0+hzDVVLoBx5pnmFkWIoRh13bJb1QdrsvVqZwLqyL2kJgP6v32OPMYNejQ D3ButEyhpQAmUjNJ8CPKkL9J1qRYlncQnPYL8kPfxh8kWDqfCoBBK7HQZ9ATeRYTIo 69tvcZiAuk+GD1U9XH6s+JK5W0YNWv0smyTnNYledyFO9m+t7tDNHVAy+CTEUPhGn4 a7DMCcaMPL+mQ== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/3] ARM: cache-v7: refactor v7_invalidate_l1 to avoid clobbering r5/r6 Date: Wed, 10 Feb 2021 19:55:31 +0100 Message-Id: <20210210185532.8425-3-ardb@kernel.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210185532.8425-1-ardb@kernel.org> References: <20210210185532.8425-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_135549_469191_45DAADD7 X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The cache invalidation code in v7_invalidate_l1 can be tweaked to re-read the associativity from CCSIDR, and keep the set/way identifier component in a single register that is assigned in the outer loop. This way, we need 2 registers less. Given that the number of sets is typically much larger than the associativity, rearrange the code so that the outer loop has the fewer number of iterations, ensuring that the re-read of CCSIDR only occurs a handful of times in practice. Fix the whitespace while at it, and update the comment to indicate that this code is no longer a clone of anything else. Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/mm/cache-v7.S | 51 ++++++++++---------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 307f381eee71..76201ee9ee59 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -33,9 +33,8 @@ icache_size: * processor. We fix this by performing an invalidate, rather than a * clean + invalidate, before jumping into the kernel. * - * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. + * This function needs to be called for both secondary cores startup and + * primary core resume procedures. */ ENTRY(v7_invalidate_l1) mov r0, #0 @@ -43,32 +42,32 @@ ENTRY(v7_invalidate_l1) isb mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR - movw r1, #0x7fff - and r2, r1, r0, lsr #13 + movw r3, #0x3ff + and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] + clz r1, r3 @ WayShift + mov r2, #1 + mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] + movs r1, r2, lsl r1 @ #1 shifted left by same amount + moveq r1, #1 @ r1 needs value > 0 even if only 1 way - movw r1, #0x3ff + and r2, r0, #0x7 + add r2, r2, #4 @ SetShift - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets +1: movw r4, #0x7fff + and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp< X-Patchwork-Id: 12081639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25DAFC433E0 for ; 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bh=saIY2DTTd0sgs5miI73l/Q4THhOnfb0BS8L9/eGeRkU=; b=Xjk+WBrcl5PCSu83AljNA73af CgiiHG6NmZfnmiSlADi8xZxHtjmgut6ECRwCSaHE7LSDHXot0dQE9KvqWlwcVk0B0eI5e6ZtUhrO7 3kr94Uieb29HNmgzyk2XYrO8ATBTpKFjeonbuW2AG8dHCv8shbUnGiEJDkWEln/lNNB3JrppkMAFJ AH0ybBCfZ6rZ7YFi9H1UICEIEy/srO4sHw9u58usVum/+I35FZQeKMFV9n/B1DZdH0L8Ns3gJdY8g SUk35i593z6RHpEaWPT/ocQEWBturD4ROjY3B24KBdMV64R5spptylbOSPX5usitmhuUOZiQlBxV0 97Ppl7Lkg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9uec-0001nh-Fk; Wed, 10 Feb 2021 18:55:58 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9ueV-0001m7-MP for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2021 18:55:53 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3395060C41; Wed, 10 Feb 2021 18:55:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612983351; bh=myRBRdz/Yt6iPpx3WSXm960tD4KCzY2ooTgvFtDf5mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S/bKMnM8xg/Oow1g6k5Fs8Jov2GS33wMFyrKoOtl/hNNBX0AUbPzfryMPOuAzYgx4 /PyVzzUx2ld04T6/5zEcyc3N8C6sYWzgbYsBhK9YuTRVPOToSBdpvU+LtHa1EN39AI LBsUvG6FrZhYufenqQHOdT69+g9DLetP+tM2uHCberIFeosH/Q4ySFrEmuoxOgbcNQ n03fB3TOnnLbXFW3WpSmz5rsIMpyr7Cwnbrp5l1Qzc6s3T/B1pKNZaqZCzpnxx3FRp 4Dh+MYOAbITqbZwmmm+FXxlA4pn6YYu3dw95Jk+4rm01rmryUqy7QQkIfH/CaIn2V6 D+f7PXXp60BIw== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/3] ARM: cache-v7: get rid of mini-stack Date: Wed, 10 Feb 2021 19:55:32 +0100 Message-Id: <20210210185532.8425-4-ardb@kernel.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210185532.8425-1-ardb@kernel.org> References: <20210210185532.8425-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_135551_928592_21F91DAE X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Pitre , Marc Zyngier , Linus Walleij , Russell King , kernel-team@android.com, Ard Biesheuvel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have reduced the number of registers that we need to preserve when calling v7_invalidate_l1 from the boot code, we can use scratch registers to preserve the remaining ones, and get rid of the mini stack entirely. This works around any issues regarding cache behavior in relation to the uncached accesses to this memory, which is hard to get right in the general case (i.e., both bare metal and under virtualization) While at it, switch v7_invalidate_l1 to using ip as a scratch register instead of r4. This makes the function AAPCS compliant, and removes the need to stash r4 in ip across the call. Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/memory.h | 15 -------- arch/arm/mm/cache-v7.S | 10 ++--- arch/arm/mm/proc-v7.S | 39 +++++++++----------- 3 files changed, 23 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 2f841cb65c30..a711322d9f40 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -150,21 +150,6 @@ extern unsigned long vectors_base; */ #define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET) -#ifdef CONFIG_XIP_KERNEL -/* - * When referencing data in RAM from the XIP region in a relative manner - * with the MMU off, we need the relative offset between the two physical - * addresses. The macro below achieves this, which is: - * __pa(v_data) - __xip_pa(v_text) - */ -#define PHYS_RELATIVE(v_data, v_text) \ - (((v_data) - PAGE_OFFSET + PLAT_PHYS_OFFSET) - \ - ((v_text) - XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) + \ - CONFIG_XIP_PHYS_ADDR)) -#else -#define PHYS_RELATIVE(v_data, v_text) ((v_data) - (v_text)) -#endif - #ifndef __ASSEMBLY__ /* diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 76201ee9ee59..830bbfb26ca5 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -53,12 +53,12 @@ ENTRY(v7_invalidate_l1) and r2, r0, #0x7 add r2, r2, #4 @ SetShift -1: movw r4, #0x7fff - and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] +1: movw ip, #0x7fff + and r0, ip, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] -2: mov r4, r0, lsl r2 @ NumSet << SetShift - orr r4, r4, r3 @ Reg = (Temp<